Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

• the present invention relates generally to spatial light modulators. More particularly, the present invention relates to improved resolution in microelectromechanical optical devices.
• SLM Spatial light modulators
• MEMS microelectromechanical systems technology
• GLV grating light valve
• DMD digital mirror device
• GLV grating light valve
• GLV grating light valve
• the GLN is used to modulate light intensity by electrostatic deflection of long thin microscopic optical structures ("ribbons") to create a diffraction grating.
• the electrostatic deflection is accomplished by applying a control voltage to the ribbon.
• half the ribbons remain in a fixed position, and the other half are deflected by distances of less than one quarter of a wavelength of the incident light by applying a voltage to the ribbons.
• the more the deflection the deeper the diffraction grating, and hence the more light is diffracted.
• a two dimensional display may be produced by reflecting a beam of light from the GLN and sweeping the beam across the display.
• a voltage proportional to the desired pixel value is applied to half the ribbons corresponding to the pixel (while the other half of the ribbons are fixed in position).
• a vertical column of pixels is generated by the GLN, and the pixel intensity is modulated as the beam is swept across the display horizontally to produce a two dimensional array of pixels.
• Each pixel is thus defined by GLN ribbons in the vertical dimension, and by the pixel time in the horizontal dimension.
• the pixel time and horizontal scan rate determine the horizontal pixel- width of the display.
• the GLN may be used to produce a row of pixels which is modulated as it is swept across the display vertically.
• the vertical resolution of a display produced by a GLN is determined by the number of ribbons and how they are combined to produce pixels. For example, Bloom discloses the use of 1920 ribbons, configured 6 per pixel to produce a 320-pixel display.
• a minimum of two ribbons per pixel is typically required, since the diffraction grating is produced by alternating fixed ribbons with deflecting ribbons.
• Fixed (“reference”) ribbons are tied to a bias voltage (typically ground), and deflecting ("active") ribbons are deflected by the application of a ribbon control voltage.
• bias voltage typically ground
• active deflecting
• different assignment of ribbons to pixels is possible, e.g. using 2, 4, 8, 10, or 12 ribbons per pixel. This assignment is defined by the electrical interconnection on the integrated circuit substrate, and is fixed at manufacturing time. Maximum resolution of a GLV can be obtained by connecting each ribbon pair to a separate interconnect pin. Such an approach is impractical for a high-resolution display, however, because a large number of interconnects would be required.
• 6,215,579 limits the amount of deflection of the ribbons to a small amount, such that the deflection is roughly proportional to the applied voltage.
• This approach allows direct control of grayscale values by applying an analog voltage directly to the groups of ribbons forming a pixel, but still suffers from the limitation that the assignment of ribbons to form a pixel must be fixed at manufacturing time.
• a row-column addressing scheme to reduce the number of interconnects required in a large pixel display is disclosed in U.S. Pat. No. 5,841,579, issued to Bloom et. al.
• the row-column addressing scheme disclosed is only applicable to a GLV operated in the non-linear (digital) mode since it relies on the hysteresis property that the ribbon will snap to the fully deflected position if a voltage exceeding a threshold is applied.
• half the required threshold voltage is applied to the row and half to the column corresponding to an addressed pixel. Only the addressed pixel will have the full voltage applied (and snap to the deflected position); all other pixels in the row and column will deflect only slightly. This slight deflection of the non-addressed pixels can result in some reduction in the contrast of the display, as noted by Bloom.
• the invention includes a system for singularly controlling individual microscopic optical structures of a MEMS optical device with individual pixel values.
• the individual pixel values are generated by a pixel source and are to be substantially simultaneously applied to the individual microscopic optical structures.
• the system comprises a multiplexing circuit, an interconnect, and a demultiplexing circuit.
• the multiplexing circuit is configured to accept individual pixel values from the pixel value source and create a multiplexed pixel stream which is communicated to the demultiplexing circuit.
• the demultiplexing circuit is configured to extract the individual pixel values from the multiplexed pixel stream. The individual pixel values may then be substantially simultaneously applied to the individual microscopic optical structures according to a defined mapping.
• Another embodiment of the invention includes a controller for providing singular control of individual microscopic optical structures of a MEMS optical device.
• the controller includes a shared interconnect which is configured to accept a multiplexed stream of individual pixel values and at least one mapper which is configured to extract individual pixel values from the stream and substantially simultaneously apply the individual values to the individual microscopic optical structures according to a configurable mapping.
• Another embodiment of the invention includes a driver for providing singular control of individual microscopic optical structures of a MEMS optical device with pixel values for substantially simultaneous application to the individual microscopic optical structures.
• the driver includes at least one multiplexing circuit which accepts at least two individual pixel values and multiplexes the individual pixel values into a single stream which is communicated to the MEMS optical device via at least one shared interconnect
• Another embodiment of the invention includes a method for singularly controlling microscopic optical structures of a MEMS optical device by sharing a single - interconnect for communicating at least two individual pixel value designated for simultaneous application to the microscopic optical structures.
• Another embodiment of the invention includes a method for displaying an image with adjustable resolution when modulating a light beam with a MEMS optical devices. The method includes sharing a single interconnect for communicating the pixel values, mapping the individual pixel values to at least one microscopic optical structure, and varying the mapping to provide different display resolutions.
• Another embodiment of the invention includes a method for non-linear image mapping.
• the method includes sharing a single interconnect for communicating the pixel values and mapping the pixel values to at least one microscopic optical structure to create non-uniform pixel sizes to compensate for distortion of the image.
• FIG. 1 is a block diagram of an Ultra-High Resolution Light Modulation Control System in accordance with an embodiment of the present invention
• FIG. 2 is a block diagram of an Ultra-High Resolution Light Modulation Control System in accordance with another embodiment of the present invention
• FIG. 3 is a detailed block diagram of the multiplexing group of FIG. 2.
• FIG. 4 is a detailed block diagram of the demultiplexing group of FIG 2.
• FIG. 5 is a timing diagram of the operation of the Ultra-High Resolution Modulation Control System of FIG. 2.
• FIG. 6 is a detailed block diagram of an alternate configuration of the demultiplexing group of FIG 2.
• FIG. 7 is a detailed block diagram of yet another alternate configuration of the demultiplexing group of FIG. 2 FIG.
• FIG. 8 is a timing diagram of the operation of the Ultra-High Resolution Modulation Control System of FIG. 2 in a reduced resolution mode of operation.
• FIG. 9 is a depiction of using the present invention to compensate for image distortion in a projection system DETAILED DESCRIPTION
• multiplexing refers to any technique for combining two distinct electrical signals for communication through an electrical interface. It is also to be understood the term “demultiplexing” used herein refers to any corresponding technique for extracting the distinct electrical signals from a multiplexed signal. It is also to be understood the term “interconnect” refers to any structure for communication of an electrical signal, including, but not limited to, a bond wire of an integrated circuit assembly, a pin on an integrated circuit package, or a trace on a printed circuit board. As illustrated in FIG. 1, a system for ultra-high resolution light modulation using a MEMS optical device is indicated generally at 10, in accordance with the present invention.
• the system may include a multiplexing circuit 12, an interconnect 14, and a demultiplexing circuit 16.
• Multiplexing circuit 12 is configured to accept at least two pixel values 18 from a pixel value source 22, where the pixel values 18 are to be simultaneously applied to the individual microscopic optical structures 24 of the MEMS optical device (not shown).
• the pixel value source 22 may be, for example, a display system.
• pixel values 18 represent a column, row, or frame of image information to be displayed by application of the pixel values 18 to the individual microscopic optical structures 24 of the MEMS optical device.
• the pixel values 18 may be provided to the multiplexing circuit 12 in a variety of ways.
• the pixel values 18 may be provided in a parallel format, in a serial format, or using a hybrid of parallel and serial transfer, as discussed further below.
• the multiplexing circuit 12 creates a multiplexed stream of pixel values 20 from the pixel values 18.
• multiplexing circuit 12 may preferably create a multiplexed stream of pixel values 20 by sequentially outputting each pixel value 18.
• the multiplexed stream of pixel values is communicated via interconnect 14 to demultiplexing circuit 16.
• the demultiplexing circuit 16 extracts the individual pixel values 18 from the multiplexed stream of pixel values 20, which may then be applied to the corresponding individual microscopic optical structures 24 of the MEMS optical device.
• Demultiplexing circuit 16 may preferably be implemented by sampling the multiplexed stream of pixel values 20 at the appropriate times to extract the pixel values 18.
• a system for ultra-high resolution light modulation using a GLV type of MEMS optical device is indicated generally at 100, in accordance with another embodiment of the present invention.
• the system may include a driver chip 102 and a GLV chip 106 communicating through a plurality of interconnect pins 108.
• the driver chip 102 may further include a plurality of multiplexing groups 104 for accepting individual pixel values to be displayed 112, which are multiplexed together to produce a plurality of multiplexed analog pixel streams 120, which are communicated to the plurality of interconnect pins 108.
• the driver chip 102 may further contain a controller 122 connected to the multiplexing groups 104 via multiplexer control 124.
• the GLV chip 106 may include a plurality of demultiplexing groups 140.
• the GLV may further include input busses 150, connecting the demultiplexing groups 140 with interconnect pins 108.
• the GLV chip may further include a plurality of ribbons 158.
• the multiplexed analog pixel streams 120, provided by interconnect pins 108 to input busses 150, are processed by demultiplexing groups 140 to produce individual ribbon control voltages 162 which are applied to the ribbons 158.
• the GLV chip 106 may further include controller 160 that is connected to the demultiplexing groups 140 via a demultiplexing control bus 166 and switch control 164.
• FIG. 3 provides further detail of one particular implementation of the multiplexing groups 104 in accordance with the present invention.
• a multiplexing group 104 may contain registers 110 for accepting individual pixel values to be displayed 112.
• a multiplexing group 104 may further include a multiplexer 114 accepting and multiplexing groups of individual pixel values to be displayed 112 from groups of registers 110 to produce a multiplexed pixel stream 116.
• a multiplexing group 104 may further include an digital to analog converter 118 accepting multiplexed pixel stream 116 from the multiplexer 114 and converting the stream into a multiplexed analog pixel stream 120.
• the multiplexing order is determined by multiplexer control 124.
• Pixel values to be displayed 112 are written into registers 110 by the display system.
• the pixel values to be displayed 112 may be written to registers 110 one at a time, several at a time, or all at once, depending upon the needs of the display system.
• the display system could write four pixel values to be displayed 112 at a time into registers 110.
• pixel values could be provided by the display system as an already multiplexed stream of data, in which case registers 110 and multiplexer 114 could be eliminated from the multiplexing group 104.
• the sequence of pixel values to be displayed 112 that is output from the multiplexer 114 is determined by the controller 122.
• a 4352-pixel display height may be implemented with sixteen multiplexing groups 104, each multiplexing group 104 containing 272 registers 110.
• each multiplexing group 104 may multiplex 272 pixel values to be displayed 112 into a multiplexed pixel stream 116.
• the sixteen multiplexed pixel streams 116 are then communicated to the GLV via sixteen interconnect pins 108.
• the multiplexing order is controlled by controller 122 via multiplexer control 124.
• the first multiplexing group 104 may output pixel 1, 2, 3, etc. up to pixel 272.
• the second multiplexing group 104 may output pixels 273, 274, 275, etc. up to pixel 544.
• FIG. 5 provides a timing diagram example for multiplexing operation as just described. Line A of FIG.
• FIG. 4 provides further detail of one particular implementation of a demultiplexing group 140 in accordance with the present invention.
• a demultiplexing group 140 may contain switches 152 connected to input bus 150 and controlled by demultiplexer control bus 166. Switches 152 sample the multiplexed analog pixel stream 120 at the time determined by the demultiplexer control bus 166.
• a demultiplexing group 140 may further include voltage storage elements 154.
• voltage storage elements 154 may be implemented by a capacitor as shown here, those skilled in the art will recognize other that other techniques for storing a voltage may be used consistent with the present invention.
• switch 152 By briefly closing switch 152, the voltage on input bus 150 is impressed upon voltage storage element 154 creating a sample and hold.
• a multiplexing group 140 may further include switch 156 connected to voltage storage elements 154. The timing for switches 152a, 152b, and 156 is shown in FIG. 5. For a first pixel time (one vertical column of pixels in a horizontally swept display), controller 160 may sequentially close switches 152a at the correct times to impress a particular pixel control voltage onto the storage elements 154a.
• Each switch 152a in a demultiplexing group 140 is briefly closed during the time corresponding to one particular pixel as shown in lines C through E of FIG. 5.
• the controller 160 closes switch 152a only when the multiplexed analog pixel stream 120 is stable, crosstalk between pixels is avoided.
• the controller may then toggle switches 156 using switch control 164 to substantially simultaneously apply the individual pixel voltages held by voltage storage elements 154a to the individual ribbons 158 as shown in line J and K of FIG. 5.
• the individual pixel voltages will be held by voltage storage elements 154a for one pixel time, during which time the controller may begin demultiplexing a new set of pixel control voltages using switches 152b and voltage storage elements 154b as shown in lines F through H of FIG 5.
• Application of individual pixel control voltages to each individual ribbon may prove advantageous in applications requiring very high resolution, since the resolution is defined by a single ribbon.
• every other ribbon may be permanently tied to a bias voltage to create reference ribbons, and the other half controlled through the demultiplexing groups 140. Although this reduces the resolution of the display, it halves the amount of circuitry required in the multiplexing and demultiplexing groups.
• FIG. 6 provides detail of an alternative implementation of a demultiplexing group
• a reduction in the number of switches is obtained by the addition of amplifier 170 and elimination of switch 152b. While one set of pixel control voltages is being held by voltage storage elements 154b, the next set of pixel control voltages can be demultiplexed and stored in voltage storage elements 154a.
• FIG. 7 provides detail of yet another alternative implementation of a demultiplexing group 140 in accordance with the present invention.
• Ribbons 158 are connected in pairs (one active, one reference) to the sample and hold represented by switches 152, switches 156, and voltage storage elements 154.
• the ribbons 158 are connected to the sample and hold by switches 168.
• Switches 168 control which ribbon is active, while the other ribbon is tied to a bias voltage. This results in a net reduction in the number of switches and voltage storage elements while maintaining single ribbon resolution. Ribbons 158 might also be grouped differently.
• even numbered ribbons 158 maybe tied to one demultiplexing group 140, and odd numbered ribbons 158 may be tied to a different demultiplexing group 140; such a configuration would be useful to separate high speed control of active ribbons from low speed control of reference ribbons.
• some ribbons may be updated at a sub-pixel time shorter than the nominal pixel time to provide sub-pixel resolution.
• Various other similar configurations including permanently tying multiple ribbons to each individual ribbon control voltage 162, may also prove advantageous as will occur to one skilled in the art.
• the mapping of pixel values to be displayed 112 to the ribbons 158 is flexibly controlled.
• the demultiplexing groups 140 can be commanded by controller 160 to apply any individual pixel value extracted from the multiplexed analog pixel stream 120 any ribbon 158 connected to the multiplexing group 140.
• the present invention may be used to provide different display resolutions with a single manufactured configuration of the driver chip 102 and GLV chip 106 by varying the mapping.
• a 4352-pixel display may also be operated in lower resolution modes providing a 2176 or 1088-pixel display height.
• FIG. 8 illustrates a timing diagram for a 2176 pixel resolution mode of operation.
• the driver chip 102 operates similarly to the 4352-pixel resolution mode discussed previously, sequentially multiplexing groups of pixel values to be displayed 112 to produce a multiplexed analog pixel stream 120 as illustrated in lines A and B.
• the GLV chip 106 operates differently, however, as the controller 160 closes two switches 152a simultaneously for each pixel in order to extract each pixel voltage from the multiplexed analog pixel stream 120 twice as illustrated in lines C though H. Extracted pixel values are then applied substantially simultaneously to the ribbons 158, similarly to the 4352- pixel resolution mode, as illustrated in lines L and M. Operation in the 1088 pixel resolution mode of operation may be accomplished by the controller 160 closing four switches 152a simultaneously for each pixel to extract the same pixel voltage for four ribbons 158 . A mapping of pixel values to one or more ribbons 158 is therefore accomplished by the timing of how controller 160 closes switches 152. A driver chip 102 and GLV chip 106 pair can therefore implement a variety of resolution modes.
• a pixel may be composed of two ribbons, one reference and one active, and 1/2 pixel resolution provided by swapping the active and reference ribbons.
• the entire display may be a single pixel, mapping half the ribbons to the reference and half to active, all of the ribbons being provided the same ribbon control voltage.
• the mapping of pixels to ribbons may be different for different portions of the array.
• a display may provide higher resolution in the center where it is most needed and less resolution near the edges. This may be accomplished by mapping pixels at the center of the display to a relatively smaller number of ribbons and mapping pixels near the edges of the display to a relatively larger number of ribbons.
• Sub-pixel resolution may also be provided by shifting the mapping of pixels to ribbons by a number of ribbons less than the number of ribbons per pixel. Sub-pixel resolution may also be provided by applying new sets of ribbon control voltages 162 at a sub-pixel time shorter than the pixel time.
• the ultra-high resolution light modulation control system disclosed herein may be used to implement non-linear image mapping. For example, as illustrated in FIG. 9, a projection system using the ultra-high resolution light modulation control system of the present invention is illustrated generally at 400. Projector 402 projects an image onto a cylindrically curved wall 404.
• the mapping of pixels to microscopic optical structures is dynamically varied as the display is swept horizontally across the wall. Starting from one edge, the display uses a portion of the MEMS optical device, mapping each pixel to an appropriate number of microscopic optical structures. As the beam sweeps towards the center, additional microscopic optical structures are used, and each pixel mapped to a larger number of microscopic optical structures, so that when the beam is at the center of the wall, the full MEMS optical device is being used. As the beam sweeps towards the other edge, pixels are mapped to a smaller number of microscopic optical structures, and some microscopic optical structures disused. This appropriately shapes the image while maintaining an identical number of pixels throughout the image, producing the undistorted image 408.
• mapping of pixels to microscopic optical structures may be determined entirely by the controller 160, reducing the need for any external computational processing as required by prior art techniques.
• Table I illustrates a simple example of mapping for a 10 pixel display implemented with a 60 ribbon GLV.
• the even-numbered ribbons 2,4,6...60 are held constant at the reference voltage, and the odd-numbered ribbons 1,3,5... 59 are mapped to pixels to be displayed.
• the middle column shows the mapping of pixels to ribbons at the extreme edge of the screen, and the rightmost column shows the mapping of pixels to ribbons at the center of the screen.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)
• Transforming Electric Information Into Light Information (AREA)

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• 2003
  • 2003-07-10 US US10/617,145 patent/US6856449B2/en not_active Expired - Lifetime
• 2004
  • 2004-07-09 JP JP2006518927A patent/JP2007530981A/ja active Pending
  • 2004-07-09 CA CA002532063A patent/CA2532063A1/en not_active Abandoned
  • 2004-07-09 WO PCT/US2004/022008 patent/WO2005008313A1/en active Application Filing
  • 2004-07-09 EP EP04777842A patent/EP1644768A4/de not_active Withdrawn

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