EP1619785B1 - Converter circuit with voltage rise rate limitation - Google Patents

Abstract

A converter circuit has a DC voltage circuit (1) formed by two series-connected capacitors and a first (5) current rise limiting network (5) connected to a first main terminal (2) and a second current rise limiting network (10) with an inductance (11) and a resistance (12) connected to the second main terminal (3). A first voltage limiting network (15) is connected in parallel to a series circuit of the first and second power semiconductor switches (S1,S2) and to a diode of the first current limiting network (5). A second voltage limiting network (16) is connected in parallel to the series circuit of the third and fourth power semiconductor switches (S3,S4) and to the diode (14) of the second current limiting network (10).

Description

Technical area

The invention relates to the field of power electronics. It is based on a converter circuit according to the preamble of claim 1.

State of the art

Power semiconductor switches, in particular integrated thyristors with commutated drive electrode (IGCT), are currently being used increasingly in converter technology and in particular in converter circuits for switching three voltage levels. Such a converter circuit for switching three voltage levels is described in "Characterization of IGCTs for Series Connected Operation, Conference Record of the Annual Meeting of the IEEE Industry Applications Society, 2000, October". Therein, the converter circuit comprises a DC voltage circuit formed by two series-connected capacitors, wherein the DC voltage circuit has a first main terminal and a second main terminal and a partial terminal formed by the two adjacent and interconnected capacitors. The capacitance value of the two capacitors is usually the same chosen big. Between the first main terminal and the second main terminal is a DC voltage, between which the first main terminal and the sub-terminal, ie at one capacitor consequently half the DC voltage applied and between the sub-terminal and the second main terminal, that is on the other capacitor also half the DC voltage ,

Furthermore, the converter circuit has a first current increase limiting network, wherein an inductance and a resistance of the first current increase limiting network is connected to the first main terminal, a capacitance of the first current increase limiting network is connected to the resistor and to the partial terminal, and a diode of the first current increase limiting network is connected to the connection point of the resistor connected to the capacity. Furthermore, the converter circuit has a second current increase limiting network, wherein an inductance and a resistance of the second current increase limiting network is connected to the second main terminal, a capacitance of the second current increase limiting network is connected to the resistor and to the partial terminal, and a diode of the second current increase limiting network is connected to the connection point of the resistor connected to the capacity. In addition, a first, second, third, fourth, fifth and sixth bidirectional power semiconductor switch are provided, wherein the first, second, third and fourth power semiconductor switches are connected in series and the first power semiconductor switch with the inductance of the first current increase limiting network and the fourth power semiconductor switch with the Inductance of the second current increase limiting network is connected. The fifth and sixth power semiconductor switches are connected in series, the connection point of the fifth power semiconductor switch to the sixth power semiconductor switch being connected to the sub-terminal, the fifth power semiconductor switch being connected to the connection point of the first power semiconductor switch to the second power semiconductor switch, and the sixth power semiconductor switch being connected to the connection point of the third Power semiconductor switch is connected to the fourth power semiconductor switch.

To the first, second, third, fourth, fifth and sixth controllable bidirectional power semiconductor switch, a series circuit of a resistor is connected in parallel with a capacitor in each case, wherein the capacitance has a value of typically 500nF and the Resistor has a value typically 10hm. The respective series connection of the resistor with the capacity with the above-mentioned value-based design serves to achieve a balanced voltage distribution at the associated power semiconductor switch at switching state transitions, ie in the transition from the on state to the off state or from the off state to the on state.

A problem with a converter circuit according to the "Characterization of IGCTs for Series Connected Operation, Conference Record of the Annual Meeting of the IEEE Industry Applications Society, 2000, October" is that the described value-based design of the resistance and the capacity of the series circuit in the shutdown of the associated power semiconductor switch a high voltage rise at the same time high current occurs, which leads to very high turn-off and dynamic elevations of the electric Fel in the power semiconductor switch. However, such turn-off losses and field overshoots on the respective power semiconductor switch can damage or even destroy it.

EP 0 321 865 describes a converter circuit where the fifth and sixth power semiconductor switches are replaced by diodes. These diodes allow the current to lead only one direction. EP 1 047 180 describes a converter circuit having capacitances used as the voltage slew limiting network for each line semiconductor switch.

Presentation of the invention

The object of the invention is therefore to develop a converter circuit of the type mentioned in such a way that the turn-off of power semiconductor switches of the converter circuit can be minimized. This object is solved by the features of claim 1. In the dependent claims advantageous developments of the invention are given.

The converter circuit according to the invention comprises a DC voltage circuit formed by two capacitors connected in series, wherein the DC voltage circuit has a first main terminal and a second main terminal and a partial terminal formed by the two adjacent and interconnected capacitors. Furthermore, a first current increase limiting network is provided, wherein an inductance and a resistance of the first current increase limiting network is connected to the first main terminal, a capacitance of the first current increase limiting network is connected to the resistor and to the partial terminal, and a diode of the first current increase limiting network is connected to the connection point of the resistor with the capacitance. Furthermore, the inventive converter circuit has a second current increase limiting network, wherein an inductance and a resistance of the second current increase limiting network is connected to the second main terminal, a capacitance of the second current increase limiting network is connected to the resistor and to the partial terminal and a diode of the second current increase limiting network is connected to the connection point of the second current increase limiting network Resistor connected to capacity. In addition, a first, second, third, fourth, fifth and sixth bidirectional power semiconductor switch are provided, wherein the first, second, third and fourth power semiconductor switches are connected in series and the first power semiconductor switch with the inductance of the first current increase limiting network and the fourth power semiconductor switch with the Inductance of the second current increase limiting network is connected. The fifth and sixth power semiconductor switches are connected in series, the connection point of the fifth power semiconductor switch to the sixth power semiconductor switch being connected to the sub-terminal, the fifth power semiconductor switch being connected to the connection point of the first power semiconductor switch to the second power semiconductor switch, and the sixth power semiconductor switch being connected to the connection point of the third Power semiconductor switch is connected to the fourth power semiconductor switch. According to the invention, a first voltage increase limiting network is connected in parallel with the series connection of the first and second power semiconductor switches and connected to the diode of the first current increase limiting network. Furthermore, according to the invention, a second voltage increase limiting network is connected in parallel with the series connection of the third and fourth power semiconductor switches and connected to the diode of the second current increase limiting network.

Advantageously, it is possible by means of the inventive first and second Spannungsanstiegsbegrenzungsnetzwerks to limit the voltage increase during the shutdown of the first, second, third, fourth, fifth and sixth power semiconductor switch, resulting in a significant reduction of Abschaltverluste and a significant increase in the maximum turn-off current in the power semiconductor switch leads. The respective power semiconductor switch can thereby be largely protected against damage or destruction.

These and other objects, advantages and features of the present invention will become more apparent from the following detailed description of preferred embodiments of the invention taken in conjunction with the accompanying drawings.

Brief description of the drawings

Fig. 1

eine erste Ausführungsform einer erfindungsgemässen Umrichterschaltung und

Fig. 2

eine zweite Ausführungsform der erfindungsgemässen Umrichterschaltung.

Show it:

Fig. 1

a first embodiment of an inventive converter circuit and

Fig. 2

A second embodiment of the inventive converter circuit.

The reference numerals used in the drawings and their meaning are listed in the list of reference numerals. Basically, the same parts are provided with the same reference numerals in the figures. The described embodiments are exemplary of the subject invention and have no limiting effect.

Ways to carry out the invention

In Fig. 1 a first embodiment of the inventive converter circuit is shown. The converter circuit according to Fig. 1 comprises a DC voltage circuit 1 formed by two capacitors connected in series, the DC voltage circuit 1 having a first main terminal 2 and a second main terminal 3 and a partial terminal 4 formed by the two adjacent and interconnected capacitors. Furthermore, in the inventive converter circuit according to Fig. 1 a first current increase limiting network 5 is provided, according to Fig. 1 an inductor 6 and a resistor 7 of the first current increase limiting network 5 is connected to the first main terminal 2, a capacitor 8 of the first current increase limiting network 5 is connected to the resistor 7 and to the partial terminal 4, and a diode 9 of the first current increase limiting network 5 is connected to the connection point of the resistor 7 is connected to the capacity 8. Furthermore, according to Fig. 1 a second current increase limiting network 10 is provided, wherein an inductor 11 and a resistor 12 of the second current increase limiting network 10 is connected to the second main terminal 3, a capacitor 13 of the second current increase limiting network 10 is connected to the resistor 12 and to the partial terminal 4 and a diode 14 of the second Current increase limiting network 10 is connected to the connection point of the resistor 12 to the capacitor 13. In addition, the converter circuit according to the invention has a first, second, third, fourth, fifth and sixth controllable bidirectional power semiconductor switches S1, S2, S3, S4, S5, S6. The fifth and sixth power semiconductor switches S5 and S6 form an active clamp switching group. Preferably, the first, second, third, fourth, fifth and sixth controllable bidirectional power semiconductor switches S1, S2, S3, S4, S5, S6 are each formed by an integrated thyristor with commutated drive electrode and by a diode connected in anti-parallel to the thyristor.

According to Fig. 1 the first, second, third and fourth power semiconductor switches S1, S2, S3, S4 are connected in series and the first power semiconductor switch S1 is connected to the inductance 6 of the first current increase limiting network 5 and the fourth power semiconductor switch S4 to the inductance 11 of the second current increase limiting network 10. Further, the fifth and sixth power semiconductor switches S5, S6 are connected in series, the connection point of the fifth power semiconductor switch S5 is connected to the sixth power semiconductor switch S6 to the sub-terminal 4, the fifth power semiconductor switch S6 is connected to the connection point of the first power semiconductor switch S1 to the second power semiconductor switch S2, and sixth power semiconductor switch S6 connected to the connection point of the third power semiconductor switch S3 to the fourth power semiconductor switch S4. According to the invention, a first voltage increase limiting network 15 is connected in parallel to the series connection of the first and second power semiconductor switches S1, S2 and connected to the diode 9 of the first current increase limiting network 5. Further, a second voltage increase limiting network 16 is connected in parallel with the series circuit of the third and fourth power semiconductor switches S3, S4 and connected to the diode 14 of the second current increase limiting network 10.

The two Spannungsanstiegsbegrenzungs networks 15, 16 cause at the shutdown of the first and second, third, fourth, fifth and sixth power semiconductor switch S1, S2, S3, S4, S5 and S6, that each a share of electricity in the capacitances 19 and 20 of the two Spannungsanstiegsbegrenzungsnetzwerke 15, 16th are driven, so that the voltage increase at the first and second, third, fourth, fifth and sixth power semiconductor switches S1, S2, S3, S4, S5 and S6 is limited. The limitation of the voltage rise advantageously leads to a significant reduction in the turn-off losses and to a significant increase in the maximum turn-off current at the respective power semiconductor switches S1, S2, S3, S4, S5, S6, whereby they can be largely protected against damage or destruction.

According to Fig. 1 For example, the first and second voltage increase limiting network 15, 16 are preferably each formed by a series connection of a diode 17, 18, a capacitor 19, 20 and a resistor 21, 22. The diode 9 of the first current increase limiting network 5 is after Fig. 1 is connected to the connection point of the diode 17 with the capacitance 19 of the first voltage increase limiting network 15. In particular, the diode 17 of the first voltage increase limiting network 15 is connected to the connection point of the first power semiconductor switch S1 to the inductance 6 of the first current increase limiting network 5. Furthermore, the diode 14 of the second current increase limiting network 10 is according to Fig. 1 is connected to the connection point of the diode 18 with the capacitance 20 of the second voltage increase limiting network 16. In particular, the diode 18 of the second voltage increase limiting network 16 is connected to the connection point of the fourth power semiconductor switch S4 with the inductance 11 of the second current increase limiting network 10.

According to Fig. 1 For example, the converter circuit according to the invention has a controllable short-circuit element 23, which is connected to the partial connection 4 and to the connection point of the second to the third power semiconductor switch S2, S3. The controllable short-circuit element 23 can thus be very easily integrated into the existing network of power semiconductor switches S1, S2, S3, S4, S5, S6 of the converter circuit, so that space can advantageously be saved. The controllable short-circuit element 23 is used in the event of a short circuit in one or more of the power semiconductor switches S1, S2, S3, S4, S5, S6 to cause a short-circuit current resulting from the short-circuit from the capacitors of the DC voltage circuit 1 is only very briefly over the short-circuited power semiconductor switch S1, S2, S3, S4, S5, S6 and then directed via the short-circuit element 23 to the partial connection 4, so that or the short-circuited power semiconductor switches S1, S2, S3, S4, S5 , S6 should not be further damaged, loaded or destroyed. The controllable short-circuit element 23 according to Fig. 1 Moreover, in the event of a short circuit at one or more phases of an electrical alternating voltage network connected to the converter circuit, a short circuit current from the phases caused by the short circuit is not or only with a small amplitude via the power semiconductor switches S1, S2, S3, S4, S5, S6 , in particular via the diodes of the power semiconductor switches S1, S2, S3, S4, S5, S6 flows, so that the power semiconductor switches S1, S2, S3, S4, S5, S6 no longer or not at all damaged, loaded or destroyed. Such a short-circuit current or fault current is directed in this case via the short-circuit element 17 to the partial connection 4. The short-circuit element 23 is then activated when a short-circuit current is detected by means of a detection device.

In Fig. 2 a second embodiment of the inventive converter circuit is shown. The second embodiment according to Fig. 2 differs from the first embodiment described in detail above Fig. 1 in that a controllable short-circuit element is provided, which is connected via an inductor 24 to the connection point of the second to the third power semiconductor switch S2, S3, wherein a series circuit of a resistor 25 with a capacitor 26 is connected in parallel to the drivable short-circuit element 23. The inductance 24 and series connection of the resistor 25 with the capacitance 26 are optional. The above-described interconnection of the inductor 24, the resistor 25 and the capacitor 26 provides when turning on the short-circuit element 23 a current increase limiting device, ie the current increase at power is limited, and when switching off the short-circuit element 23, a voltage increase limiting device, ie the voltage increase during shutdown is limited, is This controllable short-circuit element 23 according to Fig. 2 is used in the event of a short circuit at one or more phases of an electrical alternating voltage network connected to the converter circuit that a short circuit current caused by the short circuit from the phases is not or only with a small amplitude via the power semiconductor switches S1, S2, S3, S4, S5, S6, in particular via the diodes of the power semiconductor switches S1, S2, S3, S4, S5, S6 flows, so that the power semiconductor switches S1, S2, S3, S4, S5, S6 not further damaged or not at all, loaded or destroyed. The short-circuit element 23 is then activated when a short-circuit current is detected by means of a detection device, wherein the activatable short-circuit element 23 then short-circuits the phases connected to the short-circuit element 23.

The short-circuit element 23 after Fig. 1 and Fig. 2 is formed with advantage of two antiparallel connected controllable power semiconductors with respective pressure contact, such as disc thyristors or GTOs. The respective controllable power semiconductor switch of the activatable short-circuit element 23 can also be formed by an integrated thyristor with commutated drive electrode or by a triac.

According to Fig. 1 and Fig. 2 is connected in parallel with the series connection of the fifth and sixth power semiconductor switch S5, S6 a balancing resistor 27. The Symmetrierungswiderstand 27 is advantageously used, for example, in a shutdown of all power semiconductor switches S1, S2, S3, S4, S5, S6 to achieve a nearly symmetrical voltage distribution across the power semiconductor switch S1, S2, S3, S4, S5, S6 and thus individual power semiconductor switch S1 , S2, S3, S4, S5, S6 to protect against excessive voltages.

LIST OF REFERENCE NUMBERS

1

DC circuit

2

first main line

3

second main connection

4

part connection

5

first power rise limit network

6

Inductance of the first current rise limit network

7

Resistance of the first current rise limit network

8th

Capacity of the first river-access-limiting network

9

Diode of the first current rise limit network

10

second electricity increase limit network

11

Inductance of the second current rise limit network

12

Resistor of the second current rise limit network

13

Capacity of the second current increase limiting network

14

Diode of the second current rise limit network

15

first voltage increase limiting network

16

second voltage increase limiting network

17

Diode of the first voltage rise limiting network

18

Diode of the second voltage increase limiting network

19

Capacity of the first voltage rise limiting network

20

Capacity of the second voltage increase limiting network

21

Resistance of the first voltage rise limiting network

22

Resistance of the second voltage increase limiting network

23

Short-circuit element

24

inductance

25

resistance

26

capacity

27

Symmeterisation resistance

S1

first power semiconductor switch

S2

second power semiconductor switch

S3

third power semiconductor switch

S4

fourth power semiconductor switch

S5

fifth power semiconductor switch

S6

sixth power semiconductor switch

Claims (9)

1. Converter circuit having a DC voltage circuit (1) which is formed by two capacitors which are connected in series, the DC voltage circuit (1) comprising a first main connection (2) and a second main connection (3) and a partial connection (4) which is formed by the two adjacent capacitors which are connected to one another, having a first current rise limiting network (5), an inductance (6) and a resistor (7) of the first current rise limiting network (5) being connected to the first main connection (2), a capacitance (8) of the first current rise limiting network (5) being connected to the resistor (7) and to the partial connection (4), and a diode (9) of the first current rise limiting network (5) being connected to the junction point between the resistor (7) and the capacitance (8),
   having a second current rise limiting network (10), an inductance (11) and a resistor (12) of the second current rise limiting network (10) being connected to the second main connection (3), a capacitance (13) of the second current rise limiting network (10) being connected to the resistor (12) and to the partial connection (4), and a diode (14) of the second current rise limiting network (10) being connected to the junction point between the resistor (12) and the capacitance (13), having a first, a second, a third, a fourth, a fifth and a sixth drivable bidirectional power semiconductor switch (S1, S2, S3, S4, S5, S6), the first, second, third and fourth power semiconductor switches (S1, S2, S3, S4) being connected in series, and the first power semiconductor switch (S1) being connected to the inductance (6) of the first current rise limiting network (5), and the fourth power semiconductor switch (S4) being connected to the inductance (11) of the second current rise limiting network (10), and a first voltage rise limiting network (15) being connected in parallel with the series circuit comprising the first and second power semiconductor switches (S1, S2) and being connected to the diode (9) of the first current rise limiting network (5), and a second voltage rise limiting network (16) being connected in parallel with the series circuit comprising the third and fourth power semiconductor switches (S3, S4) and being connected to the diode (14) of the second current rise limiting network (10),
   characterized in that
   the fifth and sixth power semiconductor switches (S5, S6) are connected in series, the junction point between the fifth power semiconductor switch (S5) and the sixth power semiconductor switch (S6) is connected to the partial connection (4), the fifth power semiconductor switch (S5) is connected to the junction point between the first power semiconductor switch (S1) and the second power semiconductor switch (S2), and the sixth power semiconductor switch (S6) is connected to the junction point between the third power semiconductor switch (S3) and the fourth power semiconductor switch (S4) in order to protect against damage and destruction.
2. Converter circuit according to Claim 1, characterized in that the first and second voltage rise limiting networks (15, 16) are each formed by a series circuit comprising a diode (17, 18), a capacitance (19, 20) and a resistor (21, 22).
3. Converter circuit according to Claim 2, characterized in that the diode (9) of the first current rise limiting network (5) is connected to the junction point between the diode (17) and the capacitance (19) of the first voltage rise limiting network (15), and
   in that the diode (14) of the second current rise limiting network (10) is connected to the junction point between the diode (18) and the capacitance (20) of the second voltage rise limiting network (16).
4. Converter circuit according to one of the preceding claims, characterized in that the first, second, third, fourth, fifth and sixth drivable bidirectional power semiconductor switches (S1, S2, S3, S4, S5, S6) are each formed by an integrated thyristor with a commutated drive electrode and by a diode which is connected back-to-back in parallel with the thyristor.
5. Converter circuit according to one of Claims 1 to 4, characterized in that a drivable short-circuiting element (23) is connected to the partial connection (4) and to the junction point between the second and third power semiconductor switches (S2, S3).
6. Converter circuit according to one of Claims 1 to 4, characterized in that provision is made of a drivable short-circuiting element (23) which is connected, via an inductance (24), to the junction point between the second and third power semiconductor switches (S2, S3), and in that a series circuit comprising a resistor (25) and a capacitance (26) is connected in parallel with the drivable short-circuiting element (23).
7. Converter circuit according to Claim 5 or 6, characterized in that the drivable short-circuiting element (23) is formed from two drivable power semiconductor switches which are connected back-to-back in parallel and each have pressure contact.
8. Converter circuit according to Claim 7, characterized in that the respective drivable power semiconductor switch of the drivable short-circuiting element (23) is formed by an integrated thyristor with a commutated drive electrode.
9. Converter circuit according to one of the preceding claims, characterized in that a balancing resistor (27) is connected in parallel with the series circuit comprising the fifth and sixth power semiconductor switches (S5, S6).

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