EP1550089A2 - Method and apparatus for token triggered multithreading - Google Patents

Method and apparatus for token triggered multithreading

Info

Publication number
EP1550089A2
EP1550089A2 EP03774679A EP03774679A EP1550089A2 EP 1550089 A2 EP1550089 A2 EP 1550089A2 EP 03774679 A EP03774679 A EP 03774679A EP 03774679 A EP03774679 A EP 03774679A EP 1550089 A2 EP1550089 A2 EP 1550089A2
Authority
EP
European Patent Office
Prior art keywords
thread
threads
processor
register
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP03774679A
Other languages
German (de)
French (fr)
Other versions
EP1550089A4 (en
EP1550089B1 (en
Inventor
Erdem Hokenek
Mayan Moudgill
John C. Glossner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Sandbridge Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandbridge Technologies Inc filed Critical Sandbridge Technologies Inc
Priority to EP13002869.9A priority Critical patent/EP2650778B1/en
Publication of EP1550089A2 publication Critical patent/EP1550089A2/en
Publication of EP1550089A4 publication Critical patent/EP1550089A4/en
Application granted granted Critical
Publication of EP1550089B1 publication Critical patent/EP1550089B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Definitions

  • the present invention is related to the inventions described in U.S. Patent Applications Attorney Docket No. 1007-5, entitled “Method and Apparatus for Thread-Based Memory Access in a Multithreaded Processor,” Attorney Docket No. 1007-6, entitled “Multithreaded Processor With Efficient Processing For Convergence Device Applications,” and Attorney Docket No. 1007-7, entitled “Method and Apparatus for Register File Port Reduction in a Multithreaded Processor,” all of which are filed concurrently herewith and incorporated by reference herein.
  • the present invention relates generally to the field of digital data processors, and more particularly to threading techniques for use in a multithreaded processor.
  • Multithreaded processors are processors that support simultaneous execution of multiple distinct instruction sequences or "threads.” Conventional threading techniques are described in, for example, M.J. Flynn, “Computer Architecture: Pipelined and Parallel Processor Design,” Jones and Bartlett Publishers, Boston, MA, 1995, and G.A. Blaauw and Frederick P. Brooks, “Computer Architecture: Concepts and Evolution,” Addison- Wesley, Reading, Massachusetts, 1997, both of which are incorporated by reference herein.
  • a technique known as “barrel multithreading” allows each thread to issue an instruction in accordance with a specified fixed numeric sequence.
  • a processor with four tlireads, denoted Thread 0, Thread 1, Thread 2 and Thread 3, in accordance with barrel multithreading would allow the threads to issue instructions in the fixed numeric order Thread 0, Thread 1, Thread 2, Thread 3, Thread 0 and so on.
  • a problem with barrel multithreading and other existing threading techniques is that such techniques are generally not configured to permit arbitrary sequencing of thread instruction issuance, or if so configured require an excessive amount of hardware for their implementation.
  • the present invention provides token triggered threading techniques for a multithreaded processor.
  • an instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled by associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions, and then utilizing the stored value to control the instruction issuance sequence.
  • each of a plurality of hardware thread units or "contexts" of the multithreaded processor may include a corresponding local next thread identifier register updatable by that hardware thread unit, with the local register for a given one of the hardware thread units storing a value identifying the next thread to be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions.
  • a global register arrangement may also or alternatively be used. More particularly, there may be associated with the threads at least one global register accessible to each of the threads, with the contents of the global register after instruction issuance by a given one of the threads identifying another of the threads to be permitted to issue one or more instructions in accordance with the instruction issuance sequence.
  • a multithreaded processor in accordance with the invention may be configured so as to permit the instruction issuance sequence to correspond, for example, to an arbitrary alternating even-odd sequence of threads, or other arbitrary sequence, without introducing blocking conditions leading to thread stalls.
  • FIG. 1 is a block diagram of an example processing system in which the invention is implemented.
  • FIG.2 is a more detailed block diagram of an illustrative embodiment of a multithreaded processor of the FIG. 1 processing system.
  • FIG. 3 illustrates an example of token triggered threading suitable for use in the multithreaded processor of FIG. 2 in accordance with the techniques of the invention.
  • FIG.4 illustrates the manner in which example instruction functions may be pipelined in the FIG. 2 multithreaded processor in accordance with the techniques of the invention.
  • FIG. 5 shows an example single issue pipeline in which each of the threads of the FIG.2 processor issues one instruction per cycle.
  • FIG. 6 shows an example multiple issue pipeline in which each of the threads of the FIG. 2 processor issues two instructions per cycle.
  • FIG.7 shows an example set of hardware thread units configured in accordance with the invention and suitable for use in the FIG. 2 processor.
  • FIG. 8 illustrates a token triggered threading technique implemented in an illustrative embodiment of the FIG. 2 processor.
  • the present invention will be illustrated herein as implemented in an example multithreaded processor. It should be understood, however, that the invention does not require the use of the particular multithreaded processor configuration of the illustrative embodiment, and is more generally suitable for use in any multithreaded processor application in which it is desirable to provide improved performance through the use of token triggered multithreading in conjunction with instruction pipelining.
  • FIGS. 1 and 2 An example processing system 100 which implements a token triggered threading technique in accordance with the invention will be described in conjunction with FIGS. 1 and 2.
  • FIG. 1 shows the processing system 100 as including a multithreaded processor 102 coupled to a main memory 104.
  • the multithreaded processor 102 includes a multithreaded cache memory 110 and a multithreaded data memory 112.
  • FIG. 2 shows a more detailed view of one possible implementation of the multithreaded processor 102.
  • the multitlireaded processor 102 includes the multithreaded cache memory 110, the data memory 112, a cache controller 114, an instruction decoder 116, a register file 118, and a set of arithmetic logic units (ALUs) 120.
  • the multithreaded cache memory 110 is also referred to herein as a multithreaded cache. It should be noted that the particular arrangements shown in FIGS. 1 and 2 are simplified for clarity of illustration, and additional or alternative elements not explicitly shown may be included, as will be apparent to those skilled in the art.
  • the multithreaded cache 110 includes a plurality of thread caches 110-1, 110-2, . . . 110- N, where N generally denotes the number of threads supported by the multithreaded processor 102. Each thread thus has a corresponding thread cache associated therewith in the multithreaded cache 110.
  • the data memory 112 includes N distinct data memory instances, denoted data memories 112-1, 112-2, . . . 112-N as shown.
  • Each of the thread caches in the multithreaded cache 110 may comprise a memory array having one or more sets of memory locations.
  • a given thread cache may further comprise a thread identifier register for storing an associated thread identifier, as will be described in greater detail below in conjunction with FIG. 7.
  • the multithreaded cache 110 interfaces with the main memory 104 via the cache controller 114.
  • the cache controller 114 ensures that the appropriate instructions from main memory 104 are loaded into the multithreaded cache 110.
  • the cache controller 114 in this illustrative embodiment, operating in conjunction with logic circuitry or other processing elements associated with the individual thread caches 110-1, 110-2, . . . 110-N, implements at least a portion of an address mapping technique, such as fully associative mapping, direct mapping or set-associative mapping.
  • an address mapping technique such as fully associative mapping, direct mapping or set-associative mapping.
  • Illustrative set-associative mapping techniques suitable for use in conjunction with the present invention are described in U.S. Patent Application Serial Nos. 10/161,774 and 10/161,874, both filed June 4, 2002 and commonly assigned with the present application, and both of which are incorporated by reference herein.
  • the multithreaded cache 110 is used to store instructions to be executed by the multithreaded processor 102, while the data memory 112 stores data that is operated on by the instructions. Instructions are fetched from the multithreaded cache 110 by the instruction decoder 116 which operates in conjunction with the register file 118 and the ALUs 120 in controlling the execution of the instructions in a conventional manner.
  • the operation of multithreaded processor elements such as 116, 118 and 120 is well-understood in the art, and therefore not described in further detail herein.
  • the data memory 112 is typically directly connected to the main memory 104, although this connection is not explicitly shown in the figure.
  • One or more of the memories 104, 110 and 112 may each be configured so as to include multiple banks or other designated portions.
  • each bank may be viewed as being made up of one or more memory modules, or a specified portion of a single memory module.
  • multithreaded processor of the type shown in FIG. 2 and suitable for use in conjunction with the present invention is described in U.S. Provisional Application Serial No. 60/341 ,289, filed December 20, 2001 , which is incorporated by reference herein.
  • An illustrative embodiment of a multithreaded processor as described in U. S . Provisional Application Serial No. 60/341,289 is capable of executing RISC-based control code, digital signal processor (DSP) code, Java code and network processing code.
  • the processor includes a single instruction multiple data (SIMD) vector unit, a reduction unit, and long instruction word (LIW) compounded instruction execution.
  • SIMD single instruction multiple data
  • LIW long instruction word
  • the present invention in accordance with one aspect thereof provides improved performance in a multithreaded processor such as processor 102 of FIG.2. More specifically, as will be described in greater detail below, the processor 102 is configured in accordance with the techniques of the invention to utilize a token triggered threading technique which operates in conjunction with instruction pipelining to provide enhanced processor concurrency and reduced likelihood of thread stalling.
  • FIG. 3 shows an example of token triggered threading for an implementation of processor 102 in which the number of threads N is eight. In general, all of the threads operate simultaneously, and each accesses a corresponding instance of the thread cache 110 and data memory 112. As shown in FIG. 3, the eight threads are denoted Thread 0, Thread 1, Thread 2, . . . Thread 7, and are illustrated as being serially interconnected in the form of a ring.
  • Thread 0, Thread 1, Thread 2, . . . Thread 7 are illustrated as being serially interconnected in the form of a ring.
  • a given thread can generally be viewed in terms of hardware as well as software.
  • the particular processor hardware associated with a given thread is therefore more particularly referred to herein as a hardware thread unit or simply a "context.”
  • the tokens are arranged in a sequential or round-robin manner, such that the contexts will issue instructions sequentially.
  • tokens indicating the next context to issue an instruction may be arranged using other patterns, such as an alternating even- odd pattern.
  • other types of threading may be used in conjunction with the present invention. A number of example threading techniques in accordance with the invention will be described in greater detail below in conjunction with FIGS. 7 and 8.
  • FIG.4 illustrates the manner in which example instruction functions may be pipelined in the multithreaded processor 102 in accordance with the present invention.
  • this type of pipelining is preferably utilized in conjunction with the token triggered threading described previously, but it is to be appreciated that numerous other combinations of pipelining and threading may be used in implementing the invention.
  • the example instruction functions in FIG. 4 include Load/Store (Ld/St), ALU, integer multiplication (I_Mul) and vector multiplication (V_Mul), and are shown as having nine, six, seven and eight pipeline stages, respectively.
  • Each of the example instruction pipelines illustrated in FIG. 4 includes at least an instruction decode stage, a register file (RF) read stage, a transfer (Xfer) stage and a writeback (WB) stage.
  • the RF read stage involves reading from a register file, e.g., the register file 118
  • the transfer stage typically involves transferring instruction results to a designated holding register
  • the WB stage involves writing instruction results back to memory or a register file.
  • the Ld/St pipeline further includes an address generation (Agen) stage, an internal (Int) or external (Ext) determination stage, and three additional memory execute stages, denoted MemO, Meml and Mem2.
  • the Ld/St pipeline thus includes a total of four memory execute stages, that is, MemO, Meml, Mem2 and WB.
  • the internal or external determination stage determines if the associated memory access is to an internal or an external memory, and may be viewed as an additional decode stage within the pipeline. It should be noted that additional memory execute stages may be required for certain external memory accesses. For example, if the WB stage of an external memory access does not complete during the period of time for which the corresponding thread is active, the thread may be stalled such that the WB stage will complete the next time the thread is active.
  • the ALU pipeline further includes two execution stages denoted Execl and Exec2.
  • the integer I VIul pipeline further includes three execution stages denoted Execl, Exec2 and Exec3.
  • the vector N_Mul pipeline further includes two multiplication stages MPY1 and MPY2, and two addition stages Addl and Add2.
  • the multithreaded processor 102 is preferably configured such that once an instruction from a particular context enters its corresponding pipeline, it runs to completion.
  • FIGS. 5 and 6 each show sequences of instructions issued by particular processor threads, and indicate for each instruction whether an even (e) portion or an odd (o) portion of the register file 118 is utilized by the corresponding thread.
  • FIGS. 10 U.S. Patent Application Attorney Docket No. 1007-7
  • each thread issues instructions in accordance with a round-robin implementation of the FIG. 3 token triggered threading. More specifically, each thread in these examples issues alternating Load and Vector Multiply instructions, which is a typical instruction sequence in many signal processing applications.
  • the Load and Vector Multiply instructions are configured substantially as described in accordance with the instruction function pipeline shown in FIG. 4.
  • FIG. 5 an example of a single issue pipeline is shown, in which each thread issues one instruction per cycle.
  • the register file portions accessed by the issued instructions alternate from thread to thread between even (e) and odd (o).
  • This ensures that adjacent register writeback operations, such as those associated with the writeback stages of the first Load instruction of Thread 4 and the Vector Multiply instruction of Thread 1, are directed to different portions of the register file. More specifically, the first Load instruction of Thread 4 is directed to an even portion of the register file, while the Vector Multiply instruction of Thread 1 is directed to an odd portion of the register file.
  • the other instructions shown in the diagram are similarly configured.
  • LSB least significant bit
  • FIG. 6 shows an example multiple issue pipeline in which each of the processor threads issues two instructions per cycle.
  • a single thread is issuing both Load and Vector Multiply instructions each cycle.
  • two additional register file read ports are required relative to the FIG. 5 example.
  • all concurrent writes are still to even or odd portions of the register file, as determined based on the LSB of the thread identifier, so the number of required register file write ports and thus the processor power consumption are reduced.
  • hardware thread units are also referred to herein as contexts, and there is generally one such unit or context associated with each thread supported by the processor.
  • Each of the hardware thread units 702 includes a thread identifier (TID) register 704 and a next thread identifier (NTID) register 706.
  • TID thread identifier
  • NTID next thread identifier
  • each of the hardware thread units 702 may include a corresponding thread cache 110 and data cache 112, as well as or alternatively associated portions of the cache controller 114 or other processor circuitry.
  • each of the hardware thread units 702 may issue one or more instructions on a given processor cycle.
  • the TID register 704 in a given hardware thread unit stores the thread identifier of the corresponding thread.
  • the NTID register 706 in the given hardware thread unit stores the thread identifier of the next hardware thread unit that will issue an instruction after the given hardware thread unit has issued its instruction(s).
  • the NTID register 706 thus may be viewed as storing a token associated with a token triggered threading technique of the present invention.
  • the token may be set by the given hardware thread unit to the thread identifier of any of the other hardware thread units, thereby providing considerable flexibility in the token triggered multithreading process.
  • the NTID register may also or alternatively be implemented as a global register accessible to all of the hardware thread units. In this case, each hardware thread unit need not serially increment the global NTID register.
  • a state machine or other similar circuitry implemented external to the hardware thread units may be used to program a global NTID register to provide any desired token sequence.
  • FIG. 8 shows an example token sequence corresponding to an alternating even-odd pattern.
  • This example illustrates that use of the NTID register as shown in FIG. 7 permits each context to grant the token to any other context in an even-odd pattern without causing any conflicts in the execution pipeline, and thus without thread stalls.
  • the combination of this threading technique with instruction pipelining significantly reduces the number of blocking conditions and allows arbitrary execution of even-odd thread sequences.
  • the thread identifier register 704 stores a multi-bit thread identifier that is used by the multithreaded processor 102 to identify a particular thread. Such thread identifiers may be generated in a conventional manner, as will be apparent to those skilled in the art.
  • thread identifier is intended to include any information suitable for identifying a particular thread or a set of multiple threads in a multithreaded processor.
  • a wide variety of different thread identifier configurations suitable for use with the present invention will be readily apparent to those skilled in the art.
  • the token triggered threading techniques of the present invention provide significant improvements relative to conventional techniques. For example, the techniques can substantially reduce the likelihood of thread stalling. Moreover, these improvements are provided without impacting processor concurrency or other aspects of processor performance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Techniques for token triggered multithreading in a multithreaded processor are disclosed. An instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled by associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions, and utilizing the stored value to control the instruction issuance sequence. For example, each of a plurality of hardware thread units of the multithreaded processor may include a corresponding local register updatable by that hardware thread unit, with the local register for a given one of the hardware thread units storing a value identifying the next thread to be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions. A global register arrangement may also or alternatively be used. The processor may be configured so as to permit the instruction issuance sequence to correspond to an arbitrary alternating even-odd sequence of threads, without introducing blocking conditions leading to thread stalls.

Description

METHODANDAPPARATUSFORTOKENTRIGGEREDMULTITHREADING
Related Application (s)
The present invention is related to the inventions described in U.S. Patent Applications Attorney Docket No. 1007-5, entitled "Method and Apparatus for Thread-Based Memory Access in a Multithreaded Processor," Attorney Docket No. 1007-6, entitled "Multithreaded Processor With Efficient Processing For Convergence Device Applications," and Attorney Docket No. 1007-7, entitled "Method and Apparatus for Register File Port Reduction in a Multithreaded Processor," all of which are filed concurrently herewith and incorporated by reference herein.
Field of the Invention
The present invention relates generally to the field of digital data processors, and more particularly to threading techniques for use in a multithreaded processor.
Background of the Invention
Multithreaded processors are processors that support simultaneous execution of multiple distinct instruction sequences or "threads." Conventional threading techniques are described in, for example, M.J. Flynn, "Computer Architecture: Pipelined and Parallel Processor Design," Jones and Bartlett Publishers, Boston, MA, 1995, and G.A. Blaauw and Frederick P. Brooks, "Computer Architecture: Concepts and Evolution," Addison- Wesley, Reading, Massachusetts, 1997, both of which are incorporated by reference herein.
By way of example, a technique known as "barrel multithreading" allows each thread to issue an instruction in accordance with a specified fixed numeric sequence. For example, a processor with four tlireads, denoted Thread 0, Thread 1, Thread 2 and Thread 3, in accordance with barrel multithreading would allow the threads to issue instructions in the fixed numeric order Thread 0, Thread 1, Thread 2, Thread 3, Thread 0 and so on.
A problem with barrel multithreading and other existing threading techniques is that such techniques are generally not configured to permit arbitrary sequencing of thread instruction issuance, or if so configured require an excessive amount of hardware for their implementation.
Existing tecliniques are therefore unduly inflexible, and may place undesirable limitations on processor concurrency. Moreover, these techniques can contribute to blocking conditions and thus thread stalling, which adversely impacts processor performance. A need therefore exists for improved threading techniques for use in a multithreaded processor.
Summary of the Invention
The present invention provides token triggered threading techniques for a multithreaded processor.
In accordance with one aspect of the invention, an instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled by associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions, and then utilizing the stored value to control the instruction issuance sequence.
By way of example, in an illustrative embodiment of the invention, each of a plurality of hardware thread units or "contexts" of the multithreaded processor may include a corresponding local next thread identifier register updatable by that hardware thread unit, with the local register for a given one of the hardware thread units storing a value identifying the next thread to be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions.
A global register arrangement may also or alternatively be used. More particularly, there may be associated with the threads at least one global register accessible to each of the threads, with the contents of the global register after instruction issuance by a given one of the threads identifying another of the threads to be permitted to issue one or more instructions in accordance with the instruction issuance sequence.
Advantageously, a multithreaded processor in accordance with the invention may be configured so as to permit the instruction issuance sequence to correspond, for example, to an arbitrary alternating even-odd sequence of threads, or other arbitrary sequence, without introducing blocking conditions leading to thread stalls.
Brief Description of the Drawings
FIG. 1 is a block diagram of an example processing system in which the invention is implemented.
FIG.2 is a more detailed block diagram of an illustrative embodiment of a multithreaded processor of the FIG. 1 processing system. FIG. 3 illustrates an example of token triggered threading suitable for use in the multithreaded processor of FIG. 2 in accordance with the techniques of the invention.
FIG.4 illustrates the manner in which example instruction functions may be pipelined in the FIG. 2 multithreaded processor in accordance with the techniques of the invention.
FIG. 5 shows an example single issue pipeline in which each of the threads of the FIG.2 processor issues one instruction per cycle.
FIG. 6 shows an example multiple issue pipeline in which each of the threads of the FIG. 2 processor issues two instructions per cycle.
FIG.7 shows an example set of hardware thread units configured in accordance with the invention and suitable for use in the FIG. 2 processor.
FIG. 8 illustrates a token triggered threading technique implemented in an illustrative embodiment of the FIG. 2 processor.
Detailed Description of the Invention
The present invention will be illustrated herein as implemented in an example multithreaded processor. It should be understood, however, that the invention does not require the use of the particular multithreaded processor configuration of the illustrative embodiment, and is more generally suitable for use in any multithreaded processor application in which it is desirable to provide improved performance through the use of token triggered multithreading in conjunction with instruction pipelining.
An example processing system 100 which implements a token triggered threading technique in accordance with the invention will be described in conjunction with FIGS. 1 and 2.
FIG. 1 shows the processing system 100 as including a multithreaded processor 102 coupled to a main memory 104. The multithreaded processor 102 includes a multithreaded cache memory 110 and a multithreaded data memory 112.
FIG. 2 shows a more detailed view of one possible implementation of the multithreaded processor 102. In this embodiment, the multitlireaded processor 102 includes the multithreaded cache memory 110, the data memory 112, a cache controller 114, an instruction decoder 116, a register file 118, and a set of arithmetic logic units (ALUs) 120. The multithreaded cache memory 110 is also referred to herein as a multithreaded cache. It should be noted that the particular arrangements shown in FIGS. 1 and 2 are simplified for clarity of illustration, and additional or alternative elements not explicitly shown may be included, as will be apparent to those skilled in the art.
The multithreaded cache 110 includes a plurality of thread caches 110-1, 110-2, . . . 110- N, where N generally denotes the number of threads supported by the multithreaded processor 102. Each thread thus has a corresponding thread cache associated therewith in the multithreaded cache 110. Similarly, the data memory 112 includes N distinct data memory instances, denoted data memories 112-1, 112-2, . . . 112-N as shown.
Each of the thread caches in the multithreaded cache 110 may comprise a memory array having one or more sets of memory locations. A given thread cache may further comprise a thread identifier register for storing an associated thread identifier, as will be described in greater detail below in conjunction with FIG. 7.
The multithreaded cache 110 interfaces with the main memory 104 via the cache controller 114. The cache controller 114 ensures that the appropriate instructions from main memory 104 are loaded into the multithreaded cache 110. The cache controller 114 in this illustrative embodiment, operating in conjunction with logic circuitry or other processing elements associated with the individual thread caches 110-1, 110-2, . . . 110-N, implements at least a portion of an address mapping technique, such as fully associative mapping, direct mapping or set-associative mapping. Illustrative set-associative mapping techniques suitable for use in conjunction with the present invention are described in U.S. Patent Application Serial Nos. 10/161,774 and 10/161,874, both filed June 4, 2002 and commonly assigned with the present application, and both of which are incorporated by reference herein.
In general, the multithreaded cache 110 is used to store instructions to be executed by the multithreaded processor 102, while the data memory 112 stores data that is operated on by the instructions. Instructions are fetched from the multithreaded cache 110 by the instruction decoder 116 which operates in conjunction with the register file 118 and the ALUs 120 in controlling the execution of the instructions in a conventional manner. The operation of multithreaded processor elements such as 116, 118 and 120 is well-understood in the art, and therefore not described in further detail herein.
The data memory 112 is typically directly connected to the main memory 104, although this connection is not explicitly shown in the figure. One or more of the memories 104, 110 and 112 may each be configured so as to include multiple banks or other designated portions. By way of example, each bank may be viewed as being made up of one or more memory modules, or a specified portion of a single memory module.
Techniques for thread-based banking of these and other memories associated with a multithreaded processor are described in the above-cited U.S. Patent Application Attorney Docket No. 1007-5, entitled "Method and Apparatus for Thread-Based Memory Access in a Multithreaded Processor."
Techniques for thread-based access to a register file such as register file 118 are described in the above-cited U.S. Patent Application Attorney Docket No. 1007-7, entitled "Method and Apparatus for Register File Port Reduction in a Multithreaded Processor."
It should be emphasized that the present invention does not require the particular multithreaded processor configuration shown in FIG. 2. The invention can be implemented in a wide variety of other multithreaded processor configurations.
A more particular example of multithreaded processor of the type shown in FIG. 2 and suitable for use in conjunction with the present invention is described in U.S. Provisional Application Serial No. 60/341 ,289, filed December 20, 2001 , which is incorporated by reference herein. An illustrative embodiment of a multithreaded processor as described in U. S . Provisional Application Serial No. 60/341,289 is capable of executing RISC-based control code, digital signal processor (DSP) code, Java code and network processing code. The processor includes a single instruction multiple data (SIMD) vector unit, a reduction unit, and long instruction word (LIW) compounded instruction execution.
The present invention in accordance with one aspect thereof provides improved performance in a multithreaded processor such as processor 102 of FIG.2. More specifically, as will be described in greater detail below, the processor 102 is configured in accordance with the techniques of the invention to utilize a token triggered threading technique which operates in conjunction with instruction pipelining to provide enhanced processor concurrency and reduced likelihood of thread stalling.
FIG. 3 shows an example of token triggered threading for an implementation of processor 102 in which the number of threads N is eight. In general, all of the threads operate simultaneously, and each accesses a corresponding instance of the thread cache 110 and data memory 112. As shown in FIG. 3, the eight threads are denoted Thread 0, Thread 1, Thread 2, . . . Thread 7, and are illustrated as being serially interconnected in the form of a ring. In the multithreaded processor, a given thread can generally be viewed in terms of hardware as well as software. The particular processor hardware associated with a given thread is therefore more particularly referred to herein as a hardware thread unit or simply a "context."
In accordance with the token triggered threading illustrated in FIG. 3, all of the hardware thread units or contexts are permitted to simultaneously execute instructions, but only one context may issue an instruction in a particular clock cycle of the processor. In other words, all contexts execute simultaneously but only one context is active on a particular clock cycle. Therefore, if there are a total of C contexts it will require C clock cycles to issue an instruction from all contexts. Each clock cycle, one of the contexts issues an instruction, and the next thread to issue an instruction is indicated by a token.
In the FIG. 3 example, the tokens are arranged in a sequential or round-robin manner, such that the contexts will issue instructions sequentially. However, tokens indicating the next context to issue an instruction may be arranged using other patterns, such as an alternating even- odd pattern. Also, as noted above, other types of threading may be used in conjunction with the present invention. A number of example threading techniques in accordance with the invention will be described in greater detail below in conjunction with FIGS. 7 and 8.
FIG.4 illustrates the manner in which example instruction functions may be pipelined in the multithreaded processor 102 in accordance with the present invention. In the illustrative embodiment of the invention, this type of pipelining is preferably utilized in conjunction with the token triggered threading described previously, but it is to be appreciated that numerous other combinations of pipelining and threading may be used in implementing the invention.
The FIG. 4 pipeline is configured for use in conjunction with the illustrative N = 8 token triggered threading of FIG. 3. The example instruction functions in FIG. 4 include Load/Store (Ld/St), ALU, integer multiplication (I_Mul) and vector multiplication (V_Mul), and are shown as having nine, six, seven and eight pipeline stages, respectively.
Each of the example instruction pipelines illustrated in FIG. 4 includes at least an instruction decode stage, a register file (RF) read stage, a transfer (Xfer) stage and a writeback (WB) stage. The RF read stage involves reading from a register file, e.g., the register file 118, the transfer stage typically involves transferring instruction results to a designated holding register, and the WB stage involves writing instruction results back to memory or a register file. The Ld/St pipeline further includes an address generation (Agen) stage, an internal (Int) or external (Ext) determination stage, and three additional memory execute stages, denoted MemO, Meml and Mem2. The Ld/St pipeline thus includes a total of four memory execute stages, that is, MemO, Meml, Mem2 and WB. The internal or external determination stage determines if the associated memory access is to an internal or an external memory, and may be viewed as an additional decode stage within the pipeline. It should be noted that additional memory execute stages may be required for certain external memory accesses. For example, if the WB stage of an external memory access does not complete during the period of time for which the corresponding thread is active, the thread may be stalled such that the WB stage will complete the next time the thread is active.
The ALU pipeline further includes two execution stages denoted Execl and Exec2.
The integer I VIul pipeline further includes three execution stages denoted Execl, Exec2 and Exec3.
The vector N_Mul pipeline further includes two multiplication stages MPY1 and MPY2, and two addition stages Addl and Add2.
The multithreaded processor 102 is preferably configured such that once an instruction from a particular context enters its corresponding pipeline, it runs to completion.
With an appropriately-configured pipeline and a sufficient number of threads, all hardware contexts may be executing concurrently even though there is only a single instruction issued per context per cycle. As indicated previously, the particular number of threads and pipeline stages are purposes of illustration only, and not intended to reflect a preferred implementation. Those skilled in the art will be readily able to determine an appropriate number of threads and pipeline stages for a particular application given the teachings provided herein.
A number of examples of the operation of the pipeline of FIG. 4 will now be described with reference to FIGS. 5 and 6. The drawings of FIGS. 5 and 6 each show sequences of instructions issued by particular processor threads, and indicate for each instruction whether an even (e) portion or an odd (o) portion of the register file 118 is utilized by the corresponding thread. The above-cited U.S. Patent Application Attorney Docket No. 1007-7, entitled "Method and Apparatus for Register File Port Reduction in a Multithreaded Processor," shows an example of how the register file 118 may be separated into even and odd portions, with a particular one of the portions being selectable utilizing a thread identifier. In the examples of FIGS. 5 and 6, it is assumed for simplicity and clarity of description that the number of tlireads N is equal to 4, and that each thread issues instructions in accordance with a round-robin implementation of the FIG. 3 token triggered threading. More specifically, each thread in these examples issues alternating Load and Vector Multiply instructions, which is a typical instruction sequence in many signal processing applications. The Load and Vector Multiply instructions are configured substantially as described in accordance with the instruction function pipeline shown in FIG. 4.
Referring now to FIG. 5, an example of a single issue pipeline is shown, in which each thread issues one instruction per cycle. It can be seen from the FIG. 5 diagram that the register file portions accessed by the issued instructions alternate from thread to thread between even (e) and odd (o). This ensures that adjacent register writeback operations, such as those associated with the writeback stages of the first Load instruction of Thread 4 and the Vector Multiply instruction of Thread 1, are directed to different portions of the register file. More specifically, the first Load instruction of Thread 4 is directed to an even portion of the register file, while the Vector Multiply instruction of Thread 1 is directed to an odd portion of the register file. The other instructions shown in the diagram are similarly configured.
The thread identifier is used to select whether the even or odd portion of the register file will be accessed by a given thread. For example, in the N = 4 case of FIGS. 5 and 6, the least significant bit (LSB) of the thread identifier can be used to select between the even and odd portions of the register file.
FIG. 6 shows an example multiple issue pipeline in which each of the processor threads issues two instructions per cycle. Here, a single thread is issuing both Load and Vector Multiply instructions each cycle. Because multiple instructions issue per cycle, two additional register file read ports are required relative to the FIG. 5 example. However, as can be seen in the diagram, all concurrent writes are still to even or odd portions of the register file, as determined based on the LSB of the thread identifier, so the number of required register file write ports and thus the processor power consumption are reduced.
It should be emphasized that the particular number of threads shown in conjunction with FIGS. 5 and 6 is by way of example only, and the invention is not limited to use with any particular thread number.
FIG. 7 shows a set 700 of hardware thread units 702-/, . = 1, 2, . . . N, that may be implemented in the FIG. 2 multithreaded processor 102 in accordance with the invention. As indicated previously, such hardware thread units are also referred to herein as contexts, and there is generally one such unit or context associated with each thread supported by the processor. Each of the hardware thread units 702 includes a thread identifier (TID) register 704 and a next thread identifier (NTID) register 706. In addition, each of the hardware thread units 702 may include a corresponding thread cache 110 and data cache 112, as well as or alternatively associated portions of the cache controller 114 or other processor circuitry.
In accordance with the invention, each of the hardware thread units 702 may issue one or more instructions on a given processor cycle. The TID register 704 in a given hardware thread unit stores the thread identifier of the corresponding thread. The NTID register 706 in the given hardware thread unit stores the thread identifier of the next hardware thread unit that will issue an instruction after the given hardware thread unit has issued its instruction(s). The NTID register 706 thus may be viewed as storing a token associated with a token triggered threading technique of the present invention. The token may be set by the given hardware thread unit to the thread identifier of any of the other hardware thread units, thereby providing considerable flexibility in the token triggered multithreading process.
Although shown in FIG. 7 as a local register associated with and individually programmable by a corresponding hardware thread unit, the NTID register may also or alternatively be implemented as a global register accessible to all of the hardware thread units. In this case, each hardware thread unit need not serially increment the global NTID register. For example, a state machine or other similar circuitry implemented external to the hardware thread units may be used to program a global NTID register to provide any desired token sequence.
FIG. 8 shows an example token sequence corresponding to an alternating even-odd pattern. The token sequence in this particular N = 8 token triggered threading example is Thread 0 (TO), Thread 3 (T3), Thread 2 (T2), Thread 1 (Tl), Thread 6 (T6), Thread 5 (T5), Thread 4 (T4), Thread 7 (T7), Thread 0 (TO), and so on.
This example illustrates that use of the NTID register as shown in FIG. 7 permits each context to grant the token to any other context in an even-odd pattern without causing any conflicts in the execution pipeline, and thus without thread stalls. The combination of this threading technique with instruction pipelining significantly reduces the number of blocking conditions and allows arbitrary execution of even-odd thread sequences.
As noted previously, the thread identifier register 704 stores a multi-bit thread identifier that is used by the multithreaded processor 102 to identify a particular thread. Such thread identifiers may be generated in a conventional manner, as will be apparent to those skilled in the art.
The term "thread identifier" as used herein is intended to include any information suitable for identifying a particular thread or a set of multiple threads in a multithreaded processor. By way of example and without limitation, an « -bit thread identifier may be used to uniquely identify one of N = 2" threads supported by the multithreaded processor. A wide variety of different thread identifier configurations suitable for use with the present invention will be readily apparent to those skilled in the art.
As indicated above, the token triggered threading techniques of the present invention provide significant improvements relative to conventional techniques. For example, the techniques can substantially reduce the likelihood of thread stalling. Moreover, these improvements are provided without impacting processor concurrency or other aspects of processor performance.
The above-described embodiments of the invention are intended to be illustrative only, and numerous alternative embodiments within the scope of the appended claims will be apparent to those skilled in the art. For example, the multithreaded processor configuration, the number of threads, the thread identifier configuration and other parameters of the illustrative embodiments can be varied to accommodate the specific needs of a given application.

Claims

ClaimsWhat is claimed is:
1. A method for controlling an instruction issuance sequence for a plurality of threads of a multithreaded processor, the method comprising the steps of: associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions; and utilizing the stored value to control the instruction issuance sequence.
2. The method of claim 1 wherein the associating step further comprises the step of associating with each of a plurality of hardware thread units of the multithreaded processor a corresponding local register updatable by that hardware thread unit, the local register for a given one of the hardware thread units storing a value identifying the next thread to be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions.
3. The method of claim 1 wherein the associating step further comprises the step of associating a plurality of registers with each of a plurality of hardware thread units, the plurality of registers comprising for each of the hardware thread units a thread identifier register storing a thread identifier of the corresponding hardware thread unit and a next thread identifier register storing a next thread identifier specifying a next one of the hardware thread units to be permitted to issue one or more instructions.
4. The method of claim 1 wherein the associating step further comprises associating with each of the threads at least one global register accessible to each of the threads, the contents of the global register after instruction issuance by a given one of the threads identifying another of the threads to be permitted to issue one or more instructions in accordance with the instruction issuance sequence.
5. The method of claim 1 wherein the associating and utilizing steps are configured to permit the instruction issuance sequence to correspond to an arbitrary alternating even-odd sequence of threads without introducing blocking conditions leading to thread stalls.
6. The method of claim 1 wherein the at least one register comprises an n -bit register suitable for storing a unique identifier of a given one of 2" threads.
7. The method of claim 1 wherein the at least one register is associated with a thread cache corresponding to the particular thread of the multithreaded processor.
8. The method of claim 1 wherein the value stored in the at least one register comprises a token associated with token triggered threading.
9. The method of claim 8 wherein the token triggered threading utilizes the token to identify in association with a current processor clock cycle a particular one of the plurality of threads that will be permitted to issue an instruction for a subsequent clock cycle.
10. The method of claim 8 wherein the token triggered threading assigns different tokens to each of a plurality of threads of the multithreaded processor.
11. The method of claim 1 wherein the multitlireaded processor is configured for pipelined instruction processing.
12. The method of claim 11 wherein the multithreaded processor utilizes an instruction pipeline in which each thread issues a single instruction per processor clock cycle.
13. The method of claim 11 wherein the multithreaded processor utilizes an instruction pipeline in which each thread issues multiple instructions per processor clock cycle.
14. The method of claim 13 wherein each of a plurality of the threads issues both a load instruction and a vector multiply instruction in each of a corresponding plurality of processor clock cycles without stalling of any of the plurality of threads.
15. A multithreaded processor comprising a plurality of hardware thread units and being configured for controlling an instruction issuance sequence for a plurality of corresponding threads of the multithreaded processor, wherein within the processor there is associated with each of the tlireads at least one register adapted for storing a value identifying a next thread to be permitted to issue one or more instructions, the stored value being utilizable to control the instruction issuance sequence of the processor.
16. An article of manufacture comprising a machine-readable storage medium having embodied thereon program code for use in controlling an instruction issuance sequence for a plurality of threads of a multithreaded processor, wherein the program code when executed by the processor implements the steps of: associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions; and utilizing the stored value to control the instruction issuance sequence.
EP03774679.9A 2002-10-11 2003-10-09 Method and apparatus for token triggered multithreading Expired - Lifetime EP1550089B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP13002869.9A EP2650778B1 (en) 2002-10-11 2003-10-09 Method and apparatus for token triggered multithreading

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US269245 2002-10-11
US10/269,245 US6842848B2 (en) 2002-10-11 2002-10-11 Method and apparatus for token triggered multithreading
PCT/US2003/031905 WO2004034340A2 (en) 2002-10-11 2003-10-09 Method and apparatus for token triggered multithreading

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP13002869.9A Division EP2650778B1 (en) 2002-10-11 2003-10-09 Method and apparatus for token triggered multithreading
EP13002869.9A Division-Into EP2650778B1 (en) 2002-10-11 2003-10-09 Method and apparatus for token triggered multithreading

Publications (3)

Publication Number Publication Date
EP1550089A2 true EP1550089A2 (en) 2005-07-06
EP1550089A4 EP1550089A4 (en) 2007-06-06
EP1550089B1 EP1550089B1 (en) 2016-11-23

Family

ID=32068734

Family Applications (2)

Application Number Title Priority Date Filing Date
EP03774679.9A Expired - Lifetime EP1550089B1 (en) 2002-10-11 2003-10-09 Method and apparatus for token triggered multithreading
EP13002869.9A Expired - Lifetime EP2650778B1 (en) 2002-10-11 2003-10-09 Method and apparatus for token triggered multithreading

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP13002869.9A Expired - Lifetime EP2650778B1 (en) 2002-10-11 2003-10-09 Method and apparatus for token triggered multithreading

Country Status (7)

Country Link
US (1) US6842848B2 (en)
EP (2) EP1550089B1 (en)
JP (1) JP2006502505A (en)
KR (1) KR100991912B1 (en)
CN (1) CN100428282C (en)
AU (1) AU2003282487A1 (en)
WO (1) WO2004034340A2 (en)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006529043A (en) 2003-05-09 2006-12-28 サンドブリッジ テクノロジーズ インコーポレーテッド A processor reduction unit that performs sums of operands with or without saturation
US7475222B2 (en) * 2004-04-07 2009-01-06 Sandbridge Technologies, Inc. Multi-threaded processor having compound instruction and operation formats
US7797363B2 (en) * 2004-04-07 2010-09-14 Sandbridge Technologies, Inc. Processor having parallel vector multiply and reduce operations with sequential semantics
US8074051B2 (en) 2004-04-07 2011-12-06 Aspen Acquisition Corporation Multithreaded processor with multiple concurrent pipelines per thread
TW200625097A (en) * 2004-11-17 2006-07-16 Sandbridge Technologies Inc Data file storing multiple date types with controlled data access
US20070223599A1 (en) * 2005-07-25 2007-09-27 Sysair, Inc., A Delaware Corporation Cellular PC modem architecture and method of operation
US20070156928A1 (en) * 2005-12-30 2007-07-05 Makaram Raghunandan Token passing scheme for multithreaded multiprocessor system
EP2069947A4 (en) * 2006-09-26 2013-10-09 Qualcomm Inc APPLICATION OF MATRIX INVERSION SOFTWARE IN A WIRELESS COMMUNICATION SYSTEM
EP2080104A4 (en) * 2006-11-10 2010-01-06 Sandbridge Technologies Inc METHOD AND SYSTEM FOR PARALLELING PIPE-LINE CALCULATIONS
EP2159688A4 (en) * 2007-06-20 2011-01-05 Fujitsu Ltd INSTRUCTION EXECUTION CONTROL DEVICE AND INSTRUCTION EXECUTION CONTROL METHOD
EP2602710A1 (en) * 2007-11-05 2013-06-12 Aspen Acquisition Corporation Method of encoding register instruction fields
EP2232367A4 (en) * 2007-12-12 2011-03-09 Univ Washington DETERMINIST MULTIPLE PROCESSING
EP2250539A1 (en) * 2008-01-30 2010-11-17 Sandbridge Technologies, Inc. Method for enabling multi-processor synchronization
CN102007469A (en) * 2008-02-18 2011-04-06 阿斯奔收购公司 Method to accelerate null-terminated string operations
US8762641B2 (en) * 2008-03-13 2014-06-24 Qualcomm Incorporated Method for achieving power savings by disabling a valid array
WO2010017263A1 (en) 2008-08-06 2010-02-11 Sandbridge Technologies, Inc. Haltable and restartable dma engine
CN102495726B (en) 2011-11-15 2015-05-20 无锡德思普科技有限公司 Opportunity multi-threading method and processor
US10534606B2 (en) 2011-12-08 2020-01-14 Oracle International Corporation Run-length encoding decompression
US9792117B2 (en) 2011-12-08 2017-10-17 Oracle International Corporation Loading values from a value vector into subregisters of a single instruction multiple data register
US9342314B2 (en) 2011-12-08 2016-05-17 Oracle International Corporation Efficient hardware instructions for single instruction multiple data processors
EP2788902B1 (en) 2011-12-08 2019-04-17 Oracle International Corporation Techniques for more efficient usage of memory-to-cpu bandwidth
US9697174B2 (en) 2011-12-08 2017-07-04 Oracle International Corporation Efficient hardware instructions for processing bit vectors for single instruction multiple data processors
GB2499277B (en) * 2012-08-30 2014-04-02 Imagination Tech Ltd Global register protection in a multi-threaded processor
US9292569B2 (en) 2012-10-02 2016-03-22 Oracle International Corporation Semi-join acceleration
CN103150149B (en) 2013-03-26 2015-11-25 华为技术有限公司 Process database is reformed the method and apparatus of data
US10318305B2 (en) 2013-09-06 2019-06-11 Huawei Technologies Co., Ltd. System and method for an asynchronous processor with pepelined arithmetic and logic unit
US11113054B2 (en) 2013-09-10 2021-09-07 Oracle International Corporation Efficient hardware instructions for single instruction multiple data processors: fast fixed-length value compression
US9430390B2 (en) 2013-09-21 2016-08-30 Oracle International Corporation Core in-memory space and object management architecture in a traditional RDBMS supporting DW and OLTP applications
US9558000B2 (en) 2014-02-06 2017-01-31 Optimum Semiconductor Technologies, Inc. Multithreading using an ordered list of hardware contexts
US9766894B2 (en) 2014-02-06 2017-09-19 Optimum Semiconductor Technologies, Inc. Method and apparatus for enabling a processor to generate pipeline control signals
US9766895B2 (en) * 2014-02-06 2017-09-19 Optimum Semiconductor Technologies, Inc. Opportunity multithreading in a multithreaded processor with instruction chaining capability
EP3131004A4 (en) * 2014-04-11 2017-11-08 Murakumo Corporation Processor and method
US10180841B2 (en) 2014-12-22 2019-01-15 Centipede Semi Ltd. Early termination of segment monitoring in run-time code parallelization
US10296346B2 (en) * 2015-03-31 2019-05-21 Centipede Semi Ltd. Parallelized execution of instruction sequences based on pre-monitoring
US10296350B2 (en) * 2015-03-31 2019-05-21 Centipede Semi Ltd. Parallelized execution of instruction sequences
US10025823B2 (en) 2015-05-29 2018-07-17 Oracle International Corporation Techniques for evaluating query predicates during in-memory table scans
US9990308B2 (en) 2015-08-31 2018-06-05 Oracle International Corporation Selective data compression for in-memory databases
US10061714B2 (en) 2016-03-18 2018-08-28 Oracle International Corporation Tuple encoding aware direct memory access engine for scratchpad enabled multicore processors
US10061832B2 (en) 2016-11-28 2018-08-28 Oracle International Corporation Database tuple-encoding-aware data partitioning in a direct memory access engine
US10402425B2 (en) 2016-03-18 2019-09-03 Oracle International Corporation Tuple encoding aware direct memory access engine for scratchpad enabled multi-core processors
US10055358B2 (en) 2016-03-18 2018-08-21 Oracle International Corporation Run length encoding aware direct memory access filtering engine for scratchpad enabled multicore processors
US10599488B2 (en) 2016-06-29 2020-03-24 Oracle International Corporation Multi-purpose events for notification and sequence control in multi-core processor systems
US10380058B2 (en) 2016-09-06 2019-08-13 Oracle International Corporation Processor core to coprocessor interface with FIFO semantics
US10783102B2 (en) 2016-10-11 2020-09-22 Oracle International Corporation Dynamically configurable high performance database-aware hash engine
US10459859B2 (en) 2016-11-28 2019-10-29 Oracle International Corporation Multicast copy ring for database direct memory access filtering engine
US10176114B2 (en) 2016-11-28 2019-01-08 Oracle International Corporation Row identification number generation in database direct memory access engine
US10725947B2 (en) 2016-11-29 2020-07-28 Oracle International Corporation Bit vector gather row count calculation and handling in direct memory access engine
DE102017223844A1 (en) * 2017-12-28 2019-07-04 Robert Bosch Gmbh Method for operating a belt drive
WO2023249637A1 (en) * 2022-06-24 2023-12-28 Zeku, Inc. Apparatus and method to implement a token-based processing scheme for virtual dataplane threads

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5339415A (en) * 1990-06-11 1994-08-16 Cray Research, Inc. Dual level scheduling of processes to multiple parallel regions of a multi-threaded program on a tightly coupled multiprocessor computer system
US5404469A (en) * 1992-02-25 1995-04-04 Industrial Technology Research Institute Multi-threaded microprocessor architecture utilizing static interleaving
US5613114A (en) * 1994-04-15 1997-03-18 Apple Computer, Inc System and method for custom context switching
US6128720A (en) 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US5682491A (en) 1994-12-29 1997-10-28 International Business Machines Corporation Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
US5649135A (en) 1995-01-17 1997-07-15 International Business Machines Corporation Parallel processing system and method using surrogate instructions
US5659785A (en) 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US5933627A (en) * 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
US5799182A (en) * 1997-01-21 1998-08-25 Ford Motor Company Multiple thread micro-sequencer apparatus and method with a single processor
US6151683A (en) * 1997-03-31 2000-11-21 Sun Microsystems, Inc. Rebuilding computer states remotely
US6298431B1 (en) * 1997-12-31 2001-10-02 Intel Corporation Banked shadowed register file
US6079010A (en) 1998-03-31 2000-06-20 Lucent Technologies Inc. Multiple machine view execution in a computer system
US6317821B1 (en) 1998-05-18 2001-11-13 Lucent Technologies Inc. Virtual single-cycle execution in pipelined processors
US6260189B1 (en) 1998-09-14 2001-07-10 Lucent Technologies Inc. Compiler-controlled dynamic instruction dispatch in pipelined processors
US6256725B1 (en) 1998-12-04 2001-07-03 Agere Systems Guardian Corp. Shared datapath processor utilizing stack-based and register-based storage spaces
US6341338B1 (en) * 1999-02-04 2002-01-22 Sun Microsystems, Inc. Protocol for coordinating the distribution of shared memory
US6282585B1 (en) 1999-03-22 2001-08-28 Agere Systems Guardian Corp. Cooperative interconnection for reducing port pressure in clustered microprocessors
US6269437B1 (en) 1999-03-22 2001-07-31 Agere Systems Guardian Corp. Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor
US6230251B1 (en) 1999-03-22 2001-05-08 Agere Systems Guardian Corp. File replication methods and apparatus for reducing port pressure in a clustered processor
US7925869B2 (en) * 1999-12-22 2011-04-12 Ubicom, Inc. Instruction-level multithreading according to a predetermined fixed schedule in an embedded processor using zero-time context switching

Also Published As

Publication number Publication date
KR20050073484A (en) 2005-07-13
CN100428282C (en) 2008-10-22
US20040073781A1 (en) 2004-04-15
WO2004034340A2 (en) 2004-04-22
KR100991912B1 (en) 2010-11-04
WO2004034340A3 (en) 2004-08-26
JP2006502505A (en) 2006-01-19
CN1711563A (en) 2005-12-21
EP2650778B1 (en) 2017-07-19
EP2650778A1 (en) 2013-10-16
AU2003282487A8 (en) 2004-05-04
EP1550089A4 (en) 2007-06-06
EP1550089B1 (en) 2016-11-23
US6842848B2 (en) 2005-01-11
AU2003282487A1 (en) 2004-05-04

Similar Documents

Publication Publication Date Title
US6842848B2 (en) Method and apparatus for token triggered multithreading
EP1550030B1 (en) Method and apparatus for register file port reduction in a multithreaded processor
US6925643B2 (en) Method and apparatus for thread-based memory access in a multithreaded processor
US8892849B2 (en) Multithreaded processor with multiple concurrent pipelines per thread

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050428

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20070507

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 9/00 20060101AFI20070427BHEP

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: ASPEN ACQUISITION CORPORATION

17Q First examination report despatched

Effective date: 20110601

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: QUALCOMM INCORPORATED

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 60349640

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: G06F0009000000

Ipc: G06F0009380000

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 9/38 20060101AFI20151106BHEP

INTG Intention to grant announced

Effective date: 20151216

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

INTG Intention to grant announced

Effective date: 20160603

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 848484

Country of ref document: AT

Kind code of ref document: T

Effective date: 20161215

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 60349640

Country of ref document: DE

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20161123

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 848484

Country of ref document: AT

Kind code of ref document: T

Effective date: 20161123

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170224

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170323

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 60349640

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20170223

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 15

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20170824

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20171031

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20171009

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20171031

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 16

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20171009

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20031009

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20161123

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20161123

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20220914

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20220916

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20220627

Year of fee payment: 20

REG Reference to a national code

Ref country code: DE

Ref legal event code: R071

Ref document number: 60349640

Country of ref document: DE

REG Reference to a national code

Ref country code: GB

Ref legal event code: PE20

Expiry date: 20231008

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20231008

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20231008