Classifications

• • G—PHYSICS
  • G07—CHECKING-DEVICES
  • G07F—COIN-FREED OR LIKE APPARATUS
  • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
  • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
  • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
  • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/3017—Runtime instruction translation, e.g. macros
  • G06F9/30178—Runtime instruction translation, e.g. macros of compressed or encrypted instructions
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3802—Instruction prefetching
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
  • G06Q20/00—Payment architectures, schemes or protocols
  • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
  • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
  • G06Q20/355—Personalisation of cards for use
  • G06Q20/3552—Downloading or loading of personalisation data

Definitions

• the present invention relates to securing the execution environment of an interpreter, such as a virtual machine, in a data processing device of the portable electronic object type such as a smart card.
• the invention relates to protection against attacks to execute data as if they were instructions
• a typical attack for example, involves performing an unwanted jump to a memory area that has recorded data. This results for example from the modification of pseudo-codes in a downloaded application, such as an applet, by an attacker in order to introduce an "aggressive" applet in a data field and thus to introduce a jump to this part of data.
• the virtual machine which is not able to distinguish instructions and data, then executes the data as if they were instructions.
• the invention aims to protect the operation of the virtual machine against such attacks and more specifically to distinguish instructions and data particularly when executing part of a downloaded application.
• a data processing device according to
• the invention comprises a storage means for storing at least one downloaded application, initially compiled in an intermediate language, composed of several application components each containing an identifier and instruction words, and a virtual execution means. It is characterized in that it includes:
• a second transformer means included in the virtual execution means for applying each of the transformed instruction words to a part of the predetermined application component and the random number associated with the reciprocal function of the transformation function in order to recover the words d instruction composing said part of the predetermined application component to execute said part of component thus recovered.
• the predetermined application component comprises a series of methods, as part of the component, whose instruction words, such as operation code bytes and parameter bytes, are systematically transformed into transformed instruction words before being permanently saved in the data processing device, which allows instructions to be distinguished from data. For example, a jump introduced irregularly in a downloaded application will not lead to a desired data since the execution of the jump is will do with respect to a data item deemed to be transformed which does not correspond to the desired jump.
• the generator means generates a random number produced by the virtual execution means, and the first transformer means applies, for example during the creation of an object by the virtual execution means, each datum and the random number associated with the transformation function in order to write a transformed datum in the storage means when the datum is produced by the virtual execution means.
• the invention provides for distinguishing the different data according to the primitive types of the data.
• the generating means generates random numbers respectively associated with primitive types of data, and the first transformer means applies each data produced by the virtual execution means and the random number associated with the primitive type of the data to the function transformation in order to write our transformed data into the storage means when the data is produced by the virtual execution means.
• FIG. 1 is a schematic block diagram of a chip card type data processing device according to the invention
• Figure 2 is an algorithm for loading an application into the data processing device according to the invention
• Figure 3 is a diagram showing a series of instructions in particular when creating an object
• Figure 4 is an object creation algorithm according to the instructions in Figure 3;
• FIG. 5 is a diagram of instructions transformed into a method for executing an addition of two local variables according to the loaded application; and FIG. 6 is an algorithm for executing the method with the transformed instructions shown in FIG. 5.
• a smart card 1 also called a microcontroller or integrated circuit card, as a portable electronic object housed in a removable manner in a reader 21 of a platform. reception such as a reception terminal 2.
• the smart card 1 is of any known type of contact or contactless smart card, and can be a payment card, a telephone card, a card additional, a removable Subscriber Identity Module (SIM), a game card, etc.
• SIM Subscriber Identity Module
• the reception terminal 2 can be a personal computer PC or a bank terminal or a point of sale terminal, or even a mobile cellular radiotelephone terminal, or a portable electronic object such as a personal digital assistant (PDA). or an electronic wallet.
• PDA personal digital assistant
• the microcontroller in the smart card 1 as a data processing device, comprises a microprocessor 3, a non-memory rewritable 4 of the ROM type, a non-volatile memory 5 of the EEPROM type and a random access memory 6 of the RAM type. All the components 3 to 6 in the smart card 1 are connected by a bus 7 internal to the card and a communication interface connected to the reader 21 in the reception terminal 2 through a contact or contactless connection LI.
• Spaces 40 and 41 of memory 4 respectively contain instructions in native code of an OS operating system (Operating System) and in pseudo-code (bytecode) of a virtual machine VM, as a means of execution on which the operating system is based.
• the pseudo-codes result from the compilation of a program in high level source language of the object oriented type, such as for example the Java Card language.
• a server (not shown) comprising a compiler converts the program in Java Card source language into a program compiled in intermediate language, that is to say into pseudo-codes which are instruction words formed by bytes, called "bytecodes", which are ready to be executed by the virtual machine VM, as an interpreter in the smart card 1.
• the compiled program constitutes an AP application, called an applet, downloaded into the smart card in the sense of 'invention.
• the memory 4 also includes at least authentication and communication applications internal to the card. Spaces 50 and 51 of the non-volatile memory 5 respectively contain data linked to the operating system OS and accessible by native codes and data linked to the virtual machine VM and accessible by pseudo-codes, as well as the pseudo-codes and application data downloaded to the map.
• the memory 5 also contains personal data linked to the owner of the smart card.
• the RAM type memory 6 essentially contains data exchanged with the outside world of the smart card 1, in particular with the reception terminal TE.
• the memory 6 notably comprises a predetermined space of fixed size for receiving one or more downloaded applications AP, such as applets, or portions of the application, from a server through the reception terminal 2 and the link LI to be executed. by the virtual machine VM.
• the predetermined space is divided into three memory spaces 60, 61 and 62.
• the space 60 mainly serves as a buffer memory for receiving machine data, such as a downloaded application AP and transforming it according to the invention into a transformed application which is written in the memory space 51 of the memory 5 reserved for VM virtual machine data.
• the other two memory spaces 61 and 62 are reserved for the first parts of methods invoked in applications comprising local variables VL and for second parts having variable sizes and comprising operands OP of the methods invoked.
• the invocation of a method on top of the stack thus constituted in the memory 6 under the control of the processor 3 causes the stacking of a respective frame ("frame") on the top of the stack which contains the other frames of method.
• the methods invoke each other, the previous method invoking the following method and the following method can only return to the previous method, by unstacking and discarding the top of the stack method. So only the method above the stack is active.
• the width of the stack is for example equal to one byte, or equal to the length of a pseudo-code.
• one or more local variables VL in the memory space 61 are declared during the implementation of a method and before the execution thereof.
• the local variables are used for the execution of the method, their number not being modified but their values being able to be modified during the execution of the method.
• a local variable can be a reference to an object whose method is called in order to access this object in the virtual machine VM, or else parameters of the method or other local variables.
• operands in the memory space 62 are values used by the virtual machine VM to execute next operations and in particular used as an argument for calling the invoked method. Operands of a method can become local variables of the next method when implementing the next method, and conversely the result of a method can become an operand of the immediately preceding method when returning to it.
• An application is in the form of programs compiled and structured into several software application components CP each comprising a series of bytes (bytecodes).
• Each byte supports an opcode constituting an IN instruction itself, or indeed one of the parameters PA of an instruction called operands.
• An instruction proper is thus composed of an instruction byte IN (opcode) which is optionally followed by one or more bytes of parameter PA.
• the application to download to which reference will be made here by way of example is in the form of a compiled file of the cap type. file and includes in particular a method component CP1 which contains all the methods of the application to download AP. Each method has a fixed length and includes several consecutive groups, each having an IN instruction byte and a predetermined number of PA parameter bytes.
• Another component CP2 of the application AP can be a static field component which contains all the static fields of the classes of the application.
• a static field is a field which belongs to a class independently of any possible instance and is not an instance of an object of the class and is thus shared by all the instances of the class.
• a static field is like an attribute associated with all the objects of a class.
• the smart card 1 further comprises, according to the invention, a random number generator 30 and two logic transformers 42 and 43.
• the generator 30 is implemented physically in or in connection with the microprocessor 3 of the smart card. It exchanges requests and responses through the bus 7 with the virtual machine VM in the memory space 40 in order to generate random numbers NA.
• the generator 30 associates a number random to a predetermined application component in the AP application when it is loaded, or to data, in particular for creating an object, as will be seen below.
• the random number generator is included in the form of software in the virtual machine VM, that is to say in the memory space 40.
• the random number generator 30 Each time the random number generator 30 generates a random number NA, the generated random number NA is written in a register RG included in the machine data space 60 in the memory RAM 6, under the control of the virtual machine VM .
• the virtual machine matches the value of the pointer in the memory 6 at the level of the register RG with an identifier ID included in a header of the component CP with which the random number NA is associated.
• the correspondence between the identifier ID and the register RG is written in the memory space 51 allocated to the virtual machine VM in the EEPROM memory 5.
• the transformers 42 and 43 are previously implemented in software form in the memory space 41 of the ROM memory 4 and are thus included in the virtual machine VM.
• a transformation is carried out for example byte by byte on all the bytes OC1 of the predetermined component CP1 when it is loaded into the machine data memory space 60 in the RAM memory 6 or on each operand when writing an operand, such as an object reference REF, in the operand space 62 when creating an object.
• an operand such as an object reference REF
• the transformation function FT is the Exclusive OR function (XOR) and therefore the corresponding reciprocal function FT is also the OR function
• FT reversible logical transformation functions
• the FT function is the multiplication of a byte and a random number
• the FT function is the division; or the FT function is the addition of a byte and a random number and the FT function is the subtraction; or else the FT function is a shift of a number of bits to one side, to the right or to the left, in a byte OC, the number determining the shift being equal to a random number NA less than the number of bits of the byte , and the reciprocal function FT is an offset to left or right of the number of NA bits in the OCT transformed byte.
• transformers 42 and 43 can process instruction words of constant length with several bytes to be transformed, instead of simply bytes, for example corresponding to complete instructions.
• the downloading of an application AP into the smart card 1 essentially comprises steps C1 to C8.
• the application AP comprising several software components CP is progressively written into a register RG1 of the machine data memory space 60 in the RAM memory 6.
• the following steps C2 to C7 are carried out progressively as the downloading of the application AP until the transfer of a transformed component thereof from the RAM memory 6 to the EEPROM memory 5 in step C7.
• the transformation according to the invention is applied only to at least one predetermined component CP1 in the download application AP designated by an identifier ID1 in the header of the component CPl.
• the virtual machine VM detects the identifiers ID at the start of each component CP of the application AP in step C2 in order to trigger, as indicated in step C3, the random number generator 30 when the virtual machine has detected the identifier ID1 of the CPl component.
• the generator 30 generates a random number NA1 which is written in a register RG2 in the space 60 of the ROM memory 6 and the virtual machine VM associates the identifier ID1 with a pointer value linked to the RG2 register by writing this correspondence in space 51.
• step C5 for each byte OCl in the component CP1 being loaded, the virtual machine VM writes the byte OCl in a buffer register RG3 of the memory space 60, the transformer 42 applies the byte OCl read in the register RG3 and the random number NA1 read in the register RG2 at the transformation function FT, such as the Exclusive OR function, and writes the result OCTl ⁇ FT (0C1, NA1) in a register RG4 in space 60, and finally the virtual machine VM replaces the byte OCl in the register RG1 with the corresponding transformed byte OCTl read in the register RG4.
• the transformation function FT such as the Exclusive OR function
• the transformed component CPT1 is then transferred from the register RG1 into the space 51 of the EEPROM 2 memory.
• Steps C2 to C7 are repeated for any other component CP2 to be transformed from the downloaded application AP.
• the component CP2 is a static field component which contains static fields of the classes of the AP application.
• the virtual machine VM loads the component CP1, CP2 into the smart card 1 by masking it randomly.
• the application is cut into portions of constant size, like packets.
• the loading steps C4 to C7 relate to each portion so as to successively transform the portions of the application.
• each part of the portion at the end or at the beginning of the component is recognized and treated separately by steps C4 to C7.
• Each portion is loaded and transformed and finally transferred into the space 51 of the EEPROM memory 5, before downloading the next portion into the RAM memory 6.
• the creation of an object for example during the execution of instructions in an internal application generates the transformation of data linked to the creation of the object, in particular the transformation of at least one REF reference to the object created into a REFT transformed reference without requiring the reciprocal transformation of the REFT transformed reference.
• the first instruction "new" in a byte of opcode (opcode) followed by two bytes of parameter "indexbyte” is first executed to create an OB object in step 02 according to the algorithm shown in FIG. 4.
• the virtual machine VM Prior to a step 01, if no random number has been associated with a data item, the virtual machine VM triggers the generation of a random number NAD in the generator 30 in order to write it in a register RGD included in the machine data space 51 of the EEPROM memory 5. More generally according to this embodiment, each time a data item is written in the RAM memory space 61 or 62 by the virtual machine VM, the random number NAD is used to transform this data.
• the parameters associated with the "new" instruction are used to reserve the necessary space in memory 5 for the object OB created by the virtual machine VM and to find all the information of the object to create.
• the parameters represent an index which makes it possible to find information in a table contained in the "constant_pool" field contained in the virtual machine.
• the object constructor in the virtual machine returns a REF reference which acts as the address of the descriptor of the object created.
• the reference REF is transformed into a reference REFT which is written on the top of the stack of the operand space 62 in the RAM memory 6.
• the following steps 04, 05 and 06 relate to manipulations of the transformed reference REFT, and not of the reference REF, in the memory RAM 6 by the virtual machine MV.
• the following instruction "dup" duplicates the transformed reference REFT in the memory space 62 by adding a copy of the reference REFT to the stack of operands.
• the "invokespecial" instruction having two parameters as shown in FIG. 3 calls the constructor of the created object OB in order to associate the transformed reference REFT with the object created internally in the virtual machine VM.
• the instruction "astore” in step 06 transfers the remaining transformed reference REFT from the operand memory space 62 to the local variable memory space 61 in the RAM memory 6 in order to manipulate the object, for example to call a method applicable to this object.
• any reference REF to an object is stored in its transformed form REFT depending on the random number NAD in the memory RAM 6. More generally, this transformation is applicable to all the fields of the object and to all the data .
• the random number generator 30 generates random numbers respectively associated with primitive types of data. For example, when creating an object, the virtual machine VM applies one or more of the following transformations to INT data of integer type, CHAR of character type, BOOL of boolean type (true / false: “true / slaughtere "), REF of type reference and D for all other types of data (float, double, etc.):
• the transformed data INTT, CHART, BOOLT, REFT and DT respectively result from transformations FT in the transformer 42 by the application of the corresponding initial data and a respective random number NAl, NAC, NAB, NAR and NAD .
• each primitive data item INT, CHAR, BOOL, REF, D and the associated random number NA1, NAC, NAB, NAR, NAD are applied by the transformer 42 to the transformation function FT in order to d 'write a transformed data INTT, CHART, BOOLT, REFT, DT in the RAM memory 6.
• the application method stored in the memory space 51 comprises six transformed OCT bytes.
• the fifth byte of the method is an OCT transformed byte of an "iadd" instruction designating an addition of the two variables VL1 and VL2 of integer type.
• the execution of the OCT transformed five-byte addition method shown in FIG. 5 essentially comprises steps E1 to E10.
• the virtual machine VM reads the random number NA1 in the register RG2 of the memory space 60, in step El, the random number NAl having been produced initially by the generator 30 when loading the AP application.
• step E2 each of the transformed bytes of the "iload" instruction 1 is applied with the number
• Step E6 is analogous to the previous steps E2 and E4 in order to retrieve the third iadd instruction by applying the fifth byte transformed in the method shown in Figure 5 and the number random NAl to the reciprocal function FT in the transformer 43.
• the two local variables to be added VLl and VL2 are retrieved first by reading the random number NAl in the register RGI of the memory space 51 , or alternatively, the random number NAD associated with all the primitive types of data in the register RGD of the memory space 51.
• the virtual machine then also reads the local transformed variables VLT2 and VLT1 above the stack in l space 62 and in step E8 each applies them to the reciprocal function FT -1 in the transformer 43 in order to recover the initial local variables VLl and VL2 which are written in two registers of the arithmetic logic unit in the virtual machine VM .
• the arithmetic unit executes the "iadd" instruction to add the local variables VL1 and VL2 to a sum SOM in step E9.
• the transformer 42 transforms the sum SOM by applying it with the random number NA1, or alternatively NAD, to the transformation function FT in the transformer 42 which produces the transformed sum SOMT in step E10.
• the transformed sum SOMT is finally positioned above the stack in the memory space 62 of the RAM memory 6.

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• Business, Economics & Management (AREA)
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• 2002
  • 2002-07-08 FR FR0208643A patent/FR2841997B1/fr not_active Expired - Fee Related
• 2003
  • 2003-07-07 US US10/520,434 patent/US7168625B2/en not_active Expired - Fee Related
  • 2003-07-07 JP JP2004518883A patent/JP4378459B2/ja not_active Expired - Lifetime
  • 2003-07-07 EP EP03762743A patent/EP1522012A2/de not_active Withdrawn
  • 2003-07-07 WO PCT/FR2003/002107 patent/WO2004006088A2/fr not_active Ceased
  • 2003-07-07 AU AU2003260670A patent/AU2003260670A1/en not_active Abandoned

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