Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/30—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/30—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability
  • H04N19/34—Scalability techniques involving progressive bit-plane based encoding of the enhancement layer, e.g. fine granular scalability [FGS]
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
  • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
  • H04N19/119—Adaptive subdivision aspects, e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
  • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
  • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/46—Embedding additional information in the video signal during the compression process

Definitions

• the present invention relates to video image encoding and more specifically to fractionally encoding enhancement layers of layer encoded video images.
• FGS encoding such as Fine Granular Scalar (FGS), and wavelet encoding
• FGS encoding encodes video images into a base-layer and an enhancement layer.
• the base layer represents the minimum image that that may be transmitted over a network with an acceptable quality.
• the enhancement layer represents additional image details that may be transmitted over the network when sufficient residual bandwidth is available.
• Enhancement layers are encoded in a bit-plane format wherein the most significant bits of each enhancement layer value are stored in a first bit plane and each succeeding bit of each enhancement layer value is stored in a corresponding bit plane. During transmission of the enhancement layer, the values in each bit plane are successively transmitted until the available bandwidth is occupied.
• Figure 1 illustrates an FGS fractional bit plane encoder in accordance with the principles of the present invention
• Figure 2 illustrates a significance mapped enhancement layer bit plane
• Figure 3 a illustrates a flow chart of an exemplary block diagram for identifying significant image areas within an image in accordance with the principles of the invention
• Figure 3b illustrates a flow chart of an exemplary process for generating a significance map in accordance with the principles of the invention.
• Figure 4 illustrates a system for determining significance mapped enhancement layer bit planes in accordance with the principles of the invention.
• a method for encoding a video image composed of a plurality of pixel blocks containing at least one area determined to be significant within a corresponding sub-layer.
• the method comprises the steps of associating a level of significance with each block of a known size within the at least one significant area, associating a level of significance with each successively larger block dependent upon the level of significance of at least one of the blocks of a known size contained within a successively larger block, and mapping each of the associated level of significance.
• the significance map is transmitted and corresponding image layers may be reconstructed using the significance map.
• FIG. 1 illustrates a block diagram of an exemplary fractional bit plane encoder 100 in accordance with the principles of the present invention.
• input signal 110 is applied to summer 115, which is mixed with motion compensated images, as will be further discussed.
• the combined signal is then applied to Discrete Coefficient Transformation (DCT) 120 to convert pixel values into coefficients.
• DCT coefficients are next applied to quantizer 125 for quantization.
• quantized DCT coefficients are then applied to a Variable Length Coder 130 and combiner 175.
• DCT Discrete Coefficient Transformation
• the quantized DCT coefficients are also applied to inverse quantizer 135 to restore the DCT coefficients.
• the restored DCT coefficient are not exactly the same as the original DCT values as some information is lost in the quantization process.
• the inverse quantized coefficients are next applied to inverse DCT 140 to recover the original pixel element after DCT and quantization processing. Similarly, a known difference between the original pixel elements and the restored pixel elements exists because some information is lost in the quantization process.
• the recovered pixel elements are applied to motion estimator/motion compensator 145.
• the motion estimated/compensated signal is then applied to summing device 115 to be combined with the original image 110.
• the summed image 150 is also applied to summing device 155 along with the recovered pixel elements output from inverse DCT 140.
• the output of summing device is a residual element between the original signal 110 and recovered base layer image.
• the residual image is concurrently applied to enhancement layer encoder 160 and significance map encoder 165.
• the results of significance map encoder 165 are further applied to enhancement encoder 170 for mapping the bit planes as will be more fully described.
• the outputs of enhancement layer 170 and sigmficance map 165 are applied to combiner 180 and the combined output applied to combiner 175.
• the output 190 of combiner 175 may then be transmitted over a network or stored for subsequent transmission.
• Figure 2a illustrates an image frame 200 containing significant information, such as changes in boundaries, color or texture.
• Significant images areas 210, 215, 220 may be identified using known methods.
• areas that exhibit little or no change in textual may be identified as non-significant. Consequently, little or no information regarding these areas need be transmitted.
• the determination of significant areas may be done by reviewing each pixel element.
• the determination of significant areas may be done by reviewing corresponding DCT coefficients.
• Figure 2b illustrates another aspect of the present invention, wherein a significant image area, for example 210, is associated with a plurality of blocks, corresponding macroblocks, and corresponding super-macroblocks.
• image area 210 is composed of super-macroblocks 222, 224, 226, 228, 230 and 232.
• Each super- macroblock may be partitioned into macroblocks.
• super-macroblock 222 is shown partitioned into macroblocks 240, 242, 244 and 246.
• Each macroblock 240, 242, 244 and 246 may be further partitioned into a mini-macroblock.
• macroblock 240 is shown partitioned into mini-macroblocks 250, 252, 254, and 256.
• Each mini-macroblock may be further partitioned into a block.
• mini-macroblock 250 is shown partitioned in to blocks 260, 262, 264 and 266.
• each super- macroblock may be similarly partitioned, identified and associated with macro-, mini-macro-, and blocks.
• block 260 contains information associated with an 8x8 configuration of pixel elements. Furthermore, mini-macroblock 250 is associated with a 16x16 configuration of pixel elements, macroblock 240 is associated with a 32x32 configuration of pixel elements and super-macroblock 222 is associated with a 64x64 configuration of pixel elements.
• block 260 is analogous with the DCT encoding of a corresponding block of pixel elements.
• Figure 2c illustrates the bit-plane mapping 270 of the identified significant area 210 in bit planes 272, 274, and 276 in accordance with the preferred embodiment of the invention. In this case the enhancement layer is encoded using a three-bit-bitplane.
• bit-planes may be any number and there is no intention to limit the bit-plane depth to that shown herein.
• area 210 and associated super- macroblocks, macroblocks, mini-macro blocks, and blocks may be readily identified.
• Figure 3a illustrates a flow chart of an exemplary process 300 for significance mapping in accordance with the principles of the invention.
• significance mapping is initiated at an arbitrarily selected bit plane associated with the image or picture.
• the bit-plane associated with the most-significant bits i.e, bit-plane 0 is selected at block 305.
• a significance map associated with the selected bit plane is determined.
• the significance map associated with the bit- plane is coded.
• the texture of the blocks identified as being significant are coded and a bit- wise representation of the significance map is generated. This bit- wise representation of the significance map can be decoded at the receiving device to understand the significance map.
• FIG. 325 a determination is made whether all the bit planes associated with the image have been processed. If the answer is negative, then a next/subsequent bit plane is selected at block 332 and the significance mapping process continues for selected next/subsequent bit plane. If, however, the answer is in the affirmative, then a determination is made at block 330 whether all the images have been processed. If the answer is negative, then a next/subsequent image or picture is selected at block 334. The significance mapping process then continues for each bit plane in the selected next/subsequent image or picture.
• Figure 3b illustrates a flow chart of an exemplary significance mapping process 310. In this exemplary process an initial block size and associated minimum and maximum block sizes are determined at block 340.
• an initial block size associated with the preferred block size is depicted.
• the block is marked or identified as being insignificant at block 370.
• a determination is made at block 360 whether the last block has been reached. If the answer is negative, then a next/subsequent block in the bit plane is selected at block.365. Processing continues on the selected next/subsequent block at block 345.
• Processing then continues on each of the successively larger block until the block size exceeds a maximum block size at block 375.
• FIG. 4 illustrates an exemplary embodiment of a system 400 that may be used for implementing the principles of the present invention.
• System 400 may represent a TV transmitter or receiving system, a desktop, laptop or palmtop computer, a personal digital assistant (PDA), a video/image storage apparatus such as a video cassette recorder (VCR), a digital video recorder (DNR), a TiNO apparatus, etc., as well as portions or combinations of these and other devices.
• System 400 may contain one or more input/output devices 402, processors 403, and memories 404, which may access one or more sources 401 that contain video images.
• Sources 401 may be stored in permanent or semi-permanent media such as a television receiver (SDTV or HDTV), a VCR, RAM, ROM, hard disk drive, optical disk drive or other video image storage devices. Sources 401 may alternatively be accessed over one or more network connections 410 for receiving video from a server or servers over, for example a global computer communications network such as the Internet, a wide area network, a metropolitan area network, a local area network, a terrestrial broadcast system, a cable network, a satellite network, a wireless network, or a telephone network, as well as portions or combinations of these and other types of networks.
• a global computer communications network such as the Internet, a wide area network, a metropolitan area network, a local area network, a terrestrial broadcast system, a cable network, a satellite network, a wireless network, or a telephone network, as well as portions or combinations of these and other types of networks.
• Input/output devices 402, processors 403, and memories 404 may communicate over a communication medium 406.
• Communication medium 406 may represent for example, a bus, a communication network, one or more internal connections of a circuit, circuit card or other apparatus, as well as portions and combinations of these and other communication media.
• Input data from the sources 401 is processed in accordance with one or more software programs that may be stored in memories 404 and executed by processors 403 in order to supply fractionally encoded video images to network 420.
• the fractionally encoded vided images may be transmitted to a storage device, or may be transmitted to a display system for real-time viewing of the encoded video image.
• Processors 403 may be any means, such as general purpose or special purpose computing system, or may be a hardware configuration, such as a laptop computer, desktop computer, handheld computer, dedicated logic circuit, integrated circuit, Programmable Array Logic (PAL), Application Specific Integrated Circuit (ASIC), etc., that provides a known output in response to known inputs.
• PAL Programmable Array Logic
• ASIC Application Specific Integrated Circuit
• the coding and decoding employing the principles of the present invention may be implemented by computer readable code executed by processor 403.
• the code may be stored in the memory 404 or read/downloaded from a memory medium such as a CD-ROM or floppy disk (not shown).
• hardware circuitry may be used in place of, or in combination with, software instructions to implement the invention.
• the elements illustrated herein may also be implemented as discrete hardware elements.
• the term processor may represent one or more processing units or computing units in communication with one or more memory units and other devices, e.g., peripherals, connected electronically to and communicating with the at least one processing unit.
• the devices may be electronically connected to the one or more processing units via internal busses, e.g., ISA bus, microchannel bus, PCI bus, PCMCIA bus, etc., or one or more internal connections of a circuit, circuit card or other device, as well as portions and combinations of these and other communication media or an external network, e.g., the Internet and Intranet.

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• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Compression Or Coding Systems Of Tv Signals (AREA)
• Image Processing (AREA)
• Compression, Expansion, Code Conversion, And Decoders (AREA)

Applications Claiming Priority (5)

Publications (1)

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• 2003
  • 2003-03-04 KR KR10-2004-7013637A patent/KR20040091682A/ko not_active Application Discontinuation
  • 2003-03-04 WO PCT/IB2003/000789 patent/WO2003075579A2/en not_active Application Discontinuation
  • 2003-03-04 CN CNA038052415A patent/CN1640146A/zh active Pending
  • 2003-03-04 JP JP2003573878A patent/JP2005519543A/ja not_active Withdrawn
  • 2003-03-04 AU AU2003208500A patent/AU2003208500A1/en not_active Abandoned
  • 2003-03-04 EP EP03706790A patent/EP1483918A2/en not_active Withdrawn

Non-Patent Citations (1)

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