Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/66—Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
  • G06F15/163—Interprocessor communication
  • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/64—Hybrid switching systems
  • H04L12/6402—Hybrid switching fabrics
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/20—Support for services
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L61/00—Network arrangements, protocols or services for addressing or naming
  • H04L61/35—Network arrangements, protocols or services for addressing or naming involving non-standard use of addresses for implementing network functionalities, e.g. coding subscription information within the address or functional addressing, i.e. assigning an address to a function
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L61/00—Network arrangements, protocols or services for addressing or naming
  • H04L61/50—Address allocation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
  • H04L69/14—Multichannel or multilink protocols

Definitions

• the present application relates, in general, to data communications involving at least one data communications network.
• Data communications is the transfer of data from one or more sources to one or more sinks that is accomplished (a) via one or more data links between the one or more sources and one or more sinks and (b) according to a protocol.
• a data communications network is the interconnection of two or more communicating entities (i.e., data sources and/or sinks) over one or more data links.
• a packet-switched network 100 and a circuit-switched network 102 Depicted is an aggregation device 104 interposed between the packet-switched network 100 and the circuit-switched network 102. Illustrated are a Personal Computing (PC) device 108 and a voice device 112, both of which are shown interfaced with the aggregation device 104 via the circuit switched network 102.
• PC Personal Computing
• FIG. IB depicted is the block diagram of Figure 1A showing the aggregation device 104 in an exploded view. Illustrated internal to the aggregation device 104 are a host processor 114, and multi-line bus (e.g., a Peripheral Component Interconnect (PCI) bus) devices 118, connected with a multi-line bus (e.g. , a PCI bus) 116. In operation, all data that transit the aggregation device 104 must be processed by and transit the host processor 114.
• PCI Peripheral Component Interconnect
• the host processor 114 generally determines whether each multi-line bus device 118 has data via polling (e.g., "round robin" polling). Ifthe polling does indicate that data are present at a particular multi-line bus device 118, the host processor 104 then directs that particular multi-line bus device 118 to deliver data to the host processor 104 via multi-line bus 116. Thereafter, the host processor 104 processes the received data as appropriate and subsequently transmits packetized data out over the packet-switched network 100.
• polling e.g., "round robin" polling
• the host processor 114 With respect to data transiting the aggregation device in a direction from the packet-switched network 100 to the circuit- switched network 102, the host processor 114 generally receives packetized data from the packet-switched network 100. Thereafter, the host processor 114 processes the received packetized data as appropriate and transmits the processed data to the appropriate multiline bus device 118 via the multi-line bus 116.
• the inventors have recognized that, insofar as in the related art all data transiting aggregation device 104 transits the host processor 114, the host processor 114 serves as a bottleneck for data transmission.
• a system includes but is not limited to a low-processor- load aggregation device interposed between a network and at least one network station, said low-processor-load aggregation device having: (a) at least one multi-channel device, said multi-channel device having at least one internal network tag associated with the at least one network station, and (b) a host-processor-controlled routing device operably coupled with the network, said host-processor-controlled routing device configured to coordinate at least one network address with the at least one internal network tag associated with the at least one network station.
• a method includes but is not limited to coordinating an external network packet with an internal private-network address of a low-processor-load aggregation device.
• said coordinating an external network packet with an internal private-network address of the low-processor-load aggregation device is characterized by coordinating the external network packet with at least one internal private-network address of at least one multi-channel device.
• said coordinating the external network packet with at least one internal private-network address of at least one multi-channel device is characterized by coordinating the external network packet with the at least one internal private-network address on the basis of a content of the external network packet.
• said coordinating the external network packet with the at least one internal private-network address on the basis of a content of the external network packet is characterized by coordinating the external network address with an internal private- network address on the basis of a Voice-Over-IP, Modem-Over-IP, or Fax-Over-IP content of the external network packet.
• said coordinating the external network packet with at least one internal private-network address of at least one multi-channel device is characterized by coordinating the external network packet with the at least one internal private-network address on the basis of a header of the external network packet.
• coordinating an external network address of the packet with at least one internal private-network address of at least one multi-channel device is characterized by coordinating the external network address with at least one internal private-network device uniquely associated with the at least one multichannel device.
• said coordinating an external network address of the packet with at least one internal private-network address of at least one multi-channel device is characterized by coordinating the external network address with at least one NLAN tag internal to the at least one multi-channel device.
• said coordinating the external network address with at least one NLAN tag internal to the at least one multi-channel device is characterized by coordinating the external network address with at least one VLAN tag internal to the at least one multichannel device, where the at least one VLAN tag is associated with a channel unit maintaining a logical channel with at least one network station.
• the network station comprises a network station selected from the network- station group including but not limited to a PC device, a voice device, and a fax device.
• said coordinating an external network packet with an internal private-network address of a low-processor-load aggregation device is characterized by coordinating the external network address with an internal private- network address of a host processor.
• said coordinating the external network address with an internal private-network address of a host processor is characterized by directing at least a part of a packet having the external network address to the internal private-network address of the host processor.
• said coordinating the external network address with an internal private-network address of a host processor is characterized by directing at least a part of a packet having the external network address to a channel unit internal to the internal private- network address of the host processor.
• the internal private-network address is characterized by an Ethernet-protocol address.
• related systems include but are not limited to circuitry and/or programming for effecting the foregoing-referenced method embodiments; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the foregoing- referenced method embodiments depending upon the design choices of the system designer.
• a method includes but is not limited to coordinating an external network-station packet with at least one internal private-network address of at least one multi-channel device.
• said coordinating an external network-station packet with at least one internal private-network address of at least one multi-channel device is characterized by coordinating the external network-station packet with the at least one internal private-network address on the basis of a content of the external network-station packet.
• said coordinating the external network-station packet with the at least one internal private-network address on the basis of a content of the external network-station packet is characterized by coordinating the external network-station address with an internal private-network address of a host processor on the basis of a content of the external network-station packet.
• said coordinating the external network-station address with an internal private-network address of a host processor on the basis of a content of the external network-station packet is characterized by coordinating the external network- station address with an internal private-network address of a host processor on the basis of a PPP control command content of the external network-station packet.
• said coordinating the external network-station packet with the at least one internal private-network address on the basis of a content of the external network-station packet is characterized by coordinating the external network-station address with an internal private-network address of a routing device on the basis of a header of the external network-station packet.
• the internal private-network address is characterized by an Ethernet-protocol address.
• related systems include but are not limited to circuitry and/or programming for effecting the foregoing-referenced method embodiments; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the foregoing- referenced method embodiments depending upon the design choices of the system designer.
• a method includes but is not limited to coordinating an external network-station control message with an internal private-network address of a low-processor-load aggregation device.
• said coordinating an external network-station control message with an internal private-network address of a low-processor-load aggregation device is characterized by coordinating the external network-station control message with the at least one internal private-network address.
• the control message comprises a PPP control message.
• the internal private-network address is characterized by an Ethernet-protocol address.
• related systems include but are not limited to circuitry and/or programming for effecting the foregoing-referenced method embodiments; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the foregoing- referenced method embodiments depending upon the design choices of the system designer.
• Figure 1A shows a packet-switched network 100 and a circuit-switched network 102.
• Figure IB depicts the block diagram of Figure 1 A showing the aggregation device 104 in an exploded view.
• Figure 2 shows the block diagram of Figure IB, modified to depict a low- processor-load aggregation device 250 interposed between the packet-switched network 100 and the circuit-switched network 102.
• Figure 8 A shows a host processor 202 operably coupled (e.g. , via a coaxial cable) with a broadcast-capable switch 204 (e.g., an Ethernet bridge, switch, or hub).
• Figure 8B depicts that the host processor 202 has directed the broadcast- packet-processing devices 216, 226, 236 to enter an ignore-initial-address-assignment mode via placing "ignore" values on all attend-ignore lines 810, 820, 830.
• Figure 8C illustrates that the host processor 202 has directed a broadcast- packet-processing device 216 to enter a process-initial-address-assignment mode via placing an "attend" value on that first broadcast-packet-processing device's 216 attend- ignore line 810.
• Figure 8D shows that the host processor 202 has transmitted a broadcast packet containing payload having a first address-assignment message (e.g. , a message that an Ethernet device is to be assigned a MAC address), which the broadcast-capable switch 204 has routed onto shared medium 255.
• a first address-assignment message e.g. , a message that an Ethernet device is to be assigned a MAC address
• Figure 8E depicts that the broadcast-packet-processing device 216 having an "attend" value on its attend-ignore line 810 processes the broadcast packet and passes the first-address assignment message to its address-assignment-recognition device 812.
• Figure 8F illustrates that the host processor 202 has directed a second broadcast-packet-processing devices 226 to enter a process-initial-address-assignment mode via placing an "attend" value on that second broadcast-packet-processing device's 226 attend-ignore line 820.
• Figure 8G shows that the host processor 202 has transmitted a broadcast packet containing payload having a second address-assignment message, which the broadcast-capable switch 204 has routed onto shared medium 255.
• Figure 8H depicts that the first and second broadcast-packet-processing devices 216, 226 respectively having an "attend" value on their attend-ignore lines 810, 820, respectively process the broadcast packet and pass the second address-assignment message to their respective internal address-assignment-recognition devices 812, 822.
• Figure 81 shows that the address-assignment-recognition device (e.g. , MAC address-assignment-recognition device) 822 has an assignment status equal to "second- address assigned", and that its associated broadcast-packet-processing device (e.g., Ethernet device) 226 has an address status equal to second-address as a result of the operations described in relation to Figure 8E.
• Figure 8 J shows an alternate embodiment of the system shown in Figure 8A.
• Figure 9A shows multi-channel devices 218, 228, 238 in the context of a system wherein packet-processing devices 216, 226, 236 have pre-assigned addresses.
• FIG. 9B shows that in one implementation, when multi-channel channel device 218 having slaved initial boot packet processing device 910 has respectively booted, slaved initial boot packet processing device 910 transmits a packet having a destination address of the host processor 202 and a source address of the packet-processing device 216.
• Figure 3 A shows a standard routing device 210 receiving an inbound packet 300 having payload containing voice (e. g. , voice over IP) contents of a type which the low- processor-load aggregation device 210 is expected to process (rather than just pass on).
• voice e. g. , voice over IP
• Figure 3B depicts that upon receipt of the Ethernet frame 302, the device having the MAC address of the Ethernet frame 302 strips the Ethernet header and hands the residual VLAN-tagged packet 304 into multi-channel device 228.
• Figure 3C depicts that upon receipt of the PCM data from the voice device 112, the channel unit (e. g. , channel unit_2) converts the PCM data into an outbound voice- over-IP packet 308 appropriately addressed to and bound for the external packet-switched network 100 ( Figure 2) and thereafter hands the voice-over-IP packet 308 to the Ethernet device 226, which encapsulates the voice-over-IP packet 308 into an Ethernet frame 310 which has as its destination address the MAC address of the host-processor-controlled aggregation-unit-specific routing device 200.
• the channel unit e. g. , channel unit_2
• Figure 3D illustrates that Ethernet switch 204 switches Ethernet frame 310 to host-processor-controlled aggregation-unit-specific routing device 200.
• Figure 4 A shows the standard routing device 210 receiving an inbound- packet 400, where the inbound-packet 400 has payload which low-processor-load aggregation device 250 is not expected to process.
• Figure 4B depicts that upon receipt of the Ethernet frame 402, the device having the MAC address of the Ethernet frame 402 strips the Ethernet header and hands the residual VLAN-tagged packet 404 into multi-channel device 228.
• Multi-channel device
• VLAN-tagged packet 404 to the VLAN unit (e.g. , VLAN Unit_3 as shown in Figure 4B) identified by the VLAN tag of the VLAN-tagged packet 404.
• Figure 4C depicts that upon receipt of an outbound packet 408 appropriately addressed to and bound for the external packet-switched network 100 ( Figure 2), multichannel device 228 hands the outbound packet 408 to the Ethernet device 226, which encapsulates the outbound packet 408 into an Ethernet frame 410 which has as its destination address the MAC address of the host-processor-controlled aggregation-unit- specific routing device 200.
• FIG. 4D illustrates that Ethernet switch 204 switches Ethernet frame 410 to host-processor-controlled aggregation-unit-specific routing device 200.
• Figures 4E-4F show the situation where the PC device 108 is expecting the low-processor-load aggregation device 250 to provide some control functions related to the NCP and LCP control aspects of the PPP protocol.
• Figure 5 shows a high-level block diagram depicting an implementation of a method, in the context of the low-processor-load aggregation device 250, wherein control information is routed to the host processor 202.
• Figure 6A shows a high-level logic flowchart depicting a method and system.
• Figure 6B depicts that the channel unit passes the payload 602 to the attached Ethernet device 226 with instructions that payload be encapsulated in an Ethernet frame 604 having the MAC address of the host processor 202 and thereafter transmits the Ethernet frame 604 via the Ethernet bus 255.
• FIG 7A shows that the host processor 202 causes an Ethernet frame 700, having control information destined for the host processor's 202 counterpart — which not shown, but which is somewhere out in the packet-switched network 100 - to be transmitted, via Ethernet switch 204, out onto the Ethernet bus 255.
• Figure 7B depicts that the channel unit passes the payload 702 to its associated VLAN unit (e.g., VLAN Unit_2, which is illustrated as associated with the channel unit_2), which creates a VLAN-tagged packet 704.
• VLAN Unit_2 which is illustrated as associated with the channel unit_2
• FIG. 2 shown is the block diagram of Figure IB, modified to depict a low-processor-load aggregation device 250 interposed between the packet-switched network 100 and the circuit-switched network 102. Depicted is that the low-processor-load aggregation device 250 interfaces with a standard routing device 210, which as shown handles routing without any knowledge of the internal structure of the- low-processor-load aggregation device 250.
• the standard routing device 210 is shown spanning the boundary of the-low-processor-load aggregation device 250 in order to illustrate that in some implementations, the-low-processor-load aggregation device 250 can be made backwards compatible with legacy routing devices and networks having no knowledge of the-low-processor-load aggregation device 250, while in other implementations the-low-processor-load aggregation device 250 can be implemented as integral with a routing device having the functionality of both the standard routing device 210 and a host-processor-controlled aggregation-unit-specific routing device 200 (e.g.
• the standard routing device 210 is described herein as functionally separate from the host-processor-controlled aggregation-unit-specific routing device 200 in order to most clearly highlight the operation of each component.
• host-processor-controlled aggregation-unit-specific routing device 200 is interposed between the standard routing device 210 and an Ethernet switch 204. While an Ethernet protocol switch is described herein for sake of conceptual clarity, those having ordinary skill in the art will appreciate that other like switches can be substituted for the Ethernet switch 204 via a minimum degree of experimentation well within the ambit of one having ordinary skill in the art.
• host- processor-controlled aggregation-unit-specific routing device 200 is controlled by the host processor 202 to add/remove headers to packets in various fashions described following. Shown is that the Ethernet switch 204 is connected to an Ethernet bus 255.
• Ethernet bus 255 is described herein as a shared-medium bus for sake of conceptual clarity, the teachings herein may be adapted to non-shared medium buses (e.g., non-shared medium Ethernet buses), via a minimum amount of experimentation well within the ambit of one having ordinary skill in the art.
• non-shared medium buses e.g., non-shared medium Ethernet buses
• the low-processor-load aggregation device 250 is illustrated herein as being composed of a "hybrid" network. That is, the host processor 202 and the host-processor-controlled aggregation-unit-specific routing device 200 are shown herein as being attached to non- shared mediums each of which is attached to unique ports of the switch 204, while the remaining Ethernet devices 216, 226, 236 are shown herein as being attached to a shared medium 255, where shared medium 255 is shown attached to a unique port of the switch 204.
• low-processor-load aggregation unit 250 is illustrated herein as being composed of a hybrid system, those skilled in the art will appreciate that the low-processor- load aggregation unit 250 is also illustrative of non-hybrid systems. For example, those skilled in the art will appreciate that the low-processor-load aggregation unit 250 is also illustrative of non-hybrid "shared medium" systems where host processor 202, the host- processor-controlled aggregation-unit-specific routing device 200, and the remaining Ethernet devices 216, 226, 236 are all attached to a shared medium 255 (thereby obviating the requirement for switch 204).
• the low-processor-load aggregation unit 250 is also illustrative of non- hybrid "switched" systems wherein the host processor 202, the host-processor-controlled aggregation-unit-specific routing device 200, and the remaining Ethernet devices 216, 226, 236 are each respectively individually attached to their own non-shared mediums, where each non-shared medium respectively attaches to a unique port of the switch 204.
• the foregoing non-hybrid systems can be implemented in light of the teachings herein via minimal experimentation well within the ambit of one having ordinary skill in the art.
• each multi-channel device may access interfaces provided by the underlying circuit switched network, as necessary, in order to establish and support at least one end of a channel, the opposite end of which is expected to be provided by some network-station device (e.g., PC device 108, or voice device 112) across an underlying intervening network (e.g. , the underlying circuit-switched network 102).
• some network-station device e.g., PC device 108, or voice device 112
• an underlying intervening network e.g. , the underlying circuit-switched network 102
• each Ethernet device 216, 226, 236 be uniquely assigned. There are many ways in which such assignment may be done, but one way in which such assignment may be done is illustrated immediately following.
• host processor 202 operably coupled (e.g., via a coaxial cable) with a broadcast-capable switch 204 (e.g., an Ethernet bridge, switch, or hub).
• a broadcast-capable switch 204 e.g., an Ethernet bridge, switch, or hub.
• three broadcast-packet-processing devices e.g., Ethernet devices
• 216, 226, 236 operably coupled via a shared medium 255 (e.g., an Ethernet bus, which those having ordinary skill in the art will recognize may consist of either or both a shared medium and a non-shared medium) with the broadcast-capable switch 204.
• a shared medium 255 e.g., an Ethernet bus, which those having ordinary skill in the art will recognize may consist of either or both a shared medium and a non-shared medium
• all three broadcast-packet-processing devices 216, 226, 236 are respectively operably coupled with the host processor via attend-ignore lines 810, 820, 830.
• the host processor 202 has directed the broadcast-packet-processing devices 216, 226, 236 to enter an ignore-initial- address-assignment mode via placing "ignore" values on all attend-ignore lines 810, 820, 830.
• the host processor 202 has directed a broadcast-packet-processing device 216 to enter a process-initial-address- assignment mode via placing an "attend" value on that first broadcast-packet-processing device's 216 attend-ignore line 810.
• the host processor 202 has transmitted a broadcast packet containing payload having a first address-assignment message (e.g. , a message that an Ethernet device is to be assigned a MAC address), which the broadcast-capable switch 204 has routed onto shared medium 255.
• a first address-assignment message e.g. , a message that an Ethernet device is to be assigned a MAC address
• the broadcast-packet-processing device 216 having an "attend" value on its attend-ignore line 810 processes the broadcast packet and passes the first-address assignment message to its address-assignment- recognition device 812.
• the internal address-assignment-recognition device 812 Upon receipt of the first-address assignment message, the internal address-assignment-recognition device 812 recognizes that its associated broadcast-packet processing device 216 does not yet have an assigned address. Accordingly, shown is that internal address-assignment-recognition device 812 accepts the first address assignment message, assigns "first address" to its broadcast-packet processing device 216, and thereafter sends an acknowledgment of the first-address assignment message to the host processor 202 to indicate that the "first-address assignment" has been completed.
• the host processor 202 has directed a second broadcast-packet-processing devices 226 to enter a process-initial- address-assignment mode via placing an "attend" value on that second broadcast-packet- processing device's 226 attend-ignore line 820.
• the address- assignment-recognition device e.g. , MAC address-assignment-recognition device
• the address- assignment-recognition device e.g. , MAC address-assignment-recognition device
• its associated broadcast- packet-processing device e.g., Ethernet device
• FIG. 8G shown is that the host processor 202 has transmitted a broadcast packet containing payload having a second address-assignment message, which the broadcast-capable switch 204 has routed onto shared medium 255.
• FIG 8H depicted is that the first and second broadcast- packet-processing devices 216, 226 respectively having an "attend" value on their attend- ignore lines 810, 820, respectively process the broadcast packet and pass the second address-assignment message to their respective internal address-assignment-recognition devices 812, 822.
• the internal address-assignment-recognition device 812 associated with the first broadcast-packet- processing device 216 Upon receipt of the second address-assignment message, the internal address-assignment-recognition device 812 associated with the first broadcast-packet- processing device 216 recognizes that its associated broadcast-packet processing device 216 has already been assigned an address (via its Assignment Status equal to "first-address assigned"), and hence ignores the second address-assignment message.
• the internal address- assignment-recognition device 822 associated with the second broadcast-packet-processing device 226 which does not yet have an assigned address recognizes that its associated broadcast-packet processing device 226 has not already been assigned an address, and hence shown is that the internal address-assignment-recognition device 822 associated with the second broadcast-packet-processing device assigns the second packet-processing device 226 the second address indicated by second-address assignment message, and thereafter sends an acknowledgment to the host processor 202 that the second address assignment has been accepted.
• the address-assignment- recognition device e.g., MAC address-assignment-recognition device
• its associated broadcast- packet-processing device e.g. , Ethernet device
• Figures 8B-8I have described the assignment of address to two of the three broadcast-packet-processing devices 206.
• the remaining (third) broadcast-packet-processing device 206 is thereafter assigned its address via a straightforward extension of the procedure illustrated in Figures 8G-8I, where such extension is well within the ambit of one having ordinary skill in the art.
• Figures 8G-8I where such extension is well within the ambit of one having ordinary skill in the art.
• the scheme described herein can be extended to many (e.g. , hundreds) of broadcast-packet-processing devices via reasonable experimentation well within the ambit of one having ordinary skill in the art.
• FIG. 8J shown is an alternate embodiment of the system shown in Figure 8 A.
• the system shown in Figure 8 J is substantially similar to that shown in 8A, with the exception that the host processor 202 is shown to be operably coupled with only one of the broadcast-packet-processing devices 216 via its attend-ignore line 810. Depicted is that the remaining two broadcast-packet-processing devices 226, 236 are respectively operably coupled with each other via their respective attend-ignore lines 821, 831.
• assigning addresses to the packet-processing-devices via the alternate system shown in Figure 8J is done in a fashion based upon a straightforward extension of the process described in relation to Figure 8 A, except that "daisy-chaining" is used to sequentially control the attend-ignore lines 810, 821, 831.
• the host processor 202 causes an attend value to appear on the attend-ignore line 810 of the first packet-processing-device 216, and then causes a first address to be assigned to the first packet-processing-device 216.
• the first packet processing device 216 causes an attend value to appear on the second attend-ignore line 821 which feeds into a second packet-processing-device, and then causes a second address to be assigned to the second packet-processing-device 226.
• the second packet processing device 226 causes an attend value to appear on the third attend-ignore line 831 which feeds into the third packet-processing- device 236, and then causes a third address to be assigned to the third packet-processing- device 236.
• the address assignments are done in a substantially similar fashion to that described in relation to Figures 8B-8I, except for the fact that daisy chaining, rather than direct control by the host processor 202, is used to control the attend-ignore lines of the second and third packet processing devices 206.
• daisy chaining rather than direct control by the host processor 202, is used to control the attend-ignore lines of the second and third packet processing devices 206.
• the attend values remain on the attend-ignore lines after respective address assignments, while in other implementations, ignore values are placed on the attend-ignore lines after respective address assignments.
• Such transmission is characterized by the host processor 202 repetitively transmitting each broadcast packet containing payload having a specific-address assignment messages until an acknowledgement from the specific address has been received by the host processor 202.
• the host processor 202 will intermittently retransmit the broadcast packet having the first-address assignment message until the host processor 202 receives an acknowledgement that the first address-assignment has been achieved.
• the broadcast-packet-processing devices have been assigned their addresses (e.g. , Ethernet devices have been assigned their unique MAC addresses). It is now desirable to activate the multi-channel devices 208 uniquely connected with the addressed broadcast-packet-processing devices. In one implementation, this is achieved via booting the multi-channel devices.
• multi-channel devices 218, 228, 238 in the context of a system wherein packet-processing devices 216, 226, 236 have pre- assigned addresses.
• packet-processing devices 216, 226, 236 have been pre-assigned their addresses via one or more of the addressing schemes described in Section I ("assigning addresses to packet-network devices"), above.
• the packet-processing devices 216, 226, 236 have had their addresses assigned in other ways (e.g. , via ROM, as is conventionally done).
• each multi-channel device 218, 228, 238 respectively has an internal slaved initial boot packet processing device 910, 920, 930 and boot-control code ROM 912, 922, 932.
• the multichannel devices 218, 228, 238 are substantially indistinguishable from each other, while in other implementations individual multi-channel devices differ.
• Figure 9A illustrates the host processor 202 initiating transmission of at least one packet containing payload having an initial boot-up message, which packet switch 204 transmits onto shared medium 255.
• a single broadcast packet containing the initial boot-up message is transmitted.
• packets individually addressed to the packet-processing devices, each such packet containing the initial boot-up message are transmitted.
• each multi-channel device 218, 228, 238 Upon receipt of the packet containing the initial boot up message, each multi-channel device 218, 228, 238 delivers the boot-up message to its respective slaved initial boot packet processing device 910, 920, 930. Thereafter, each slaved initial boot packet processing device 910, 920, 930 respectively boots from its respective boot-control code ROM 912, 922, 932.
• slaved initial boot packet processing device 910 transmits a packet having a destination address of the host processor 202 and a source address of the packet- processing device 216.
• the host processor 202 has knowledge of all active packet-processing devices 216, 226, 236 on the shared medium 255 (either because the addresses are pre-assigned or because the host processor has assigned the addresses as in Section I, above), the host processor 202 can treat those known addresses as the "set" of addresses.
• the host processor 202 can add the source address of the packet in which the acknowledgment was contained to a set of "booted-up" addresses (if the source addresses are not already represented in the set of received addresses). Thereafter, the host processor can compare the set of received "booted-up" addresses against the set of the known earlier-assigned packet-processing device addresses (e.g. , first-address, second-address, and third-address in Figures 9A, 9B), and can continue retransmitting the booted-up message packets until the set of received booted-up addresses matches the set of known addresses.
• the known earlier-assigned packet-processing device addresses e.g. , first-address, second-address, and third-address in Figures 9A, 9B
• the host processor 202 retransmits a boot-up message ifthe host processor 202 has not received acknowledgement from all multi-channel devices that an earlier-sent boot-up message has been processed. The possibility exists that the device has been booted up, but that for some reason the acknowledgment has been lost. Accordingly, in one implementation when a slaved initial boot packet processing device receives a boot-up message, but the multi-function device having the slaved initial boot packet processing device which received the boot-up message has already booted, the slaved initial boot packet processing device determines that boot- control code has previously been executed, and hence does not reboot. However, the slaved initial boot packet processing device does send an acknowledgment of the duplicate boot-up message.
• FIGS. 3A-3E shown are a series of high-level block diagrams depicting an implementation of a method in the context of a partial view of the-low-processor-load aggregation device 250, where the low-processor-load aggregation device 250 is expected to provide some level of voice data processing.
• FIG 3 A shown is standard routing device 210 receiving an inbound packet 300 having payload containing voice (e.g. , voice over IP) contents of a type which the low-processor- load aggregation device 210 is expected to process (rather than just pass on).
• voice e.g. , voice over IP
• voice over IP contents of a type which the low-processor-load aggregation device 210 is expected to process (rather than just pass on)
• voice contents of a type which the low-processor-load aggregation device 210 is expected to process are representative of other types of contents which the low-processor-load aggregation device 210 is expected to process (rather than just pass on).
• Examples of such other types of contents which the low-processor-load aggregation device 210 is expected to process are Fax over IP (e.g., International Telecommunications Union (ITU) T.38) contents, Modem Over IP (e.g., Telecommunications Industry Association (TIA) TR 30.1) contents, and other contents recognized as analogous to the foregoing by those having ordinary skill in the art.
• Fax over IP e.g., International Telecommunications Union (ITU) T.38
• Modem Over IP e.g., Telecommunications Industry Association (TIA) TR 30.
• standard routing device 210 examines the destination address in the header of the inbound packet 300, and determines from its (standard routing device's 210) internal routing table that the destination address of the inbound packet 300 header is associated with the port(s) of the standard routing device 210 that feed into the host-processor-controlled aggregation-unit-specific routing device 200, and consequently routes the inbound packet "downward" to the host-processor-controlled aggregation-unit-specific routing device 200.
• the host-processor-controlled aggregation-unit-specific routing device 200 has been earlier configured by the host processor 202 to recognize that the address of the received inbound packet 300 is an address that is potentially associated with a channel involving the voice device 112 (in one implementation, this potential association is recognized via inbound packet 300 being addressed to the one or more packet network addresses associated with the host-processor-controlled aggregation-unit-specific routing device 200), where the voice device 112 is expecting the low-processor-load aggregation device 250 to provide processing of voice data (e.g., Pulse Code Modulated (PCM) data).
• voice data e.g., Pulse Code Modulated (PCM) data
• the host-processor-controlled aggregation-unit-specific routing device 200 looks relatively deeply into the received inbound packet 300 to see ifthe port identification of the packet (e.g. inbound packet's 300 User Datagram Protocol (UDP) Port ifthe packet switched network 100 is using IP) is one that the host processor 202 has earlier established is a port identifier that is potentially associated with expected voice processing.
• the port identification of the packet e.g. inbound packet's 300 User Datagram Protocol (UDP) Port ifthe packet switched network 100 is using IP
• UDP User Datagram Protocol
• the host-processor- controlled aggregation-unit-specific routing device 200 determines that the port identification of the packet is one that the host processor 202 has earlier indicated as a port identifier that is potentially associated with expected voice processing, the host-processor- controlled aggregation-unit-specific routing device 200 maps the known inbound packet to at least one logical channel uniquely internal to at least one multi-channel device, said mapping based on both the network and port addresses of the inbound packet 300; for example, in the case where the packet switched network 100 is using Internet Protocol (IP), the inbound packet's internet destination address and the inbound packet's user datagram protocol port number will be respectively mapped to an Ethernet MAC address uniquely associated with the multi-channel device 228 and a (Virtual Local Area Network) VLAN tag associated with at least one logical channel uniquely internal to the multi-channel device 228 (in some implementations the association is one-to-one), where the at least one logical channel is one end of a logical channel established with voice device
• IP Internet Protocol
• multi-channel device 228 is described as "associated with" the MAC address in that the association arises, in one implementation, from the fact that each of the multi-channel devices 218 ( Figure 2), 228, 238 ( Figure 2) is uniquely connected to a corresponding Ethernet device having a uniquely assigned MAC address.
• host-processor-controlled aggregation-unit-specific routing device 200 strips the packet network header from the inbound packet 300, and creates an Ethernet frame 302 having a destination MAC address associated with the multi-channel device 228, and further having, internal to the Ethernet frame, a VLAN tag associated with a "VLAN” (e.g. , VLAN_2) which is associated with a logical channel (e.g., that maintained by channel unit_2) internal to the multi-channel device 228.
• VLAN e.g. , VLAN_2
• a logical channel e.g., that maintained by channel unit_2
• VLAN tags and associated VLANs are described herein for sake of illustration, those having ordinary skill in the art can adapt the teachings herein to other tags via a minimum amount of experimentation well within the ambit of one having ordinary skill in the art.
• the inventors note that in some Ethernet implementations VLAN tags provide significant benefits in that both legacy and new Ethernet switches tend not to "see" VLAN identifiers, and hence in one implementation VLAN tags have been found to a high degree of accuracy and ease of use when utilized with the teaching provided herein. Depicted is that the Ethernet frame 302 is sent onto Ethernet bus 255 by Ethernet switch 204.
• Multi-channel device 228 delivers VLAN-tagged packet 304 to the VLAN unit (e.g. , VLAN Unit_2 as shown in Figure 3B) identified by the VLAN tag of the VLAN- tagged packet 304 (in one implementation, this association between VLAN and channel unit is recognized on the basis of control information earlier-sent to multi-channel device 228 by host processor 202).
• VLAN unit e.g. , VLAN Unit_2 as shown in Figure 3B
• this association between VLAN and channel unit is recognized on the basis of control information earlier-sent to multi-channel device 228 by host processor 202).
• VLAN Unit_2 removes the VLAN tag from the VLAN-tagged packet 304 and delivers the remaining voice-over-IP data to its (VLAN Unit_2's) associated channel unit (e.g., channel unit_2, as shownin Figure 3B).
• the associated channel unit converts the voice-over-IP data into its PCM representation, and then sends the PCM data to the voice device 112.
• Figures 3 A-3B demonstrated an inbound voice packet transiting the low- processor-load aggregation device 250.
• Figures 3C-3D will demonstrate an outbound voice packet transiting the low-processor-load aggregation device 250
• the channel unit e.g., channel unit__2
• the channel unit converts the PCM data into an outbound voice-over-IP packet 308 appropriately addressed to and bound for the external packet-switched network 100 ( Figure 2), and thereafter hands the voice-over-IP packet 308 to the Ethernet device 226, which encapsulates the voice-over-IP packet 308 into an Ethernet frame 310 which has as its destination address the MAC address of the host-processor-controlled aggregation-unit-specific routing device 200.
• Ethernet device 226 transmits the Ethernet frame 310 over Ethernet bus 255.
• Ethernet switch 204 switches Ethernet frame 310 to host-processor-controlled aggregation-unit-specific routing device 200. Thereafter, shown is that the host-processor-controlled aggregation-unit-specific routing device 200 removes the Ethernet headers from the Ethernet frame 310, and thereafter transmits the outbound voice-over-IP packet 308 out into the packet-switched network 100.
• Figures 3 A-3D illustrated a situation representative of those instances in which the low-host-processor-load aggregation device 250 is expected to provide voice processing for a network station device. However, in most instances, the low-host- processor-load aggregation device 250 will not be expected to provide such processing.
• Figures 4A-4F address various implementations addressing the more common case.
• FIGS. 4A-4F shown are a series of high-level block diagrams depicting an implementation of a method in the context of the low-processor-load aggregation device 250 where a network station is not expecting that the-low-processor- load aggregation device 250 will provide voice processing.
• FIG. 4A shown is the standard routing device 210 receiving an inbound-packet 400, where the inbound-packet 400 has payload which low-processor-load aggregation device 250 is not expected to process.
• Standard routing device 210 examines the destination address of the inbound-packet header, determines from its routing table that the destination address is associated with the attached aggregation device, and consequently routes the inbound packet "downward" to the host-processor-controlled aggregation-unit-specific routing device 200.
• the host-processor-controlled aggregation-unit-specific routing device 200 has been earlier configured by the host processor 202 ( Figure 2) to recognize that the address of the received inbound packet 400 is associated with a channel of a particular multi-channel device which is associated with the MAC address.
• host-processor-controlled aggregation-unit-specific routing device 200 maps the known inbound packet to at least one logical channel uniquely internal to at least one multi-channel device, said mapping based on the network address of the inbound packet 400; for example, in the case where the packet switched network 100 is using Internet Protocol (IP), the inbound packet's internet destination address will be mapped to an Ethernet MAC address uniquely associated with the multi-channel device 228 and a VLAN tag associated with at least one logical channel uniquely internal to the multi-channel device 228, where the at least one logical channel is one end of a logical channel established with data device 108 (e.g. , the logical channel maintained by channel unit_3 of multi-channel device 228).
• IP Internet Protocol
• multi-channel device is described as "associated with" the MAC address in that the association arises, in one implementation, from the fact that each of the multi-channel devices 218 ( Figure 2), 228, 238 ( Figure 2) is uniquely connected to an Ethernet device having a uniquely assigned MAC address.
• host-processor-controlled aggregation-unit-specific routing device 200 encapsulates the entire inbound packet 400 (i. e. , the entirety of the inbound packet 400, including both the payload and its associated inbound packet header), and creates an Ethernet frame 402 having a MAC destination address of Ethernet device 226 associated with multi-channel device 228, and further having, internal to the Ethernet frame, a VLAN tag associated with a "VLAN” (e.g., VLAN_3) which is associated with a logical channel (e.g. , the logical channel maintained by channel unit_3) maintained internal to the multi-channel device 228.
• VLAN e.g., VLAN_3
• VLAN tags and associated VLANs are described herein for sake of illustration, those having ordinary skill in the art can adapt the teachings herein to other tags via a minimum amount of experimentation well within the ambit of one having ordinary skill in the art.
• the inventors note that in some Ethernet implementations VLAN tags provide significant benefits in that both legacy and new Ethernet switches tend not to "see" VLAN identifiers, and hence in one implementation VLAN tags have been found to a high degree of accuracy and ease of use when utilized with the teaching provided herein. Depicted is that the Ethernet frame 402 is sent onto Ethernet bus 255 by Ethernet switch 204.
• Multi-channel device 228 delivers VLAN-tagged packet 404 to the VLAN unit (e.g. , VLAN Unit_3 as shown in Figure 4B) identified by the VLAN tag of the VLAN- tagged packet 404.
• VLAN Unit_3 removes the VLAN tag from the VLAN-tagged packet 404 and delivers the inbound packet 400, including both the payload and its associated inbound packet header, to its associated channel unit (e.g., channel unit_3 as shown in Figure 4B).
• the associated channel unit sends the inbound packet 400 to the PC device 108.
• Figure 4A-4B demonstrated an inbound non- voice packet transiting the low- processor-load aggregation device 250.
• Figures 4C-4D will demonstrate an outbound non- voice packet transiting the low-processor-load aggregation device 250.
• multi-channel device 228 hands the outbound packet 408 to the Ethernet device 226, which encapsulates the outbound packet 408 into an Ethernet frame 410 which has as its destination address the MAC address of the host-processor-controlled aggregation-unit-specific routing device 200. Thereafter, Ethernet device 226 transmits the Ethernet frame 410 over Ethernet bus 255.
• Ethernet switch 204 switches Ethernet frame 410 to host-processor-controlled aggregation-unit-specific routing device 200. Thereafter, shown is that the host-processor-controlled aggregation-unit-specific routing device 200 removes the Ethernet headers from the Ethernet frame 410, and thereafter transmits the residual outbound packet 408 out into the packet-switched network 100.
• Figures 3A-3D illustrated instances in which the low-processor-load aggregation device 250 is expected to provide processing of the contents of voice packets over an established channel.
• Figures 4A-4D illustrated instances in which the low- processor-load aggregation device 250 is only expected to forward packets and is not expected to process the contents of those forwarded packets.
• Figures 4E-4F illustrated following, illustrate instances in which the low-processor-load aggregation device 250 is expected to provide some control functions based upon specifically-identified control packets via an example based upon PPP (Point to Point Protocol) processing; the scheme in Figures 4E-4F is a hybrid of the schemes illustrated in Figures 3A-3D and 4A-4D.
• PPP Point to Point Protocol
• a network station using the low-processor-load aggregation unit 250 will expect that the low-processor-load aggregation unit 250 will support a PPP link.
• PPP is typically used to provide data link control functions between a network station (e.g., the PC device 108) and the low- processor-load aggregation device 250.
• the PPP control information generally only needs to be exchanged between the PC device 108 and the low-processor- load aggregation device 250 (i.e., the PPP control information will typically only be exchanged between the low-processor-load aggregation device 250 and a network station (e.g., PC device 108) so that data link control is maintained).
• a network station e.g., PC device 108
• FIG. 4E-4F shown is the situation where the PC device 108 is expecting the low-processor-load aggregation device 250 to provide some control functions related to the NCP and LCP control aspects of the PPP protocol.
• the PPP control information generally need only be exchanged between the PC device 108 and the low-processor-load aggregation device 250 so that data link control is maintained.
• the host processor 202 creates PPP control information (e.g. , LCP or NCP packets), appends a VLAN tag (e.g. , VLAN_3 tag) to the PPP control information, and thereafter encapsulates the entire VLAN tag-PPP control information packet in an Ethernet frame 412 having as a destination MAC address that of the Ethernet device 226 associated with the multi-channel device 228.
• PPP control information e.g. , LCP or NCP packets
• VLAN tag e.g. , VLAN_3 tag
• the Ethernet device 226 houses the channel unit (e.g., channel unit_3) associated with at least one logical channel uniquely internal to the at least one multi-channel device (the logical channel being one which carries data such as has been discussed previously), where the at least one logical channel is being encapsulated in a PPP link established between the low-processor- load aggregation device 250 and the PC device 108.
• channel unit_3 associated with at least one logical channel uniquely internal to the at least one multi-channel device (the logical channel being one which carries data such as has been discussed previously), where the at least one logical channel is being encapsulated in a PPP link established between the low-processor- load aggregation device 250 and the PC device 108.
• the Ethernet device 226 Upon receipt of the control information in the Ethernet frame 412, the Ethernet device 226 strips the Ethernet header and passes the VLAN-tagged packet into the multi-channel device 228. The multi-channel device 228 then strips the VLAN tag (e.g. , VLAN_3 tag) and hands the residual PPP control information to the appropriate channel unit (e.g., channel unit_3). Thereafter, the channel unit (e.g., channel unit_3) merges the PPP control packets that came from the host processor 202 with the PPP-encapsulated data packets (e.g.
• those PPP-encapsulated data packets that are created by putting PPP headers on the IP packets received from the host-processor-controlled aggregation-unit-specific routing device 200 are PPP-encapsulated to provide link control of the data link between the channel unit (e. g. , channel unit_3) and the PC device 108). Thereafter, the channel unit (e.g., channel unit_3) sends the PPP-encapsulated data over the PPP link maintained between the channel unit (e.g., channel unit_3) and the network station (e.g., PC device 108).
• the channel unit e.g., channel unit_3 sends the PPP-encapsulated data over the PPP link maintained between the channel unit (e.g., channel unit_3) and the network station (e.g., PC device 108).
• the multi-channel device 228 receiving an outbound packet 428 having payload containing PPP contents.
• the multichannel device 228 examines the destination address of the outbound packet's 428 header.
• the multi-channel device 228 has been earlier configured by the host processor 202 to recognize that the address of the received outbound-packet is associated with either control or data related to a channel over which PC device 108 is communicating, where the PC device 108 is expecting the low-processor-load aggregation device 250 to provide some control functions related to the NCP and LCP control aspects of the PPP protocol.
• the multi-channel device 228 looks relatively deep into the payload of the received packet to see if whether the packet contains PPP control information.
• the multi-channel device 228 maps the known inbound packet to the host processor, said mapping based on both the network address and the contents of the outbound packet; for example, encapsulating the entire outbound packet in an Ethernet frame 424 having as a MAC destination address that of the host processor 202.
• the multi-channel device 228 instructs its attached Ethernet device 226 to map the inbound packet's internet destination address to an Ethernet MAC address associated with the host- processor-controlled aggregation-unit-specific routing device 200, and thereafter send the Ethernet frame out over Ethernet bus 255 (e.g., analogous to the operations shown and described in relation to Figures 4C-4D).
• the host processor 202 processes the control command, and then communicates (e.g., via either a dedicated path (not shown) or back through the Ethernet switch 204 and the Ethernet bus 255) with the appropriate channel unit (e.g., channel unit_3) to effect whatever control command(s) was contained in the received PPP control packet.
• the system functions substantially analogous to the system described in relation to Figures 4C-4D, where data packets were described as being forwarded across the low-processor-load aggregation device 250.
• FIG. 5 shown is a high-level block diagram depicting an implementation of a method, in the context of the low-processor-load aggregation device 250, wherein control information is routed to the host processor 202.
• FIG. 5 shown is the standard routing device 210 receiving an inbound- packet 500, where the inbound-packet 500 having a payload 602 of control or unknown contents.
• Standard routing device 210 examines the destination address of the inbound- packet 500 header, determines from its routing table that the destination address is associated with the attached aggregation device, and consequently routes the inbound packet "downward" to the host-processor-controlled aggregation-unit-specific routing device 200.
• the host-processor-controlled aggregation-unit-specific routing device 200 has been configured such that, by default, it encapsulates inbound packets which it does not recognize in an Ethernet frame 510 having the MAC address of the host processor 202 and thereafter transmits the Ethernet frame 510 to the Ethernet switch 204.
• the Ethernet switch 204 thereafter transmits the Ethernet frame 510 to the host processor 202.
• the host processor processes the content of the inbound packet 500 containing the control or other unrecognized information via techniques well known to those having ordinary skill in the art.
• control information be transmitted as associated with a particular channel.
• Figures 6A-6B One implementation by which this is done is shown in Figures 6A-6B.
• FIG. 6A shown is a high-level logic flowchart depicting a method and system.
• the method depicted in Figure 6A functions substantially analogously as described in relation to Figures 3 A-3B above, except that when the payload 602 of the inbound packet 600 is ultimately received by the channel unit (e.g., channel unit_2 as shown in Figure 6A), the channel unit recognizes that the data is not voice data. Accordingly, illustrated in Figure 6B is that the channel unit passes the payload 602 to the attached Ethernet device 226 with instructions that payload be encapsulated in an Ethernet frame 604 having the MAC address of the host processor 202 and thereafter transmits the Ethernet frame 604 via the Ethernet bus 255.
• the channel unit e.g., channel unit_2 as shown in Figure 6A
• the channel unit recognizes that the data is not voice data.
• the channel unit passes the payload 602 to the attached Ethernet device 226 with instructions that payload be encapsulated in an Ethernet frame 604 having the MAC address of the host processor 202 and thereafter
• Figures 6 A-B illustrated the situation in which inbound control information, associated with a particular active channel, makes its way to the host processor 202. However, in other instances the host processor 202 may want to send control information, associated with an active channel, to the host processor's 202 counterpart (not shown) somewhere in packet-switched network 100 (e.g., such as in a Named Telephony Event (NTE)).
• Figures 7A-7B illustrate how one implementation achieves the foregoing.
• the host processor 202 causes an Ethernet frame 700, having control information destined for the host processor's 202 counterpart -.- which not shown, but which is somewhere out in the packet-switched network 100 - to be transmitted, via Ethernet switch 204, out onto the Ethernet bus 255.
• Illustrated in Figure 7A is that the payload 702 of the Ethernet frame is ultimately received by the channel unit associated with the VLAN tag (e.g. , channel unit_2 associated with the VLAN_2 tag), which examines the payload 702 and recognizes that data in payload 702 is not voice data.
• the channel unit associated with the VLAN tag e.g. , channel unit_2 associated with the VLAN_2 tag
• the channel unit passes the payload 702 to its associated VLAN unit (e.g., VLAN Unit_2, which is illustrated as associated with the channel unit_2), which creates a VLAN-tagged packet 704.
• VLAN-tagged packet 704 is then passed to the attached Ethernet device 226 with instructions that the VLAN-tagged packet 704 be encapsulated in an Ethernet frame 706 having the MAC address of the host-processor-controlled aggregation-unit-specific routing device 200 and thereafter transmits the Ethernet frame 706 via the Ethernet bus 255.
• the host-processor-controlled aggregation-unit-specific routing device 200 Upon receipt of Ethernet frame 706 containing the VLAN-tagged packet 704, the host-processor-controlled aggregation-unit-specific routing device 200 maps the source MAC address of the MAC device 226 from which Ethernet frame 706 originated to its appropriately associated IP address, and maps the VLAN-tag to its appropriately associated UDP (i.e., essentially does the inverse of the function described above in relation to Figure 3A), and hands the constructed IP packet to transmits the resultant outbound packet 708 to the packet-switched network 100. Upon receipt of such control information, the host processor's 202 counterpart (not shown) will engage in operations substantially analogous to those described in relation to Figures 6A-6B, above.
• an implementer may opt for a hardware and/or firmware vehicle; alternatively, if flexibility is paramount, the implementer may opt for a solely software implementation; or, yet again alternatively, the implementer may opt for some combination of hardware, software, and/or firmware.
• any vehicle to be utilized is a choice dependent upon the context in which the vehicle will be deployed and the specific concerns (e.g., speed, flexibility, or predictability) of the implementer, any of which may vary.
• signal bearing media include, but are not limited to, the following: recordable type media such as floppy disks, hard disk drives, CD ROMs, digital tape, and computer memory; and transmission type media such as digital and analogue communication links using TDM or IP based communication links (e.g., packet links).
• electrical circuitry includes, but is not limited to, electrical circuitry having at least one discrete electrical circuit, electrical circuitry having at least one integrated circuit, electrical circuitry having at least one application specific integrated circuit, electrical circuitry forming a general purpose computing device configured by a computer program (e.g., a general purpose computer configured by a computer program which at least partially carries out processes and/or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes and/or devices described herein), electrical circuitry forming a memory device (e.g., forms of random access memory), and electrical circuitry forming a communications device (e.g. , a modem, communications switch, or optical-electrical equipment).
• a computer program e.g., a general purpose computer configured by a computer program which at least partially carries out processes and/or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes and/or devices described herein
• electrical circuitry forming a memory device
• any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components.
• any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality.

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