EP1470477A1 - Method for processing instructions - Google Patents
Method for processing instructionsInfo
- Publication number
- EP1470477A1 EP1470477A1 EP20030706230 EP03706230A EP1470477A1 EP 1470477 A1 EP1470477 A1 EP 1470477A1 EP 20030706230 EP20030706230 EP 20030706230 EP 03706230 A EP03706230 A EP 03706230A EP 1470477 A1 EP1470477 A1 EP 1470477A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- command
- block
- program
- instruction
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000012545 processing Methods 0.000 title claims description 35
- 230000003111 delayed effect Effects 0.000 claims description 8
- 230000001960 triggered effect Effects 0.000 claims description 2
- 238000011161 development Methods 0.000 description 5
- 238000013459 approach Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 108090000623 proteins and genes Proteins 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
Definitions
- the invention relates to a method for command processing in a processor, wherein a currently executable command of a program memory is addressed by a program control unit on the one hand by means of a program counter status of a program counter implemented in it, by the program control unit controlling the counting mode and the Specifies the step size of the program counter and also stores a jump address from which it continues its counting mode when a jump command occurs, and on the other hand the addressed command is read out, decoded and executed by the program control unit.
- parallelism primarily means the operations and calculations that can be carried out in parallel in a processor and are independent of one another.
- ILP instruction level parallelism
- ILP-based systems use conventional high-level programming languages, which were created for sequential processors, on the one hand, and compiler technology and hardware, on the other hand, to automatically detect parallelism.
- ILP-based systems for programming, however, it should be noted that program branches cannot be parallelized.
- VLIW Very long instruction word
- the program contains the information about existing parallelism.
- a disadvantage of this processor technology is the fact that the predictive instruction processing of program branches, the branch prediction and the speculative code processing are not manageable.
- an EPIC program In addition to the ILP, an EPIC program also tells the processor the conditions under which certain instructions are to be executed. The processor gets all the commands execute, but only adopt results that meet the additional conditions (predicated instruction).
- This technology also has the disadvantage that the command processing of fixed blocks of commands can only be implemented by command-intensive subroutines. It is also not possible to optimally design the branch prediction of program branches where the return address is already set.
- a software method known in the prior art to process program branches in a time-saving manner is to save the jumps back and forth to the called subroutines by programming the instructions in such a way that they can be executed "inline".
- This multiple occurrence of the UP in the program harbors the disadvantage of the high memory consumption.
- the task is therefore to expand the EPIC processor technology with options for fast command processing of command blocks that go beyond the usual call of subroutines.
- the solution to the problem according to the invention provides that an additional block command is implemented in the processors on the hardware side, so that the program control unit provides for a program branch in which a certain number of commands to be processed one after the other is provided and so that the return address is fixed after command processing, this implemented block command is optionally called instead of a subroutine, in which the current program counter status and the number of commands in succession of commands are additionally stored.
- a further embodiment of the solution of the task according to the invention provides that the additional block command is executed by the arithmetic unit as a conditional command (predicated instruction), the command word containing the information under which condition the stored number of commands of the command block are processed.
- conditional command predicated instruction
- both branches are executed in a preliminary processing phase until the result of the condition query at the end of the associated delayed slot has been evaluated in an execute phase.
- the delayed slots serve as respective execution channels in the area of the program for each command being processed in this way. program control. They are only closed after the execution phase of each command.
- command processing times can be saved by the fact that an execute phase of a previous command does not necessarily have to be reached before the next command can be read out.
- the respective processing status of the interrupted first command block and the end address to be saved for the return, which results from the second block command, are stored in a local program control stack.
- the addresses of the commands combined in the respective command block are placed in the special address area that can be read by the compiler.
- the invention will be explained in more detail below on the basis of an exemplary embodiment.
- the associated drawing figure shows a schematic representation of the arithmetic unit with its processes during command processing.
- the program instructions are present in the program sequence 1 in the program memory 1.
- the program counter 5 contained in the program control unit 10 has addressed a command word of the program memory 1 and this has been recognized as a jump command by its subsequent decoding.
- the number of commands from the block command is also stored in the command number memory 6.
- the return address can thus be calculated and specified by the program control unit 10 after the command block has been processed.
- the drawing shows that the first command block 2 contains a further block command.
- the associated jump address is stored in the jump address memory 3 by this command and the second command block 11 is thereby addressed.
- the calculation is made from the number of commands in the local stack 8 to the calculated return address and the command processing in the first command block 2 can be continued until its end.
- the program control unit 10 loads the contents of the memory of the current program counter status 4, which represents the processing status of the interrupted program in the program memory 1 by the stored return address, into the program counter and the program instructions 1 to be processed are returned to. gene.
- the program in program memory 1 can thus be continued at the interrupted point.
- Calculator program memory first instruction block jump address memory memory of the current program counter status program counter instruction number memory delayed slots (Execute Phase) instruction number memory of the local stack processing status memory of the local stack program control unit second instruction block local stack of the program control
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10204345A DE10204345A1 (en) | 2002-02-01 | 2002-02-01 | Command processing procedures |
DE10204345 | 2002-02-01 | ||
PCT/DE2003/000126 WO2003065204A1 (en) | 2002-02-01 | 2003-01-17 | Method for processing instructions |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1470477A1 true EP1470477A1 (en) | 2004-10-27 |
Family
ID=27588306
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP20030706230 Withdrawn EP1470477A1 (en) | 2002-02-01 | 2003-01-17 | Method for processing instructions |
Country Status (5)
Country | Link |
---|---|
US (3) | US20050246571A1 (en) |
EP (1) | EP1470477A1 (en) |
JP (1) | JP2005516301A (en) |
DE (1) | DE10204345A1 (en) |
WO (1) | WO2003065204A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AT500858B8 (en) * | 2004-08-17 | 2007-02-15 | Martin Schoeberl | INSTRUCTION CACHE FOR REAL-TIME SYSTEMS |
DE102012218363A1 (en) * | 2012-10-09 | 2014-04-10 | Continental Automotive Gmbh | Method for controlling a separate flow of linked program blocks and control device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0374419A3 (en) * | 1988-12-21 | 1991-04-10 | International Business Machines Corporation | Method and apparatus for efficient loop constructs in hardware and microcode |
JPH07160585A (en) * | 1993-12-13 | 1995-06-23 | Hitachi Ltd | Low power data processor |
US5805863A (en) * | 1995-12-27 | 1998-09-08 | Intel Corporation | Memory pattern analysis tool for use in optimizing computer program code |
US5710913A (en) * | 1995-12-29 | 1998-01-20 | Atmel Corporation | Method and apparatus for executing nested loops in a digital signal processor |
US5898865A (en) * | 1997-06-12 | 1999-04-27 | Advanced Micro Devices, Inc. | Apparatus and method for predicting an end of loop for string instructions |
US6463582B1 (en) * | 1998-10-21 | 2002-10-08 | Fujitsu Limited | Dynamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method |
US6453407B1 (en) * | 1999-02-10 | 2002-09-17 | Infineon Technologies Ag | Configurable long instruction word architecture and instruction set |
-
2002
- 2002-02-01 DE DE10204345A patent/DE10204345A1/en not_active Ceased
-
2003
- 2003-01-17 WO PCT/DE2003/000126 patent/WO2003065204A1/en active Application Filing
- 2003-01-17 US US10/502,991 patent/US20050246571A1/en not_active Abandoned
- 2003-01-17 EP EP20030706230 patent/EP1470477A1/en not_active Withdrawn
- 2003-01-17 JP JP2003564729A patent/JP2005516301A/en active Pending
-
2008
- 2008-10-22 US US12/256,236 patent/US20090070557A1/en not_active Abandoned
-
2009
- 2009-11-04 US US12/612,463 patent/US20100049949A1/en not_active Abandoned
Non-Patent Citations (1)
Title |
---|
See references of WO03065204A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO2003065204A1 (en) | 2003-08-07 |
JP2005516301A (en) | 2005-06-02 |
US20050246571A1 (en) | 2005-11-03 |
US20100049949A1 (en) | 2010-02-25 |
US20090070557A1 (en) | 2009-03-12 |
DE10204345A1 (en) | 2003-08-14 |
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Legal Events
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
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17P | Request for examination filed |
Effective date: 20040722 |
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AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT SE SI SK TR |
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AX | Request for extension of the european patent |
Extension state: AL LT LV MK RO |
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17Q | First examination report despatched |
Effective date: 20070530 |
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RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: NXP SEMICONDUCTORS GERMANY GMBH |
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RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: NXP B.V. |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
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18D | Application deemed to be withdrawn |
Effective date: 20100803 |