EP1458087B1 - Electrical circuit, apparatus and method for the demodulation of an intensity-modulated signal - Google Patents
Electrical circuit, apparatus and method for the demodulation of an intensity-modulated signal Download PDFInfo
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- EP1458087B1 EP1458087B1 EP03405164A EP03405164A EP1458087B1 EP 1458087 B1 EP1458087 B1 EP 1458087B1 EP 03405164 A EP03405164 A EP 03405164A EP 03405164 A EP03405164 A EP 03405164A EP 1458087 B1 EP1458087 B1 EP 1458087B1
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- 238000000034 method Methods 0.000 title claims description 20
- 238000005070 sampling Methods 0.000 claims abstract description 23
- 230000002123 temporal effect Effects 0.000 claims abstract description 8
- 230000002463 transducing effect Effects 0.000 claims abstract description 5
- 238000001514 detection method Methods 0.000 claims description 19
- 230000026683 transduction Effects 0.000 claims description 18
- 238000010361 transduction Methods 0.000 claims description 18
- 238000007781 pre-processing Methods 0.000 claims description 9
- 238000011156 evaluation Methods 0.000 claims description 8
- 102100036464 Activated RNA polymerase II transcriptional coactivator p15 Human genes 0.000 abstract description 10
- 101100204393 Arabidopsis thaliana SUMO2 gene Proteins 0.000 abstract description 10
- 101000713904 Homo sapiens Activated RNA polymerase II transcriptional coactivator p15 Proteins 0.000 abstract description 10
- 229910004444 SUB1 Inorganic materials 0.000 abstract description 10
- 229910004438 SUB2 Inorganic materials 0.000 abstract description 10
- 101150112492 SUM-1 gene Proteins 0.000 abstract description 10
- 101150096255 SUMO1 gene Proteins 0.000 abstract description 10
- 101100311460 Schizosaccharomyces pombe (strain 972 / ATCC 24843) sum2 gene Proteins 0.000 abstract description 10
- 101100311330 Schizosaccharomyces pombe (strain 972 / ATCC 24843) uap56 gene Proteins 0.000 abstract description 10
- 101150018444 sub2 gene Proteins 0.000 abstract description 10
- 230000003287 optical effect Effects 0.000 abstract description 7
- 230000005855 radiation Effects 0.000 abstract description 6
- 238000012935 Averaging Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000003491 array Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000000691 measurement method Methods 0.000 description 3
- 238000001914 filtration Methods 0.000 description 2
- 238000005305 interferometry Methods 0.000 description 2
- 238000012014 optical coherence tomography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 238000013144 data compression Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/02—Transference of modulation from one carrier to another, e.g. frequency-changing by means of diodes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
- H03D3/06—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal by combining signals additively or in product demodulators
- H03D3/08—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal by combining signals additively or in product demodulators by means of diodes, e.g. Foster-Seeley discriminator
Definitions
- This invention generally relates to all sensing and measurement techniques that rely on temporally modulated signals, preferably optical radiation fields, whose local variation of amplitude and phase must be measured as a function of time. More particularly, it relates to all of these sensing and measurement techniques that require dense one- or two-dimensional arrays of such amplitude- and phase-sensitive demodulation pixels. These techniques include optical coherence tomography (OCT), time-of-flight (TOF) range imaging and multiple wave interferometry.
- OCT optical coherence tomography
- TOF time-of-flight
- optical sensing and measurement techniques are known that are based on temporally modulated optical radiation fields whose local amplitude and phase vary as a function of time. These techniques require the spatially and temporally resolved determination of amplitude and phase, the so-called demodulation of the modulated radiation field. While several electronic circuits and digital signal processing algorithms exist that can provide this demodulation function for a single measurement spot, none of these solutions allow the integration into dense, massively parallel and reliably operating arrays of demodulation photosensors.
- a standard AM-demodulation consists of band-pass filtering, rectifying, and low-pass filtering the input signal. This technique is widely known for AM radio receivers. Its disadvantage is the need for large RC-constants for frequencies below 10 kHz, which are not compatible with the small pixel size and the new CMOS processes.
- Direct detection by multiplying the input signal on one path with an oscillator signal matching the carrier frequency and on a second path with the oscillator's 90-degrees shifted signal allows detection of amplitude and phase.
- signal multiplication is complex and power consuming compared to the power available in each pixel (typically a few ⁇ W) and therefore not suited for massive parallel integration in a pixel field.
- the circuits should be integrable in dense one- or two-dimensional arrays due to their compact size, low electric power consumption, simplicity of driving, independent signal pre-processing capabilities and robustness of operation regarding fabrication tolerances of semiconductor processes.
- the invention separates the envelope detection into two different tasks:
- the electrical circuit according to the invention performs the first (i) of the two above-identified tasks.
- the input signal is locally sensed and sampled at a frequency that is four times the modulation frequency of the signal.
- Subtraction/summation stages accumulate differences of two samples per modulation period, separated by half the period, during several averaging periods; the two stages are time shifted with respect to each other by a defined or predetermined fraction of the modulation period, preferably a quarter period.
- the resulting two output signals are employed for the determination of the local envelope amplitude and the temporal phase in the second task (ii), representing a mean over the averaging periods.
- the inventive electrical circuit for the detection of a signal modulated with a modulation frequency, a modulation period being defined as the inverse of the modulation frequency comprises transduction means for transducing the modulated signal into an electrical signal, sampling means for sampling said electrical signal with a sampling frequency which is equal to four times the modulation frequency or a multiple thereof, first subtraction means for evaluating a first difference between two first samples separated by half the modulation period, and second subtraction means for evaluating a second difference between two second samples separated by half the modulation period, said second samples being time-shifted with respect to said first samples by a defined or predetermined fraction of the modulation period, preferably a quarter period.
- the electrical circuit further comprises first summation means for evaluating a first sum of a plurality of subsequent first differences evaluated by said first subtraction means, and second summation means for evaluating a second sum of a plurality of subsequent second differences evaluated by said second subtraction means.
- the one-dimensional or two-dimensional array sensor according to the invention comprises a plurality of pixels, at least one, and preferably each, of which comprises an electrical circuit according to the invention.
- the inventive apparatus for the demodulation of a modulated signal comprises detection means for detecting the modulated signal, and evaluation means for evaluating an envelope amplitude and/or a temporal phase from an output of said detection means.
- Said detection means comprise an electrical circuit according to the invention.
- the method for the detection of a signal modulated with a modulation frequency, a modulation period being defined as the inverse of the modulation frequency comprises the steps of transducing the modulated signal into an electrical signal, sampling said electrical signal with a sampling frequency which is equal to four times the modulation frequency or a multiple thereof, evaluating a first difference between two first samples separated by half the modulation period, and evaluating a second difference between two second samples separated by half the modulation period, said second samples being time-shifted with respect to said first samples by a defined or predetermined fraction of the modulation period, preferably a quarter period.
- a first sum of a plurality of subsequent first differences is evaluated, and a second sum of a plurality of subsequent second differences is evaluated.
- phase shift between the sampled signals is exactly a quarter of the modulation period.
- Numerical methods are known to treat non-uniform sampling grids to extract the mathematically correct values for amplitude and phase of the modulation (cf. A. B. Cain, and J. H. Ferziger and W. C. Reynolds, "Discrete orthogonal function expansion for non-uniform grids using the fast Fourier transform", J. computational physics 56, pp. 272-286, 1984).
- the electrical circuit according to the invention can be used for any input signals such as electromagnetic, ultrasonic or chemical signals.
- input signals such as electromagnetic, ultrasonic or chemical signals.
- the invention is discussed for the example of an optical signal.
- Figure 1 shows a block diagram of an electrical circuit 1 or a demodulation pixel according to the invention.
- the electrical circuit 1 comprises a transduction stage T, a sampling or sample and hold stage S, two subtraction stages SUB1 and SUB2, two summation stages SUM1 and SUM2, a signal preprocessing stage PP and a readout stage RO.
- the signal path is split into two channels 21, 22: a first channel 21 includes the first subtraction stage SUB1 and behind it the first summation stage SUM1, and a second channel 22 includes the second subtraction stage SUB2 and behind it the second summation stage SUM2.
- An input signal I which is preferably an optical radiation field, is sensed in the transduction stage T and transduced to an electrical signal of any kind (e.g., charge, voltage or current as described for example in U.S. Patent No. 6,469,489 by S. Bourquin and P. Seitz).
- the transduction stage T may have an approximate or exact offset compensation, non-linear signal compression or both of these. Offset compensation and signal compression increase the dynamic range of the detection system, since the input signal may have a large DC offset, which carries no useful information for the demodulation process.
- switch is a single field-effect transistor (FET) for voltage or current signals or a charge-coupled-device (CCD) gate for charge signals.
- FET field-effect transistor
- CCD charge-coupled-device
- a drift field demodulation pixel cf. patent application No. GB-0214257.8 or a pixel using the lock-in principle (cf. WO-96/15626) can replace the transduction stage T and the sampling stage S.
- the subtraction stages SUB1, SUB2 determine the difference between two samples separated by half the modulation period.
- the two subtraction stages SUB1, SUB2 are time-shifted with respect to each other by a quarter period.
- Each subtraction stage SUB1 and SUB2 is followed by its corresponding summation stage SUM1 and SUM2, respectively.
- the summation stages SUM1, SUM2 might have a non-linear signal compression to increase the dynamic of the detection system.
- the pre-processing stage PP allows integration of certain additional functionalities such as calculation of the ratio of the two summation signals or the sum of their squares, etc.
- a second sample and hold stage might be included if necessary.
- the pre-processing stage PP might also be a pass-through.
- the readout stage RO serves to read out the signals from the pre-processing stage PP. It may support parallel or sequential data transmission.
- a third sample and hold stage can be included to make the readout timing independent of the synchronous functioning of the subtraction and summation stages SUB, SUM.
- the readout stage is preferably laid out for random addressing.
- All stages are synchronized on the modulation frequency f or a multiple or a fraction of it.
- circuits for the pixel stages T, S, SUB, SUM, PP, RO are discussed.
- FIG. 2 shows an embodiment of the transduction stage T that converts photons I to a corresponding voltage.
- the circuit is fed by a ground voltage VSS and a supply voltage VDDA.
- a photodiode PD is the photons-sensing element and has an internal capacitance Cpd. Absorbed photons create a negative electronic charge on the positively precharged capacitance, resulting in a voltage drop.
- the resulting voltage is amplified by a source follower (unity gain, high input impedance, low output impedance) formed by two p-channel MOS transistors MP2 and MP3, where MP3 is the current source.
- the bias voltage at the gate of MP3 vbias defines the current used by the source follower.
- An output line of the transduction stage T is designated by T_out.
- the photodiode PD is reset after a certain time to a fixed voltage vreset by the n-channel MOS transistor MN1 in order to subtract the DC offset.
- the photodiode reset signal rspd controls transistor MN1.
- the transduction stage T can be enhanced by a storage node SN, which allows to reduce the bandwidth of the source follower as well as of the following circuitry and thus reduces the noise in the system.
- This modified embodiment of the transduction stage T is illustrated in Figure 3 .
- the n-channel MOS transistors Mstore and Mrsstore function as switches controlled by their gate voltages store and rsstore, respectively.
- the switch Mstore Before resetting the photodiode PD, the switch Mstore is closed and opened again to sample the voltage on the photodiode PD onto the capacitor Cstore.
- the voltage stored on Cstore is amplified by the source follower MP2, MP3.
- the switch Mrsstore closes and opens again, thus resetting the voltage on Cstore to the voltage vreset.
- a current source MP5 which introduces a current equivalent to the photogenerated DC current through the photodiode PD, is connected in series with the photodiode PD.
- Figure 4 shows a possible implementation. Two operation modes are possible:
- the modes are selected by choosing the correct gate voltage rsoc of MP4.
- the transistor MP6 is an additional switch, which allows to switch off this improved offset compensation.
- the voltage ocswi controls the switch MP6.
- the sampling stage S can be built of simple switches, e.g., NMOS switches or transmission gates as shown in Figures 5(a), 5(b) and 5(c), or it can contain a storage node. Additional storage nodes allow sample and hold operation.
- the transduction stage T and the sample and hold stage S may be combined into one device, e.g., a drift field modulation pixel as shown in Figure 6 or a lock-in pixel as shown in Figure 7.
- a drift field modulation pixel as shown in Figure 6
- a lock-in pixel as shown in Figure 7.
- FIG 8 shows an implementation of one of the subtraction stages SUB1 or SUB2 and its allocated summation stage SUM1 or SUM2, respectively.
- Phase1 and phase2 are non-overlapping opposite phase clocks.
- a charge proportional to the voltage difference between the first sample of the sampled signal and a reference voltage vref is stored on a capacitor Csub.
- a charge proportional to the voltage difference between the next sample of the sampled signal and the voltage at the negative input of an operational transconductance amplifier OTA, which approximates vref, is stored.
- the charge difference on the capacitor Csub between phase1 and phase2 is added to the charge on a capacitor Cint. This process is repeated a certain number of times.
- the output signal of this stage is therefore proportional to the sum of the voltage differences.
- Figure 9 shows an embodiment of a readout stage RO for one signal RO_in with a storage node.
- the signal RO_in is sampled through a switch Mstore into a readout storage node RSN.
- the capacitance of the readout storage node RSN is increased by a moscap MC to reduce the noise.
- a read switch Mrd When a read switch Mrd is closed, the signal is driven off-pixel by a source follower built of the MOS transistors Mfollow and Mcs.
- a plurality of electrical circuits 1.11, 1.12, ..., 1.1m; ... 1.nm as shown in Fig. 1 can be stacked in a one- or two-dimensional array, as shown in Figure 10 .
- Each of the circuits 1.11-1.nm consists of a photodiode and electronic circuitry C comprising the stages S, SUB, SUM, PP and RO described with reference to Fig. 1.
- the circuits 1.11-1.nm form the pixels of an array sensor, which itself is part of an apparatus 10 for the demodulation of a modulated signal according to the invention.
- the apparatus 10 comprises a column address decoder CAD and a row address decoder RAD for selecting one circuit after the other by indicating the corresponding column address CA and row address RA.
- the address decoders CAD, RAD are used to read out the outputs of each circuit 1.11-1.nm serially. Their electrical schematic is known art and is therefore not described here.
- the column address decoder CAD can be followed by evaluation means EV for on-chip evaluating of an envelope amplitude and/or a temporal phase from outputs of the electrical circuits.
- evaluation means EV are well-known.
- the evaluation means EV might be omitted if the envelope amplitude and temporal phase evaluation is done off-chip.
- an output amplifier OA yields an apparatus output signal on an output line OL.
- circuits 1.11-1.nm may be arranged in a different way than in rows and columns as shown in Fig. 10. Any kind of arrangement falls within the scope of the invention.
Abstract
Description
- A widely used method applies a discrete Fourier transform, removes negative and zero frequency components and re-centers the spectrum before reverse transforming. This method is described in S. S. C. Chim and G. S. Kino, "Correlation microscope," Opt. Lett. 15, pp. 579-581, 1990.
- If the input signal is sampled at a frequency that is four times the input signal modulation frequency, different algorithms for local envelope detection are known. An evaluation can be found in K. G. Larkin, "Efficient nonlinear algorithm for envelope detection in white light interferometry," J. Opt. Soc. Am. 13, pp. 832-843, 1996. But all of them imply multiplication and are therefore not applicable in a power efficient pixel structure.
- US-A-4 547 737 shows a demodulation method which samples an incoming signal at four times its modulation frequency, calculates differences between samples separated by half the modulation period, and processes the difference signals obtained to demodulate the signal fully.
- Figure 1
- shows a block diagram of the demodulation pixel according to the invention.
- Figure 2
- shows a circuit diagram of a transduction stage that converts photons into a corresponding voltage in the demodulation pixel according to the invention.
- Figure 3
- shows a variation of the transduction stage shown in Fig. 2 wherein a storage node has been added.
- Figure 4
- shows a circuit diagram of a transduction stage with improved offset compensation in the demodulation pixel according to the invention.
- Figures 5(a)-(c)
- show three types of sampling stages in the demodulation pixel according to the invention: (a) switches, (b) NMOS switches, (c) transmission gates.
- Figure 6
- shows a cross-section of a drift field modulation pixel according to the invention.
- Figure 7
- shows a cross-section of a lock-in pixel according to the invention.
- Figure 8
- shows a circuit diagram of a circuit containing a subtraction stage and a summation stage.
- Figure 9
- shows a circuit diagram of a readout stage in the demodulation pixel according to the invention.
- Figure 10
- schematically shows a two-dimensional array sensor according to the invention.
- Calibrated current compensation: A transistor MP4 is used as a switch. A current source MP5 behaves like a forward biased diode when the switch MP4 is closed, and the compensation current matches exactly the photogenerated current. When the switch MP4 opens again, the current through MP5 becomes independent of the photocurrent variations.
- Low-pass filtered current compensation: The transistor MP4 is used as a resistance, forming a low-pass filter with the gate capacitance of transistor MP5. An additional capacitor might be needed to adapt the cut-off frequency of this filter. The current source MP5 generates a compensation current, which is independent of photocurrent variations of frequencies higher than the cut-off frequency of the filter.
- 1
- Electrical circuit
- 10
- Apparatus
- 21
- First channel
- 22
- Second channel
- CA
- Column address
- CAD
- Column address decoder
- EV
- Evaluation means
- I
- Input signal
- OA
- Output amplifier
- OL
- Output line
- OTA
- Operational transconductance amplifier
- PD
- Photodiode
- PP
- Pre-processing stage
- RA
- Row address
- RAD
- Row address decoder
- RO
- Readout stage
- RSN
- Readout storage node
- S
- Sampling stage
- SN
- Storage node
- SUB1, SUB2
- Subtraction stages
- SUM1, SUM2
- Summation stages
- T
- Transduction stage
- VDDA
- Supply voltage
- VSS
- Ground voltage
Claims (13)
- An electrical circuit (1) for the detection of a signal (I) modulated with a modulation frequency, a modulation period being defined as the inverse of the modulation frequency, comprising:transduction means (T) for transducing the modulated signal (I) into an electrical signal,sampling means (S) for sampling said electrical signal with a sampling frequency which is equal to four times the modulation frequency or a multiple thereof,first subtraction means (SUB1) for evaluating a first difference between two first samples separated by half the modulation period, andsecond subtraction means (SUB2) for evaluating a second difference between two second samples separated by half the modulation period, said second samples being time-shifted with respect to said first samples by a defined fraction, preferably a quarter, of the modulation period,
first summation means (SUM1) for evaluating a first sum of a plurality of subsequent first differences evaluated by said first subtraction means (SUB1), and
second summation means (SUM2) for evaluating a second sum of a plurality of subsequent second differences evaluated by said second subtraction means (SUB2). - The electrical circuit (1) according to claim 1, wherein said transduction means (T) comprise a photodiode (PD) and preferably a source follower (MP2, MP3) for amplifying an electrical output signal of said photodiode (PD).
- The electrical circuit (1) according to claim 2, wherein a storage node (SN) is arranged between said photodiode (PD) and said source follower (MP2, MP3).
- The electrical circuit (1) according to claim 2 or 3, wherein a current source (MP5) for introducing a current equivalent to a photogenerated DC current through said photodiode (PD) is connected in series with said photodiode (PD).
- The electrical circuit (1) according to any of the preceding claims, wherein said sampling means (S) comprise at least two switches and/or a storage node.
- The electrical circuit (1) according to claim 1, wherein said transduction means (T) and said sampling means (S) are combined into one element, e.g., a drift field modulation pixel or a lock-in pixel.
- The electrical circuit (1) according to any of the preceding claims, further comprising pre-processing means (PP) for pre-processing said first and second sum evaluated by said first and second summation means (SUM1, SUM2), respectively, e.g., for calculating a sum of the squares of said first and second sums or for calculating a ratio of said first and second sums.
- The electrical circuit (1) according to any of the preceding claims, further comprising readout means (RO) for reading out an output signal of said electrical circuit (1).
- A one-dimensional or two-dimensional array sensor comprising a plurality of pixels (1.11-1.nm),
characterized in that
at least one, and preferably each, of said pixels (1.11-1.nm) comprises an electrical circuit according to any of the preceding claims. - An apparatus (10) for the demodulation of a modulated signal (I), comprising:detection means for detecting the modulated signal (I), andevaluation means (EV) for evaluating an envelope amplitude and/or a temporal phase from an output of said detection means,
said detection means comprise an electrical circuit (1.11-1.nm) according to any of the claims 1-8. - The apparatus (10) according to claim 10, wherein said detection means comprise a plurality of pixels (1.11-1.nm) with parallel outputs, at least one, and preferably each, of said pixels (1.11-1.nm) comprising an electrical circuit according to any of the claims 1-8, and wherein said apparatus (10) further comprises at least one on-chip address decoder (CAD. RAD) for individually reading out each electrical circuit (1.11-1.nm).
- A method for the detection of a signal (I) modulated with a modulation frequency, a modulation period being defined as the inverse of the modulation frequency, comprising the steps of:transducing the modulated signal (I) into an electrical signal,sampling said electrical signal with a sampling frequency which is equal to four times the modulation frequency or a multiple thereof,evaluating a first difference between two first samples separated by half the modulation period, andevaluating a second difference between two second samples separated by half the modulation period, said second samples being time-shifted with respect to said first samples by a defined fraction, preferably a quarter, of the modulation period,
a first sum of a plurality of subsequent first differences is evaluated, and
a second sum of a plurality of subsequent second differences is evaluated. - The method according to claim 12, wherein said first and second sum are pre-processed prior to being used for evaluating an envelope amplitude and/or a temporal phase of the modulated signal (I), e.g., a sum of the squares of said first and second sums or a ratio of said first and second sums is calculated.
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03405164A EP1458087B1 (en) | 2003-03-10 | 2003-03-10 | Electrical circuit, apparatus and method for the demodulation of an intensity-modulated signal |
DE60301852T DE60301852T2 (en) | 2003-03-10 | 2003-03-10 | Electric circuit, method and apparatus for demodulation of an intensity modulated signal |
AT03405164T ATE306745T1 (en) | 2003-03-10 | 2003-03-10 | ELECTRICAL CIRCUIT, METHOD AND DEVICE FOR DEMODULATION OF AN INTENSITY MODULATED SIGNAL |
US10/548,753 US7595476B2 (en) | 2003-03-10 | 2004-03-03 | Electrical circuit, apparatus and method for the demodulation of an intensity-modulated signal |
CNB200480006478XA CN100477490C (en) | 2003-03-10 | 2004-03-03 | Electrical circuit, apparatus and method for the demodulation of an intensity-modulated signal |
PCT/CH2004/000122 WO2004082131A1 (en) | 2003-03-10 | 2004-03-03 | Electrical circuit, apparatus and method for the demodulation of an intensity-modulated signal |
KR1020057016807A KR101033952B1 (en) | 2003-03-10 | 2004-03-03 | Electrical circuit, apparatus and method for the demodulation of an intensity-modulated signal |
JP2006504150A JP4579232B2 (en) | 2003-03-10 | 2004-03-03 | Electrical circuit, apparatus and method for demodulation of intensity modulated signals |
Applications Claiming Priority (1)
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EP03405164A EP1458087B1 (en) | 2003-03-10 | 2003-03-10 | Electrical circuit, apparatus and method for the demodulation of an intensity-modulated signal |
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EP1458087A1 EP1458087A1 (en) | 2004-09-15 |
EP1458087B1 true EP1458087B1 (en) | 2005-10-12 |
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US (1) | US7595476B2 (en) |
EP (1) | EP1458087B1 (en) |
JP (1) | JP4579232B2 (en) |
KR (1) | KR101033952B1 (en) |
CN (1) | CN100477490C (en) |
AT (1) | ATE306745T1 (en) |
DE (1) | DE60301852T2 (en) |
WO (1) | WO2004082131A1 (en) |
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2003
- 2003-03-10 EP EP03405164A patent/EP1458087B1/en not_active Expired - Lifetime
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US10016137B1 (en) | 2017-11-22 | 2018-07-10 | Hi Llc | System and method for simultaneously detecting phase modulated optical signals |
US10299682B1 (en) | 2017-11-22 | 2019-05-28 | Hi Llc | Pulsed ultrasound modulated optical tomography with increased optical/ultrasound pulse ratio |
US10219700B1 (en) | 2017-12-15 | 2019-03-05 | Hi Llc | Systems and methods for quasi-ballistic photon optical coherence tomography in diffusive scattering media using a lock-in camera detector |
Also Published As
Publication number | Publication date |
---|---|
EP1458087A1 (en) | 2004-09-15 |
CN100477490C (en) | 2009-04-08 |
JP2006524800A (en) | 2006-11-02 |
KR101033952B1 (en) | 2011-05-11 |
DE60301852D1 (en) | 2005-11-17 |
ATE306745T1 (en) | 2005-10-15 |
JP4579232B2 (en) | 2010-11-10 |
US20060097781A1 (en) | 2006-05-11 |
US7595476B2 (en) | 2009-09-29 |
DE60301852T2 (en) | 2006-05-18 |
KR20060006778A (en) | 2006-01-19 |
WO2004082131A1 (en) | 2004-09-23 |
CN1759530A (en) | 2006-04-12 |
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