EP1456950A2

EP1456950A2 - Integrated circuit comprising a clock generator, a chip card comprising one such integrated circuit and the associated clock generation method

Info

Publication number: EP1456950A2
Application number: EP02796907A
Authority: EP
Inventors: Christophe Moreaux; Ahmed Résidence le Musset Bâtiment 6 KARI; Olivier Tardieu
Original assignee: STMicroelectronics SA
Current assignee: STMicroelectronics SA
Priority date: 2001-12-13
Filing date: 2002-12-11
Publication date: 2004-09-15
Also published as: WO2003050955A2; FR2833781B1; US20050133603A1; WO2003050955A3; FR2833781A1; US7400874B2

Abstract

The invention relates to a contactless integrated circuit which receives a radio frequency signal. According to the invention, the circuit comprises a clock generator, said generator being used to produce a clock signal (CLK) from a first alternation (AC0) and a second alternation (AC1) which are representative of the radio frequency signal received. The invention also relates to a method of generating a clock signal, during which the first and the second alternations are compared in order to produce the clock signal. The invention is suitable for contactless cards, transponders, etc.

Description

Integrated circuit comprising a clock generator. smart card comprising such an integrated circuit and associated clock generation method.

The invention relates to an integrated circuit comprising a clock generator and an associated clock generation method. The invention is particularly interesting for integrated circuits used in contactless applications, such as smart cards, transponders, etc.

In contactless circuits, the data and the energy received by the chip are transmitted by a reader (or transmitter) in the form of an amplitude modulated radiofrequency signal; we usually speak of modulation to speak of communication from the reader to the contactless circuit. In addition, a contactless circuit can transmit digital data to the reader, in this case we speak of retromodulation.

An integrated circuit known for contactless application notably comprises (FIG. 1) an antenna 11, a rectifier bridge 12, a voltage regulator 13, a logic circuit 14, a clock generator 15 and a modulation and demodulation circuit 16.

The radiofrequency signal is received by the antenna 11 which produces two ACO signals (represented in FIG. 2), ACl having the form of two positive half-vibrations, the radiofrequency signal being approximately equal to the result of the subtraction of the signal ACl from the signal ACO.

The rectifier bridge 12 is a bridge with four diodes, it comprises two inputs connected to two inputs outputs of the antenna 11 to receive the two signals ACO, ACl, and an output on which a rectified voltage HVR is produced. The voltage HVR is approximately the sum of the two signals ACO, ACl; 1 average amplitude of the rectified voltage varies directly depending on the distance between the reader and the contactless integrated circuit. The average amplitude of the rectified voltage can thus vary between approximately 2 V when the circuit is a few tens of centimeters from the reader and approximately 15-20 V when the circuit is a few millimeters from the reader. In practice, the HVR voltage is most often limited to around 8 V by an appropriate device. The voltage regulator 13 receives the rectified voltage HVR and produces a supply voltage VDD having a nominal value VDDO of the order of 3 V (for 0.6 μm technology), stable and continuous, which will be used subsequently. for powering all components of the integrated circuit. The regulator 13 comprises inter alia a filter comprising in particular a set of resistors and associated capacitors according to known diagrams.

The voltage VDD varies as follows. At the start of reception of the radiofrequency signal emitted by the reader, during a transient phase, the voltage VDD varies rapidly between a zero value and a nominal value VDDO. The voltage VDD then keeps its nominal value VDDO until the interruption of the reception of the radio frequency signal, either because the reader stops transmitting, or because the contactless circuit becomes too far from the reader, making detection impossible antenna level. In other words, after the transient phase, the voltage VDD retains its nominal value only if the energy received by the circuit via the radiofrequency signal is sufficient.

The modulation and demodulation circuit 16 can extract digital data contained in the received radio frequency signal from the rectified voltage HVR, digital data which will be used by other integrated circuit components. The circuit 16 can also, for the retromodulation (communication from the contactless circuit to the reader), modulate on the radiofrequency signal received from the data to be transmitted to the reader, the radiofrequency signal modulated by the circuit 16 then being retransmitted via the antenna 11.

The clock generator 15 produces a clock signal CLK from the alternation ACO. The clock signal CLK is then used to clock the operation of all the components of the integrated circuit.

Finally, the logic circuit 14 receives the supply voltage VDD and produces different control signals when the supply voltage VDD reaches a minimum value close to its nominal value VDDO. The control signals are, for example, the signals POR, CLKDIS, used to trigger the operation of the circuit 16 and of the clock generator 15.

The clock generator 15 is conventionally produced using a set of logic gates. According to one embodiment, the clock generator comprises a NOR type logic gate with two inputs on which the ACO signal and the CLKDIS control signal are applied respectively, and an output on which the clock signal is produced CLK.

The CLK signal varies in normal operation according to the time diagram in FIG. 2. When the CLKDIS signal is active, here equal to "0", the CLK signal is equal to "0" if the ACO signal is greater than a threshold voltage VTRIG, and the CLK signal is equal to "1" if the ACO signal is less than the threshold voltage VTRIG. When the CLKDIS signal is inactive (in practice for a few microseconds after the start of reception of the radio frequency signal), the CLK signal is zero. The threshold voltage VTRIG corresponds to a switching threshold voltage of the logic inverters used for the realization of the NOR door. The voltage VTRIG depends in particular on the threshold voltage of the transistors constituting the inverters and especially on the voltage VDD supplying them. As can be clearly seen in FIG. 2, the signal CLK obtained has a duty cycle different from V2, which can cause operating difficulties for certain components of the contactless circuit.

Another drawback of known clock generators is that they are liable to not function correctly if the supply voltage VDD changes in significant proportions. This is for example the case at the start of a retromodulation.

In fact, to transmit data to the reader, the circuit 16 modulates the radio frequency signal with the data to be transmitted, the modulated signal then being retransmitted towards the reader by the intermediary of the antenna 11, as we have seen previously .

In practice, the modulation of the radiofrequency signal is carried out by varying the load seen by the antenna 11. This can be carried out by varying the load at the output of the rectifier bridge 12, or even by pulling one and / or the other of the ACO, ACl potentials to ground.

This results in a significant and immediate drop in the amplitude of the signals ACO, ACl as soon as the retromodulation starts (instant TO on the time diagram of FIG. 3). The decrease in the amplitude of the ACO signal will cause a decrease in the VDD voltage. The variations of the voltage VDD are however much slower than those of the amplitude of the signal ACO; this is mainly due to the presence of filters in the voltage regulator 13. The voltage VDD will thus decrease slowly for a few periods of the signal ACO, until reaching a new value VDDl much lower than VDDO, value VDDl which it will keep then for the duration of the retromodulation. In the example of FIG. 3, three periods are necessary for the voltage VDD to reach its stable value VDDl. In practice, ten periods may be necessary. The voltage VTRIG, which depends directly on the voltage VDD and which conditions the generation of the clock signal CLK, will follow the variations of the voltage VDD (see FIG. 3). At the instant Tl, the voltage VTRIG is still much higher than the amplitude of the signal ACO, so that the logic gates of the clock generator do not switch: the signal CLK does not vary at the instant Tl whereas it should have varied. The same phenomenon is reproduced at time T2 in FIG. 3, insofar as the voltage VTRIG is still too high compared to the value of ACO. It is necessary to wait for the time of a few periods of the alternating ACO to see a pulse appear on the signal CLK (instant T3 in the example in FIG. 3).

Thus, during the start of the back modulation, the known clock generators do not function correctly, due to the difference in behavior between the supply voltage VDD and the amplitude of the alternation ACO.

This malfunction can have significant consequences; it can in particular cause errors in reception by the reader of the signal retransmitted by the contactless circuit.

An object of the invention is to produce a new clock generator which does not exhibit such malfunctions during large and rapid variations in the amplitude of the two half-waves ACO, ACl on the antenna, for example at the start of a retromodulation. Another object of the invention is to provide a new clock generator which produces signals perfectly regular clock cycles, with a duty cycle equal to 1/2.

With these objectives in view, the invention relates to a contactless integrated circuit receiving a radio frequency signal, the circuit being characterized in that it comprises a clock generator for producing a clock signal from a first half-wave and a second half-wave representative of the received radio frequency signal.

Thus, according to the invention, the clock signal is obtained from the two half-waves ACO, ACl, and no longer from only one. In this way the clock signal obtained is no longer dependent on the amplitude of one or the other of the half-waves, because the amplitude of a half-wave is no longer compared with a predefined threshold, unlike this. which is done in known clock generators.

According to a preferred embodiment of the invention, the clock signal is obtained by comparison of the first half-wave with the second half-wave.

Thus, two signals varying in time in a similar manner are compared (amplitude and duration of the similar variations) so that the comparison is not likely to be vitiated by error because of a different variation of the compared signals.

Furthermore, the clock signal obtained is perfectly symmetrical and has a duty cycle equal to%, by the very form of the two half-waves, as will be seen more clearly below.

Preferably, the clock signal is produced after the supply voltage VDD of the integrated circuit has become available, that is to say after the supply voltage VDD has reached its nominal, continuous and regulated value. It is thus possible to supply the clock signal obtained and the supply voltage simultaneously to any other component

(memory, logic circuits, etc.) of the integrated circuit using both the clock signal and the supply voltage, this avoids any possible malfunction of such a component.

According to a practical embodiment, the clock generator according to the invention comprises a comparator of analog signals. The invention finally relates to a smart card, comprising an integrated circuit with a clock generator such as that described above.

The invention and the advantages which result therefrom will appear more clearly on reading the following description of exemplary embodiments of a clock generator according to the invention. The description should be read with reference to the accompanying drawings in which: - Figure 1, already described, is a block diagram of an integrated circuit for contactless applications, Figures 2, 3, already described, are time diagrams showing l evolution of signals at different points in the circuit of FIG. 1, FIG. 4 is a block diagram of a clock generator according to the invention,

- Figure 5 is a time diagram showing the evolution of signals at different points of the circuit of Figure 4, and - Figure 6 is an electronic diagram of a possible embodiment of the circuit of Figure 5.

A generator according to the invention is a comparator which comprises (FIG. 4) two data inputs to which the signals ACO, ACl produced on the antenna of a contactless integrated circuit are applied and corresponding to the two half-waves of the radiofrequency signal emitted by a reader.

The generator produces the clock signal CLK by comparing the signals ACO, ACl. If the ACO signal is greater than the ACl signal (Figure 5), which in practice, by the very form of the ACO, ACl signals, means that the ACO signal is positive and that the ACl signal is zero, then the signal clock is active (equal to "1" in

1 example). Conversely, if the ACO signal is less than the ACl signal, in other words, if the ACO signal is zero and the ACl signal is positive, then the CLK signal is inactive (equal to "0" in the example).

The signal CLK obtained is perfectly symmetrical by the very form of the alternations ACO, ACl because:

ACO, ACl are from the same period and they are similar: they are both zero in one half period and positive in the other,

- ACO, ACl are shifted in time by half a period.

The electronic diagram of FIG. 6 details a particular embodiment of the comparator of FIG. 4, comprising four transistors T61, T63, T65, T66 of type P, four transistors T62, T64, T67, T68 of type N and an inverter I .

The transistors T61, T65 and T62 are connected in series: a supply voltage VDD is applied to the source of T61, the source of T65 is connected to the drain of T61, the drain of T62 is connected to the drain of T65 and the source of T62 is connected to a circuit ground.

The drain of T62 is also connected to an input of the inverter I, which produces the CLK signal.

The transistors T63, T66, T64 are also connected in series: the voltage VDD is applied to the source of T63, the source of T66 is connected to the drain of T63, the drain of T64 is connected to the drain of T66 and the source of T64 is connected to the circuit earth.

The gate of transistor T61 is connected to the drain of T64 and the gate of T63 is connected to the drain of T62. Finally, the validation signal CLKDIS is applied to the gates of the transistors T65, T66 connected together.

The CLKDIS signal is obtained as in known contactless circuits. The CLKDIS signal is activated (in the example at "0") when the supply voltage VDD reaches a minimum value sufficient to ensure correct operation of the integrated circuit and more precisely correct operation of the clock generator in the present case .

The operation of the generator will now be described in an example where it is assumed that initially, the signal CLKDIS is active, the signal AC1 is equal to 0 and the signal ACO is positive. The transistors T62, T63, T65, T66 are therefore conducting, the transistors T61, T64 are blocked and the signal CLK is equal to "1" (instant TO, FIG. 5).

At time T1, the signal ACl goes to zero and the signal ACO increases and becomes positive.

When the signal AC1 goes to zero, the transistor T64 is blocked. As the transistor T63 is still on, the charges conveyed by the current flowing through it accumulate on the drain of the transistor T64: the potential on the gate of the transistor T61 increases accordingly and the transistor T61 is gradually blocked.

In parallel, when the ACO signal increases and becomes positive, the transistor T62 becomes conducting, the current which crosses it leads to ground the electric charges present on its drain: the potential on the drain of the transistor T62 and on the gate of the transistor T63 consequently decreases and the transistor T63 gradually turns on. Furthermore, when the potential on the drain of transistor T62 reaches the threshold value of the inverter I, the latter switches and the signal CLK becomes equal to "1".

A new equilibrium is established when the potential on the drain of transistor T64 reaches the value VDD and the potential on the drain of transistor T62 reaches the zero value (mass of the circuit). It should be noted that, with respect to the duration of a half period of the signal ACO (or ACl), the time necessary for the switching of the inverter I is almost zero.

Variants of the diagram of FIG. 6 can of course be envisaged.

For example, the role of the inverter I is to transform the potential on the drain of T62, which varies continuously, into a logic signal CLK taking two values 0 or 1 depending on whether the potential on the drain of T62 is higher or no to a potential threshold associated with the inverter I. The inverter I can be replaced by any component capable of performing this function, such as for example a logic gate or a converter.

The transistors T65, T66 have the function of authorizing or blocking the overall operation of the comparator, as a function of the signal CLKDIS. They can be deleted. Where appropriate, the drains of the transistors T63, T64 are connected together and the drains of the transistors T61, T62 are connected together. In this case, a comparator operating continuously will be obtained: such a comparator is less advantageous in practice because on the one hand it consumes continuous energy and on the other hand, the supply of the clock signal before the voltage d A VDD power supply is not available may cause a malfunction of a component of the circuit in contact. It is also possible to add two transistors T67, T68 (shown in FIG. 6 in dotted lines), of type N here. The drain and the source of T67 are connected respectively to the drain and the source of T62, and the drain and the source of T68 are connected respectively to the drain and the source of T64. Finally, the CLKDIS signal is applied to the gate of the transistors T67, T68. The addition of these two transistors makes it possible to connect all the comparator nodes to ground when the CLKDIS signal is inactive (in the example equal to "1"). This avoids any untimely energy consumption when no clock signal is produced.

The invention is of course not limited to the embodiment of FIG. 6. In practice, any comparison circuit, making it possible to compare two signals varying in a similar manner but in significant proportions (since the amplitude of ACO, ACl can vary between 2-3 V and 15-20 V), can be used to carry out the invention.

Claims

claims

1 ^.; Contactless integrated circuit receiving a radio frequency signal, the circuit being characterized in that it comprises a clock generator for producing a clock signal (CLK) from a first half-wave (ACO) and a second half-wave (ACl) representative of the radiofrequency signal received.

2. Integrated circuit according to claim 1, characterized in that the clock signal is obtained by comparison of the first half-wave (ACO) with the second half-wave (ACl).

3. Integrated circuit according to one of claims 1 or 2, characterized in that the clock signal is produced after a supply voltage (VDD) of the integrated circuit has become available.

4. Integrated circuit according to one of the preceding claims, characterized in that the clock circuit comprises a comparator comprising: a first transistor (T61) and a second transistor (T62) connected in series, the supply voltage (VDD ) being applied to a source of the first transistor (T61) and a ground voltage (GND) being applied to the source of the second transistor (T62), the first half-wave (ACO) being applied to a gate of the second transistor (T62), the clock signal being produced on the drain of the second transistor (T62), - a third transistor (T63) and a fourth transistor (T64) connected in series, the supply voltage (VDD) being applied to a source of the third transistor (T61) and a ground voltage (GND) being applied to the source of the fourth transistor (T62), the second half-wave (ACl) being applied to a gate of the fourth transistor (T62), a gate of the first transistor (T61) being connected to the drain of the fourth transistor (T64) and a gate of the third transistor (T63) being connected to the drain of the second transistor (T62).

5. Integrated circuit according to claim 4, characterized in that it also comprises:

- a fifth transistor (T65) connected in series between the first transistor (T61) and the second transistor (T62), a source and a drain of the fifth transistor being connected respectively to a drain of the first transistor and to the drain of the second transistor (T62 ), and

- a sixth transistor (T66) connected in series between the third transistor (T63) and the fourth transistor (T64), a source and a drain of the sixth transistor being connected respectively to a drain of the third transistor (T63) and to the drain of the fourth transistor (T64), a validation signal (CLKDIS) being applied to a gate of the fifth transistor (T65) and to a gate of the sixth transistor (T66) connected together.

6. Integrated circuit according to one of claims 4 or 5, characterized in that it also comprises:

a seventh transistor (T67) comprising a drain and a source connected respectively to the drain and to the source of the second transistor, the validation signal (CLKDIS) being applied to a gate of the seventh transistor (T67).

7. Integrated circuit according to one of claims 4 to 6, characterized in that it also comprises: - an eighth transistor (T68) comprising a drain and a source connected respectively to the drain and to the source of the fourth transistor, the validation signal

(CLKDIS) being applied to a gate of the eighth transistor (T67).

8. Method for producing a clock signal in a contactless integrated circuit, characterized in that, during the process, a first half-wave (ACO) and a second half-wave (ACl) representative of a radiofrequency signal are compared received by the integrated circuit, the clock signal (CLK) being the result of the comparison.

9. Contactless smart card, characterized in that it comprises an integrated circuit according to one of claims 1 to 7.