EP1430601A2

EP1430601A2 - Hysteresis comparator

Info

Publication number: EP1430601A2
Application number: EP02767779A
Authority: EP
Inventors: Walter Einfeldt
Original assignee: Philips Corporate Intellectual Property GmbH; Koninklijke Philips Electronics NV
Current assignee: NXP BV
Priority date: 2001-09-15
Filing date: 2002-09-13
Publication date: 2004-06-23
Also published as: DE10145656A1; JP2005503706A; WO2003026128A3; WO2003026128A2

Abstract

To provide a hysteresis comparator with a reference voltage input and a difference voltage input together with an inverting output and a non-inverting output, wherein a switching threshold of the comparator may be predetermined by an upper threshold voltage and a lower threshold voltage with regard to the reference voltage, which comparator allows flexible adaptation in simple manner to various applications, provision is made for the upper threshold voltage and the lower threshold voltage to be capable of being set independently of one another.

Description

Comparator

The invention relates to a comparator with a reference voltage input and a difference voltage input together with an inverting output and a non-inverting output, wherein a switching threshold of the comparator may be predetermined by an upper threshold voltage and a lower threshold voltage with regard to the reference voltage. Comparators of the generic type are known. These act as difference voltage transformers and are known to be used to convert analog voltage signals into digital signals. Depending on the level of an input voltage superimposed over the reference voltage, the comparator switches at the output to a HIGH voltage level or a LOW voltage level. The reference voltage determines a threshold voltage, the output state being assumed to be HIGH when this is exceeded and LOW when it is fallen short of. To increase switching accuracy of the comparator, it is known to set an upper threshold voltage and a lower threshold voltage for the reference voltage (threshold voltage). The difference between the upper threshold voltage and the lower threshold voltage provides comparator hysteresis. The upper threshold voltage and the lower threshold voltage result in the fact that switching into the HIGH state requires the upper threshold voltage to be exceeded and switching into the LOW state requires the lower threshold voltage to be fallen short of. This hysteresis determined by the upper and lower threshold voltages ensures that the interference signal superimposed over the input signals does not have any effect on the switching state of the comparator.

Comparators provided with hysteresis are known for example from US-PS 5,617,050, US-PS 5,798,663, US-PS 5,610,545, US-PS 5,528,185 and US-PS 6,166,566. Li these known comparators, in each case a constant upper threshold voltage and a constant lower threshold voltage are set, i.e. the difference between the upper threshold voltage and the reference voltage and between the reference voltage and the lower threshold voltage is identical. It is an object of the invention to provide a comparator of the generic type which provides in a simple manner flexible adaptation to various applications.

This object is achieved according to the invention by a comparator having the features of claim 1. Because the upper threshold voltage and the lower threshold voltage may be set independently of one another, it is advantageously possible to set the difference between the upper threshold voltage and the reference voltage and between the reference voltage and the lower threshold voltage to be asymmetric. In a preferred development of the invention, it is possible in particular to select the upper threshold voltage or the lower threshold voltage to be identical to the reference voltage and to design hysteresis thus only for the lower threshold voltage or for the upper threshold voltage. This opens up many and varied application options for the comparator according to the invention, especially that of triggering switchover when the reference voltage is exceeded or fallen short of, while input signal fluctuations may be suppressed either in the upper hysteresis range or the lower hysteresis range. In a further preferred development of the invention, it is also possible to set the upper and lower threshold voltages, which may be set independently of one another, in each case at the level of the reference voltage. Thus, comparators may be obtained which operate as desired with hysteresis, optionally asymmetric hysteresis, or without hysteresis. Thus, an optimal characteristic curve may be set for the comparator as a function of the application.

In a particularly preferred development of the invention, provision is made for setting of the upper threshold voltage and/or of the lower threshold voltage to be determined by modifying the channel width of p-channel transistors connected between the inverting output and the non-inverting output of the comparator. By modifying the ratio of the channel widths of the p-channel transistors relative to one another, it is possible simply to adjust the gain of the comparator and thus the hysteresis of the comparator symmetrically or asymmetrically.

It is additionally possible, in a preferred development of the invention, to adjust the channel widths of the p-channel transistors by a "metal-programmable" width or an "electrically programmable" width. In this way, the upper threshold voltage and/or the lower threshold voltage may be simply set independently of one another using methods known per se.

Further preferred developments of the invention are revealed by the other features mentioned in the subclaims.

The invention will be further described with reference to examples of embodiments shown in the drawings, to which, however, the invention is not restricted: Fig. 1 is a block diagram of a programmable comparator; Figs. 2 and 3 show possible characteristic curves for the asymmetric comparator;

Fig. 4 shows a first example of embodiment of a comparator according to the invention; Fig. 5 shows a second example of embodiment of a comparator according to the invention;

Fig. 6 shows a third example of embodiment of a comparator according to the invention.

Fig. 1 is a block diagram of a comparator 100. A reference voltage NJREF is present at an input IΝΝ. A voltage is applied to another input IΝP which results from superimposition of the reference voltage N_REF and a differential input voltage N_ TΝ. The reference voltage V_REF is constant, such that a HIGH voltage signal is obtained at an output OUTP if the differential input voltage N_IN is positive and a LOW voltage signal is obtained at the output OUTP if the differential input voltage N_ESf is negative. The respectively inverted signals are applied to the output OUTΝ. The structure and mode of operation of such comparators 100 are known, such that these will not be explained in any more detail in the context of the description. A first coupling element 12 is connected between the input IΝP and the output

OUTP and a second coupling element 14 between the input IΝΝ and the output OUTΝ. The coupling elements 12 and 14 serve, in a manner still to be explained, in programming the hysteresis of the comparator 100. The coupling element 12 serves in setting an upper threshold voltage and the coupling element 14 in setting a lower threshold voltage of the comparator 100. The difference between upper threshold voltage and lower threshold voltage corresponds to the hysteresis of the comparator 100. The upper threshold voltage may be greater than/equal to the reference voltage N_REF and the lower threshold voltage may be lower than/equal to the reference voltage NJREF.

The operation of two embodiments of the comparator 100 is clear from the characteristic curves illustrated in Figs. 2 and 3. The differential input voltage N_IΝ together with the HIGH voltage signal and LOW voltage signal present at the output OUTP are shown therein over the time t. The reference voltage NJREF together with the upper threshold voltage N_SO and the lower threshold voltage N_SU are constant over time. The difference N_SO - N_SU corresponds to the hysteresis 16. According to the characteristic curves in Fig. 2, the differential input voltage N_DST is smaller than the upper threshold voltage N_SO in the period to to t_1} such that the LOW voltage signal is present at the output OUTP. At the time t_1} the differential input voltage N_IΝ rises above the upper threshold voltage V_SO, such that the comparator 100 switches to the HIGH voltage signal at the output OUTP. At the time t₂, when the differential input voltage N_IN falls below the lower threshold voltage V_SU, the comparator switches back to the LOW voltage signal at the output OUTP. It is clear that an analog input voltage signal is converted into a digital signal. According to the illustration in Fig. 2, the hysteresis 16 is symmetric, i.e. the difference between upper threshold voltage N_SO and reference voltage N_REF matches the difference between the reference voltage N_REF and the lower threshold voltage N_SU.

In contrast thereto, in the case of the characteristic curves shown in Fig. 3, an asymmetric hysteresis 16 of the comparator 100 is programmed. The upper threshold voltage NJSO here corresponds to the reference voltage NJREF, such that the hysteresis 16 corresponds to the difference between the reference voltage N_REF or upper threshold voltage N_SO and the lower threshold voltage N_SU. The output OUTP or OUTΝ is accordingly switched into the signal states HIGH or LOW in the event respectively of the upper threshold voltage NJSO being exceeded or the lower threshold voltage N_SU being fallen short of.

These characteristic curves shown in Figs. 2 and 3 are provided for clarification merely by way of example. Thus, other asymmetric hystereses 16 of the comparator 100 may also be programmed. For example, the lower threshold voltage N_SU may coincide with the reference voltage NJREF, while the upper threshold voltage NJSO is greater than the reference voltage N_REF. Furthermore, the comparator 100 may be designed with different voltage differences between the upper threshold voltage NJSO and the reference voltage NJREF and the reference voltage NJREF and the lower threshold voltage N_SU.

The nub of the invention is to design the comparator 100 and its coupling elements 12 and 14 in such a way that the hysteresis 16 may be freely programmed, in particular asymmetrically programmed, i.e. the upper threshold voltage NJSO and the lower threshold voltage N_SU may be set independently of one another.

Fig. 4, 5 and 6 show various circuit arrangements for the comparator 100, which allow mutually independent setting of the upper threshold voltage NJSO and the lower threshold voltage N_SU. It is clear from the circuit arrangement 10 shown in Fig. 4 that it is possible to go beyond a generally known standard construction of the comparator 100 with the n-channel transistors Ml and M4 and the p-channel transistors M2 and M5 by additionally connecting p-channel transistors M3 and M6. The p-channel transistor M6 constitutes the coupling element 12 and the p-channel transistor M3 the coupling element 14 (Fig. 1).

All the p-channel transistors M2, M3, M5 and M6 have the same channel length LP and all the n-channel transistors Ml and M4 have the same channel length LN. In addition, the p-channel transistors M2 and M5 have the same channel width WP and the n- channel transistors Ml and M4 have the same channel width WN. It is clear from this that the switching behavior of the circuit arrangement 10 may be set solely by selecting the channel widths W6 of the p-channel transistor M6 or W3 of the p-channel transistor M3. The following applies to the width ratios: k3 = W3 / WP and k6 = W6 / WP. If a symmetric hysteresis 16 is initially assumed, the following applies: k3 = k6 = k.

From this, the following is obtained for the gain of the comparator 100:

wherein βsqP and βsqN are the transconductance parameters of the p-channel and n-channel transistors respectively with a ratio of the channel dimensions (channel width to channel length) of W L = 1. From this, it is clear that the gain of the comparator 100 may be adjusted via the factor k. According to the circuit arrangement 10 in Fig. 4 the following applies: k < 1 - comparator 100 with finite gain; k = 1 - comparator 100 with maximum gain and k > 1 - comparator 100 with symmetric hysteresis 16.

It is clear that, by selecting the width ratios k3 or k6, the size of the hysteresis 16 and the position of the upper threshold voltage NJSO or of the lower threshold voltage NJSU respectively may be adjusted independently of one another relative to the reference voltage N_REF. If the comparator 100 is to be operated with hysteresis 16, the upper threshold voltage NJSO is obtained as follows: f 2*LN*I_BIAS λ sqrt(k6) - 1

V _SO = sqrt βsqN*WN sqrt(l + k6) It is clear that the upper threshold voltage NJSO is positive for k6 > 1 and zero for k6 = 1.

Similarly, the following is obtained for the lower threshold voltage N JSU:

_, _crr l*LN*I BIAS _Λ l-sqrt(k3)

V SU = sqrt = * — - — - .

{ βsqN* WN ) sqrt(l + k3) It is clear that the lower threshold voltage NJSU is negative for k3 > 1 and zero for k3 = 1.

On the basis of these relationships, the difference NJSO - NJSU may be determined for the hysteresis 16, wherein the following applies: f2*LΝ*I BIASV f sqrt(k6) -l l-sqrt(k3)^|

Hysteresis = sqrt = * - — - — ~ — - .

^J βsqN*WN J ^sqrt(l + k6) sqrt(l + k3)J These equations apply for the assumption k3 > 1 and k6 > 1.

On the basis of the above-mentioned relationships, it is clear that comparators 100 with a hysteresis 16 or without hysteresis 16 may be obtained as a function of the width ratios k3 and k6. By mutually independent adjustment of the width ratios k3 > 1 and k6 > 1, the upper threshold voltage NJSO and the lower threshold voltage NJSU may be adjusted independently of one another. If the width ratios k3 and k6 are of equal size, a comparator 100 is obtained with symmetric hysteresis 16. If the width ratios k3 and k6 are different, an asymmetric hysteresis 16 is obtained with regard to the reference voltage NJREF.

It is also possible to position the upper threshold voltage NJSO or the lower threshold voltage NJSU on the reference voltage N_REF (c.f. in this respect also Fig. 3) by adjusting the width ratio k6 = 1 or the width ratio k3 = 1.

The width ratios k3 and/or k6 may also be set slightly greater than 1, for example k3 and/or k6 = 1.01, such that fine adjustment of the comparator 100 to the reference voltage NJREF may be achieved.

If the comparator 100 is set without hysteresis 16, i.e. the width ratios k3 and k6 are equal to k, wherein k < 1, the gain of the comparator 100 may be simply adjusted within a wide range. Where k3 = k6 = 1, the greatest possible gain is achieved. This is the point of transition to the comparator 100 with hysteresis 16. For the upper threshold voltage NJSO and the lower threshold voltage NJSU, the result, according to the above-mentioned relationships (where k3 = k6 = 1), is 0 Nolt, i.e. the switchover point of the comparator 100 is at the reference voltage N_REF. The hysteresis 16 is thus zero.

Adjustment of the width ratios k3 and k6 for programming the hysteresis 16 may be achieved in various possible ways. On the one hand, there is the possibility of providing, on integration of the circuit arrangement 10, a fixed channel width W3 for the transistor M3 and a fixed channel width W6 for the transistor M6.

Another possibility is obtained in that, by changing a metal mask of the transistors M3 and M6 after integration thereof into the circuit arrangement 10, the latter may be adapted subsequently to a desired hysteresis 16. For this purpose, a "metal-programmable" channel width may be set for the transistors M3 and M6.

Finally, through electrical programming of the integrated circuit arrangement 10, the hysteresis 16 maybe dynamically adapted to various instances of application of the comparator 100. This "electrically programmable" channel width may thus be set for the transistors M3 and M6. Both the setting of metal-programmable and of electrically programmable channel widths are generally known, such that they will not be explained in any more detail in the context of the present description.

Fig. 5 shows a modified embodiment of the circuit arrangement 10 according to Fig. 4. In the case of the circuit arrangement 10 according to Fig. 4, the voltage level at the output OUTP or at the inverting output OUTN in the HIGH state may assume the value of the supply voltage NDD. However, in the LOW switching state, the voltage potential 0 Nolt cannot be achieved. This may be desirable in the case of various application options for the comparator 100, in particular with subsequent digital circuits. According to Fig. 5, it is therefore proposed to connect the output OUTP with a further p-channel transistor M7, which is connected with a further current source I_BIAS2. hi this way, the possibility is obtained, in addition to logical inversion of the output signal OUTP into OUTΝ, of setting the LOW voltage signal at the value 0 Nolt.

Finally, Fig. 6 shows a further embodiment of the circuit arrangement 10, in which the p-channel transistors M3 and M6 are each subdivided into parallel-connected p- channel transistors M3ι and M3₂ and M6ι and M6₂ respectively. The p-channel transistor M3₂ may be connected via a switching means S3 to the supply voltage NDD and the p- channel transistor M6₂ via a switching means S6 to the supply voltage NDD. In this way, it is possible to program the channel width W3 or W6 of the transistors M3 or M6 respectively by actuating the switching means S3 and/or S6. This programming could be refined by subdividing the p-channel transistors M3 or M6 into more than two parallel-connected p- channel transistors, of which at least two would be connected to the supply voltage NDD via corresponding switching means S. Depending on actuation of the switching means, various setting options for the hysteresis 16 are then obtained, which, as explained, may also be asymmetric. LIST OF REFERENCE NUMERALS

100 Comparator INP Input

10 Circuit arrangement ΓNN Input

12 First coupling element OUTP Output

14 Second coupling element OUTN Output

16 Hysteresis HIGH Signal state

LOW Signal state t Time

N_REF Reference voltage

NjπSf Differential input voltage

NJSU Lower threshold voltage

NJSO Upper threshold voltage IJBIAS Current source

NDD Supply voltage

WP Channel width of the p-channel transistors

WΝ Channel width of the n-channel transistors

LP Channel length of the p-channel transistors LΝ Channel length of the n-channel transistors

Ml n-channel transistor

M2 p-channel transistor

M3 p-channel transistor

M4 n-channel transistor M5 p-channel transistor

M6 p-channel transistor

M3ι p-channel transistor (split)

M3₂ p-channel transistor (split)

M6t p-channel transistor (split) M6₂ p-channel transistor (split)

Claims

1. A comparator with a reference voltage input and a difference voltage input together with an inverting output and a non-inverting output, wherein a switching threshold of the comparator may be predetermined by an upper threshold voltage and a lower threshold voltage with regard to the reference voltage, characterized in that the upper threshold voltage (NJSO) and the lower threshold voltage (NJSU) may be set independently of one another.

2. A comparator as claimed in claim 2, characterized in that the upper threshold voltage (NJSO) and/or the lower threshold voltage (NJSU) matches the reference voltage (NJREF).

3. A comparator as claimed in one of the preceding claims, characterized in that the hysteresis (16) of the comparator (100) is asymmetric.

4. A comparator as claimed in one of the preceding claims, characterized in that p-channel transistors (M3, M6) are connected between the inverting output (OUTΝ) and the non-inverting output (OUTP), the channel widths (W3, W6) of which p-channel transistors (M3, M6) are adjustable.

5. A comparator as claimed in claim 4, characterized in that the channel widths

(W3, W6) are metal-programmable.

6. A comparator as claimed in one of the preceding claims, characterized in that the channel widths (W3, W6) are implemented in fixed manner in an integrated circuit arrangement (10).

7. A comparator as claimed in claim 4, characterized in that the channel widths (W3, W6) are electrically programmable.

8. A comparator as claimed in one of the preceding claims, characterized in that the p-channel transistors (M3, M6) comprise at least two parallel-connected p-channel transistors (M3ι, M3₂ and M6_ls M6₂ respectively), of which at least one p-channel transistor (M3₂ or M6₂) may be switched on or off by an actuatable switching means (S3, S6).

9. A comparator as claimed in one of the preceding claims, characterized in that the outputs (OUTP and/or OUTN) are connected with the base of a p-channel transistor (M7), which is fed by an additional current source (I_BIAS2).