EP1417579A2

EP1417579A2 - Interrupt-controller

Info

Publication number: EP1417579A2
Application number: EP01990568A
Authority: EP
Inventors: Jörg Franke; Joachim Ritter
Original assignee: TDK Micronas GmbH
Current assignee: TDK Micronas GmbH
Priority date: 2000-12-16
Filing date: 2001-12-14
Publication date: 2004-05-12
Also published as: WO2002048880A3; US20030172215A1; DE10062995A1; WO2002048880A2; JP2004516547A

Abstract

The invention relates to an interrupt controller for controlling the accessing of a processor (100) by interrupt sources (11, 12, 13, 14) and for controlling the associated branching of the signal processing programme (Rx) that is being executed with a current priority (Px) in the processor. The input side of the interrupt controller contains a predetermined number of interrupt interfaces (21, 22, 23, 24) for connecting the interrupt sources and a priority value (Pi) and an address (Adi) is allocated to each interrupt interface (21, 22, 23, 24). A selection device (30) determines the interrupt interfaces that have the highest priority value (Pmax) amongst the activated interrupt interfaces. The multiplexing of the individual interrupt interfaces (21, 22, 23, 24) to the processor (100) as an interrupt request (IR) is dependent on a priority comparator (40) and a branching logic (60), which control the triggering of a context backup (I) in the processor (100), based on the determined priority value (Pmax) and the current priority value (Px). If possible, the branching logic only determines the associated branching addresses (Vi) at the end of the context backup (I) that is being executed, in order to take into consideration the interrupt requests that are received during said context backup (I).

Description

Interrupt controller means

The invention relates to an interrupter control device, with which the access of a plurality of interrupter sources to a processor is controlled, which there corresponds to the active one

Interrupt source should switch the current program. As an example, here is a processor in a motor vehicle that is currently in a relatively insignificant program mode, e.g. Regulation of heating and ventilation. If a temperature sensor in the motor reports overheating during this time, the processor must be quickly switched to an engine control program so that there is no damage. The conflict in which two or more interrupter sources simultaneously send signals for changing the program is solved in that the interrupter control device only switches through the individual interrupter sources one after the other according to predetermined priorities to the interrupter input of the processor. For this purpose, each breaker source is connected to its own breaker interface, which is individualized by an address and a predetermined, in particular programmable, priority value. Each interrupt interface is generally also assigned at least two settable status registers (= flag), from which the interrupt control device recognizes an interrupt request triggered by the interrupt source and, on the other hand, indicates to the interrupt source that the respective interrupt interface has been enabled or disabled.

All interrupt interfaces are coupled to a selector that selects the one with the highest priority from the incoming interrupt requests. A priority comparator then compares the highest priority determined by the selection device with the priority of the program currently running and then sends an interrupt request signal (= interrupt request) to the interrupt input of the processor if the requested priority is higher than the priority of the current program. If the priority is lower, the current program continues undisturbed. Since the processor, as a rule, cannot immediately switch to the higher priority program even when the interrupt request has a high priority, an exchange of request and release signals takes place between it and the interrupter control device, which signals are usually referred to as "handshake" methods. Branch logic in the breaker control circuit is fed with the priority or address of the highest priority breaker interface that is for the Program branch is queried by the processor. The branching logic usually also controls the “handshake” method and supplies the associated signals.

The branch instructions issued by the branch logic trigger different interrupt routines in the processor (= interrupt routine), which are assigned to the respective priority of the interrupt interface to be switched through, but which always also contain a context-saving routine. The following operations are usually carried out during the context-saving routine: the program running in the processor is stopped, the contents of the registers present in the processor core are loaded into separate memory areas, the

Return address to the interrupted program is determined and saved and some status signals (= flags) are set or deleted. In the individual part of the respective interrupt routines, for example, new contents are read into some registers of the processor core, for example fixed coefficients, etc. The exchange of request, ready and blocking signals between the interrupt controller and the processor already mentioned ensures that this running program can only be interrupted at the permissible points.

The time of data backup in the processor is not negligible but, depending on the interrupt routine, requires a large number of cycles, for example between 10 and 30 cycles. During the course of the individual interrupt routine, new interrupt requests can only be detected by setting the corresponding flags in the associated interrupt interface. These set flags can only be evaluated again when the interrupt routine in the processor has expired and this is indicated by corresponding signals from the branch logic. The lockout time for new interrupt requests during the context backup makes up part of the total lockout time, which is also referred to as latency and is usually assigned to the entire interrupt routine. A shortening of the interrupt routine by a parallelization of the context protection and the other operations intervenes strongly in the architecture of the processor and increases its switching effort. For example, in the data sheet of the company "Micronas Intermetall" from September 29, 1999 with the

Description "CEVF-3 V3.2 Dashboard Controller Emulator", order number: 6251-479-3PD, part 9: "9. Interrupt Controller (IR) V1.5" on pages 71 to 79 an interrupter control device described, which contains these functional units, compare the block diagram given on page 72, in Fig. 9-1: "Block diagram".

The object of the invention is to provide an interrupter control device which, in cooperation with conventional processors, has a relatively low latency.

The object is achieved with an interrupter control device according to the preamble of claim 1 in that the branching address is delayed by the branching logic, in particular is only released or can be called up towards the end of the context-saving routine triggered by the interrupt signals.

The invention and advantageous embodiment are explained in more detail with reference to the figures of the drawing: FIG. 1 shows the block diagram of an interrupter control device according to the invention, FIG. 2 shows a branching diagram according to the prior art,

Figure 3 shows the corresponding branching scheme according to the invention and Figure 4 shows in the timing diagram a branching example according to the invention.

The block diagram according to FIG. 1 shows the functional blocks of an interrupter control device, which is generally designed as a monolithically integrated circuit. Figure 1 also shows four external interrupt sources 11, 12, 13, 14 and an external processor 100 (= CPU). The interrupt sources can be processors, transmitter devices or sensors that generate data or analog signals sl, s2, s3, s4 that serve as switchover signals for the processor 100. Figure 1 shows only four interrupt sources; as a rule, however, 16 or more interrupter sources can be connected to an interrupter control device.

Each breaker source 11, 12, 13, 14 is assigned an breaker interface 21, 22, 23, 24, which represents the respective input circuit of the breaker control device. The interrupter interfaces can be designed the same or different depending on the type of connectable interrupter sources. Each contains for identification

Interrupt interface has its own address Adi and an associated priority value Pi, which is advantageously also programmable via a bus line (not shown). A status register area (= flag area) is also assigned to each interrupt interface in order to by setting the corresponding status signals (= flag) to indicate an external interruption request, the readiness to accept the signals sent by the interrupter source or other statuses.

A selection device 30 determines from the current interrupt requests the one with the highest priority Pmax together with the associated address Adm. A priority comparator 40 compares this priority value Pmax with a currently valid priority value Px and generates an interrupt request signal IR if the priority value Pmax is higher than the current priority value Px. The new priority value Pmax is now stored as the new current priority value Px, for example in a register 35, in order to be available again for the current priority comparison at the next interrupt request. If the priority value Pmax is less than the current priority value Px, then this value need not be saved.

If the priority comparator 40 increases from the supplied priority value Pmax

Recognizes the priority value as the current priority value Px, then it uses an interrupt request signal IR to report an interrupt request to the processor 100, which is processed there as soon as the running program 'Rx makes this possible. The processing first triggers a context backup I (see FIG. 3) of the current program Rx, which is uniform for all priority cases, the context backup not only storing the data Dx but also storing the

Return address Ax is included in the interrupted program. Only after the context has been saved can the processor core be prepared for the new program, for which it must of course be informed which of the stored programs it should now process. When the context protection I has ended, the processor 100 notifies the branching logic 60 via control signals Vs, possibly also via a "handshake" method, that it now wants to get the required information about the program to be controlled or that it asks from the interrupt control device this information from the branch logic 60 or a register 55 which has previously been loaded accordingly by the branch logic. With this information, the processor triggers the branch internally by jumping the program pointer to the start address of the associated processing program.

The branching diagram of FIG. 2 shows the sequence of previous interrupt routines in which the branch addresses are formed at the beginning of the interrupt routine. First of all assumed that a signal processing Rx is running in the processor 100, which is assigned the priority Px. During the ongoing signal processing Rx, an interrupter source with the priority Pi becomes active, which for example is greater than the previous priority Px. If the priority Pi were lower than the previous Px, then nothing would change in the signal processing of the processor 100 and the program Rx would continue, compare the arrow pointing to the right, which indicates the program Rx.

In the assumed case with Pi> Px, the branch logic 60 with the possible branch addresses Vi is first activated. V0, V2, V3, V4 and V6 are given as possible branch addresses, the smaller number indicating the higher priority. The first called branch address V6 triggers an interrupt routine 16 in the processor 100, which contains a data backup Dx of the signal processing Rx currently running and a return address Ax in this program. The required time duration of the interrupt routine is shown by the adjacent time arrow t. No new interrupt command can be processed during the interrupt routine. As already mentioned, the associated time is referred to as latency, cf. arrows L6, L4, L3. After the interrupt routine 16 has expired, the processor 100 runs in the program R6. An interruption request received in the meantime with priority P4 can only be processed now. The branch logic 60 generates a branch instruction V4 depending on this interrupt request

Interrupt routine 14 with data backup D6 and return address A6 is triggered. A relatively early interrupt request with the higher priority P3 can only be processed after the time interval t3 when the interrupt routine 14 has been completed. The processor 100 is then in the signal processing program R4. By the end of t3, the processor has signaled that it is in an uninterruptible interrupt routine. If the processor releases this blocking signal, the branch logic 60 triggers the interrupt program 13 with the data backup D4 and the return address A4 via the branch instruction V3, which ends after the latency period L3. Processor 100 is now in program sequence R3. This program is either processed or interrupted by an interrupt request with a higher priority, i.e. PO, PI or P2. If the number of priority levels is less than the number of interrupt sources that can be connected, then it can be determined via the selection device 30 that, in the case of interrupt requests of the same priority, the one with the smaller or the larger address Adi should prevail. In FIG. 3, the branching diagram of an interrupter control device according to the invention is shown in comparison to FIG. As in the branching scheme of FIG. 2, the starting point is current signal processing Rx in the connected processor 100, to which a priority Px is assigned. An interrupt request Pi with the assumed higher priority value P6 triggers a uniform context backup I of the current program Rx with data backup Dx and return address Ax via the priority comparator 40 in accordance with the interrupt request IR it issues. In contrast to FIG. 2, the branch logic is only queried for the context save I, which thereby has the possibility of updating the last valid branch address Vi up to the end of the context save I. The programs are only branched after the context has been saved. 3 shows the possible branch addresses V6, V4, V3 with the associated programs R6, R4, R3. After jumping into the new program, this program is now considered the current program Rx with priority Px. For a new incoming interrupt request from an interrupter source, the functional sequence starts again at the top, this is shown in FIG. 3 by the dashed line from R6 to the beginning of the branching scheme.

FIG. 4 shows in the time diagram, using an assumed example, some branching processes taking place according to the invention. The duration of the individual context backups I is no longer linked to the respective priority Pi, as in FIG. 2, but rather it is a matter of uniform routines because the processor 100 only receives the corresponding branch information Vi at the end of the context backup. The blocking times L required for context saving I are therefore all of the same size in FIG. 3, because the most unfavorable number of registers to be saved must now be taken into account for uniform context saving I. During the blocking time L of each context backup I, a data backup Dx, D4, D4 'of the currently running program Rx, R4, R4 with the backup of the associated return address Ax, A4, A4' takes place. A preparation phase for the new program is not possible during the blocking period L or only if it is uniform for all priorities. The blocking times for the individual preparation phases follow the blocking time L of the associated context protection I, but are not indicated in FIG. 4. The time saved in the case of interruption requests is clear from the time diagram in FIG. 4. First, the running program Rx is interrupted by an interrupt request with priority P6. The associated first context protection Ii requires time L. An interruption request with priority P4 initially has no effect, because I) continues to run during time L. Only immediately before completion is the branch logic 60 queried, which determines as branch address V4, which corresponds to the interrupt request with the priority P4 which is received later. After completion of this first context protection Ii, the processor 100 works with the program R4. The required blocking time until the requested program R4 becomes active is shown by the arrow t4. With a branching scheme according to FIG. 2, at least the full blocking time L would have been added at time t4.

An interruption request with priority P3 occurs during program run R4. The context save routine, second context save I ₂ is therefore started again by the priority comparator 40 and the data D4 of the currently running program R4 with the return address A4 are saved therein. Another message appears during the context save I ₂

Interruption request with priority P5, i.e. a subordinate priority value. After the context save I _{2 has} expired, the branch logic 60 determines the branch address V3. The processor 100 now runs in the program R3 since there is no request for an interrupt with a higher priority. Since the program R3 was preceded by a branch, the processor resumes the interrupted program R4 after the end of this program (= End) and jumps to the fixed return address A4 of the second context protection I ₂ . However, program R4 cannot be completed because an interrupt request with priority value P2 has been received in the meantime. For this purpose, the branching logic 60 again triggers a context backup routine I ₂ , third context backup I, with a data backup D4 'and a return address A4' of the again interrupted program R4. Shortly before this routine I ₃ ends, a newly received interrupt request with the higher priority PI is recognized. At the end of context protection I ₃ , branch address VI is therefore determined by branch logic 60. The processor therefore continues to work in program R1 and not in program R2. The associated blocking time tl is very short.

The late output of the branch addresses Vi is achieved in a particularly advantageous manner by modifying the content of a register contained in the interrupter control device, which is used as a "vector table base" register (= VTB) and contains an address as content. This register, the content of which is an address, is queried by the processor 100 at the end of the context save I, and the processor then learns which program address to retrieve from the modified content, which still contains the original address and the additional information at previously unused locations is.

Of course, information about the branch address Vi can also reach the processor directly via suitable data connections and not only indirectly via an address or data modification of a register controlled by the processor. In addition, a security device is also expedient, which recognizes, for example, by checking the data width or the type of access, that the data on the data bus have nothing to do with a possible program branching. As a result, data on the bus, which can also be interpreted as branch information, can be recognized, blocked or rendered ineffective. Information about the type of access can be signaled, for example, by means of corresponding flags.

It is immaterial for the implementation of the invention whether the individual functional units of the interrupter control device are implemented in whole or in part in hardware or software technology. The special design is based on the optimization of the following criteria: required chip area, number of connecting legs, processing speed, flexibility, etc.

Claims

claims

1. Breaker control device for access control of breaker sources (11, 12, 13, 14) to a signal input of a processor (100) and for branching a program (Rx) currently running in the processor, wherein

- The breaker control device on the input side a predetermined number of

Contains interrupt interfaces (21, 22, 23, 24) for connecting the interrupt sources,

each interrupt interface (21, 22, 23, 24) is assigned, in particular a programmable priority value (Pi) and an address (Adi),

a selection device (30) looks for the one with the highest priority value (Pmax) and the associated address (Adm) from the interrupt interfaces activated by the interrupt sources,

- A priority comparator (40), an interrupter request signal (IR) in dependence on the highest priority value (Pmax) determined by the selection device and a current priority value (Px) that triggers a context protection (I) in the processor (100), and

a branch logic (60) corresponding to the highest priority value (Pmax) determined by the selection device (30) and a branch address (Vi) are generated,

characterized in that

- The branching address (Vi) in the branching logic (60) is only determined towards the end of the context saving by the branching logic (60) and is delivered to the processor (100) or can be called up by the latter, taking into account the current highest priority value (Pmax) becomes.

2. Interrupter control device according to claim 1, characterized in that with the same priority values (Pi) of the activated interrupt interfaces (21, 22, 23, 24), the selection device (30) according to a predetermined auxiliary criterion, in particular a value corresponding to the addresses (Adi) , performs.

3. Breaker control device according to claim 1 or 2, characterized in that the branch address (Vi) the content of a "vector table base" register (55), with its addressing by the processor (100) of the breaker control device in particular the willingness to branch is signaled, modified in such a way that the

Processor recognizes the own branch address required for the program execution.

4. Interrupter control device according to claim 1 or 3, characterized in that branch address (Vi) is designed as address modifications.

5. Interrupt control device according to claim 1 or 3, characterized in that the branch address (Vi) is designed as a data modification to a specific address.

6. Interrupt control device according to one of claims 1 to 5, characterized in that a security device recognize, block or render ineffective the erroneous output of an interrupt request (IR) or a branch address (Vi) before forwarding to the processor (100) ,