EP1417565A1

EP1417565A1 - Digital value division method

Info

Publication number: EP1417565A1
Application number: EP02791493A
Authority: EP
Inventors: Catherine Robert
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2001-07-17
Filing date: 2002-07-17
Publication date: 2004-05-12
Also published as: WO2003012625B1; FR2827683A1; FR2827683B1; WO2003012625A1

Abstract

A method for performing a division of a dividend by a divider including a step of determining a result of the division and a step of determining at least one flag associated with the result of the division, wherein the step of determining said flag occurs before the end of the step of determining said result.

Description

DIGITAL VALUE DIVISION METHOD

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to electronic devices adapted to performing computations, like microprocessors or microcontrollers. In particular, the present invention relates to divisions performed by these devices.

Discussion of the Related Art Conventionally, when a microprocessor divides a dividend by a divider, it stores the values of the operands (dividend and divider) into registers, then performs the division by means of the given algorithm. The result of the division, that is, the quotient and the remainder, are provided at the end of the division.

After this, the microprocessor calculates a number of flags associated with the result of the division. Generally, three flags are calculated. The three flags are the negative flag N, the zero flag Z, and the overflow flag V. These flags are useful to interpret the result of the division and the microprocessor can use them for other operations. The meaning of the flags is the following.

Negative flag N is at "1" if the most significant bit of the quotient is at "1" and at "0" in the opposite case. Zero flag Z is at "1" if the quotient is zero. Otherwise, it is at "0" .

Overflow flag V normally is at "0" . If the quotient cannot be represented by the number of bits which is assigned thereto or if the division is impossible (for example, both the divider and the dividend are equal to zero) , the overflow flag is at "1". The result of the division has no meaning and cannot be used, no more than flags N and Z.

To determine negative flag N, the microprocessor compares the most significant bit of the quotient to zero. For zero flag Z, all the bits of the quotient are compared to zero. To determine overflow flag V, the microprocessor examines among others the remainder and partial results leading to the calculation of the remainder. How the overflow flag is determined will not be described in detail herein.

Thus, in prior art, the flag calculation occurs at the end of the actual division, when the quotient and the remainder are known. This has disadvantages.

Indeed, in many cases, the value of one of the flags associated with the result of the division is necessary for the microprocessor to trigger the next instruction. For example, the microprocessor must process a specific instruction A if the zero flag is at "1" and another instruction B if the zero flag is at "0" . Further, if the overflow flag is at "1", the result of the division cannot be used and the determination of the quotient and of the remainder was useless. There again, the fact of having to wait until the end of the computation of the quotient and of the remainder results in a general loss of time for the micro- processor.

Summary of the invention

An object of the present invention is to provide an optimized division method.

Another object of the present invention is to provide a division method implemented by an electronic device and enabling optimal use thereof. To achieve this object, the present invention provides a method for performing a division of a dividend by a divider including a step of determining a result of the division and a step of determining at least one flag associated with the result of the division. The step of determining said flag occurs before the end of the step of determining said result.

According to an embodiment of the present invention, the step of determining said flag starts substantially at the same time as the step of determining said result. According to an embodiment of the present invention, said flag belongs to a group including a negative flag, a zero flag, and an overflow flag.

According to an embodiment of the present invention, the division is a division of signed numbers or a division of unsigned numbers, and the divider is a 16-bit number and the dividend is a 16- or 32-bit number.

According to an embodiment of the present invention, in the case of a division of signed numbers, the value of the negative flag is provided by the result of the logic operation (most significant bit of the dividend) XOR (most significant bit of the divider) , and, in the case of a division of unsigned numbers and of a 16- bit dividend, the negative flag is set to "1" if the divider is smaller than the dividend, and, in the case of a division of unsigned numbers and of a 32-bit dividend, the negative flag is set to "1" if the divider is smaller than the 16 most significant bits of the dividend.

According to an embodiment of the present invention, the zero flag is set to "1" if the following conditions are fulfilled:

in which "D" designates the dividend; "d" designate the divider; "Abs (D) " is the absolute value of the dividend; "Abs (d) " is the absolute value of the divider; "Dm" represents the 16 most significant bits of the dividend; "Dl" represents the 16 least significant bits of the dividend; "Abs(D)m" represents the 16 most significant bits of the absolute value of the dividend; "Abs(D)l" represents the 16 least significant bits of the absolute value of the dividend.

According to an embodiment of the present invention, the overflow flag is set to "1" if the following conditions are fulfilled:

wherein "D" designates the dividend; "d" designate the divider; "Abs' (d) " is a 17-bit number formed of one zero as the most significant bit followed by the 16 bits of the absolute value of the divider,- "Abs'(D)m" represents the 17 most significant bits of the absolute value of the dividend; "d'^H is a 17-bit number formed of one zero as the most significant bit followed by the 16 bits of the divider,- "D'm" is a 17-bit number formed of one zero as the most significant bit, followed by the 16 most significant bits of the dividend.

According to an embodiment of the present invention, the step of determining a result of the division includes the steps of: a) loading a 33-bit dividend register with a number, the least significant bits of which correspond to the bits of the dividend or of its absolute value and the other bit(s) of which have value "0" , b) loading a 17-bit divider register with a number, the

16 least significant bits of which correspond to the bits of the divider or of its absolute value and the most significant bit of which is "0", c) shifting by one bit to the left the content of the dividend register and putting a "0" in the place of the least significant bit, in the case where the division is a division of signed numbers and in the case where, the division being a division of unsigned numbers, the dividend is a 16-bit number, d) performing 16 iterations, each iteration including the steps of: dl) calculating the difference between the number formed by the 17 most significant bits of the dividend register and the content of the divider register, d2) if said difference is positive or zero, replacing the 17 most significant bits of the dividend register with the 17 bits of said difference, shifting by one bit to the left the content of the dividend register and introducing a "1" in the place of the least significant bit of the dividend register, d3) if said difference is negative, shifting by one bit to the left the content of the dividend register and introducing a "0" in the place of the least significant bit of the dividend register, e) when the iterations are over, providing the result of the division from the content of the dividend register. According to an embodiment of the present invention, the negative flag and the zero flag are calculated at the latest during shifting step c) and the overflow flag is calculated at the latest during the first iteration of step d) . The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.

Brief Description of the Drawings

Fig. 1 shows a general flowchart used in the present invention to perform a division,-

Figs. 2a to 2h illustrate the content of registers during the division of 7 by 2; and

Fig. 3 shows the flowchart of Fig. 1, indicating the flag calculation.

Detailed Description According to the present invention, the determination of the flags is performed before the complete determination of the result (quotient and remainder) of the division, and not after, as in prior art.

The present invention will be described in the context of divisions using the flowchart of Fig. 1. This flowchart, which has been developed by the applicant, is a general flowchart usable in many types of divisions. In the example of implementation of the present invention described hereafter, the performed divisions belong to four different types: the performed divisions can be divisions of 32-bit dividends by 16—bit dividers, or of 16-bit dividends by 16-bit dividers, and they can be divisions having operands which are both signed numbers or unsigned numbers.

In all four cases, the quotient and the remainder of the division are both provided over 16 bits. The quotient and the remainder are signed numbers if the division is a division of signed numbers and unsigned numbers if the division is a division of unsigned numbers. It should be reminded that a signed number can be positive, negative or zero. It is positive if its sign bit, that is, its most significant bit, is "0", and negative if its sign bit is "1". The other bits of the signed number are its value bits. In hexadecimal notation, the 16-bit signed numbers range from δOOOjj to 7FFFH (index H indicating that the notation is hexadecimal) . The 32-bit signed numbers range from 80000000_H to 7FFFFFFF_H. An unsigned number can only be positive or zero. Its most significant bit has no sign meaning. Over 16 bits, the unsigned numbers range from 000OH to FFFF_H.

To change from a positive signed number +X to the negative signed number -X, the complement to two of number +X is taken. To simply obtain the complement to two of a number, its complement to one can simply be taken (which corresponds to inverting all its bits) and one can be added. For example, over four bits, +7 can be written as "0111". The complement to one of +7 is "1000" and its complement to two is "1000" + "0001" = "1001". "1001" represents signed number -7.

Similarly, to change from a negative signed number -X to the positive signed number +X (for example, to obtain the absolute value of -X) , the complement to two of -X is taken. Thus, -7, which is written as "1001", has a complement to one equal to "0110" and a complement to two equal to "0111", which effectively corresponds to +7. At the beginning of each division, the microprocessor determines whether the division to be performed is a division of signed numbers or not, as well as the number of bits of the dividend (16 or 32) . If the division is a division of signed numbers and concerns at least one negative operand, the micro- processor stores the sign of this operand and calculates its absolute value. Indeed, the divisions are performed with positive numbers. If an operand is negative, its absolute value is used to perform the division. For example, to divide (-7) by (+2) , the division of 7 by 2 is performed, and the proper sign is resti- tuted to the result of the division. The operation of the flowchart of Fig. 1 will now be described. The specific hardware used in the implementation of the present invention will appear from the description.

In a step 1, the microprocessor examines the divider. In the case of a division of signed numbers and if the divider is a negative number, the microprocessor first calculates the absolute value of the divider. The microprocessor then loads a divider register DVS with the 16 bits of the divider or, if necessary, with the 16 bits of its absolute value. Register DVS is a 17-bit register. The most significant bit (leftmost) of register DVS is set to "0" and the 16 least significant bits of register DVS correspond to the 16 bits of the divider (or of its absolute value) .

In a step 2, the dividend is examined and, if it is a negative signed number, its absolute value is calculated. The microprocessor then loads the dividend (if necessary, its absolute value) into a dividend register DVD. The dividend register is a 33-bit register. If the dividend is coded over 32 bits, the 32 bits of the dividend or of its absolute value correspond to the 32 least significant bits (rightmost) of register DVD. The most significant bit of register DVD is at "0". If the dividend is a 16-bit number, the 16 bits of the dividend or of its absolute value are placed in the 16 first locations MDL of dividend register DVD and the 17 last locations MDH of register DVD, corresponding to the most significant bits, are set to "0".

The next step of the flowchart, step 3, is only carried out in three cases: the two cases where the division involves signed numbers and the case where, in a division of unsigned numbers, the dividend is a 16-bit number. During step 3, the content of register DVD is shifted by one bit to the left. The first location (the locations are counted from right to left) of register DVD if the register is coded over 32 bits, corresponding to the least significant bit, now vacant, is set to "0". After this operation, the most significant bit of the dividend (or of its absolute value) corresponds to the 33^rd location of register DVD, and to the 17^th location of register DVD if the dividend is coded over 16 bits. When the dividend is an unsigned number of 32 bits, step 3 is not carried out.

After step 3, or after step 2 if there is no step 3, a series of iterations starts. Each iteration includes several steps, noted from 4 to 8 and surrounded with dotted lines 15.

During step 4, difference MDH - DVS is calculated. For simplicity, the content of the divider register is called DVS and the content of the 17 last locations of dividend register DVD, corresponding to the 17 most significant bits of register DVD, is called MDH. Subtraction MDH - DVS is performed by a 17-bit subtractor, which can be a 17-bit adder adding MDH and the complement to two of DVS. The result of subtraction MDH - DVD is a 17-bit number.

During a step 5, it is examined whether the result of subtraction MDH - DVS is positive or zero.

If such is the case (MDH - DVS > 0) , the content of portion MDH of register DVD is replaced, in a step 6, with the result of subtraction MDH - DVS. Then, the entire register DVD is shifted by one bit to the left and a "1" is introduced in the first location, now vacant, of register DVD.

In the opposite case (MDH - DVS < 0) , the content of the entire register DVD is shifted in a step 7 by one bit to the left and a "0" is introduced in the first location of register DVD. In a step 8 which follows either step 6, or step 7, it is examined whether the number of iterations to be performed has been accomplished or not.

In the present case, it is desired to obtain a quotient of 16 bits and the number of iterations to be performed is 16, whether the dividend has 16 bits or 32 bits.

If the number of iterations is smaller than 16, an iteration is resumed by returning to step 4.

If the number of iterations is equal to 16, the iterative part of the division is over and it is proceeded to a step In step 9, the bits contained in portion MDH of register DVD are shifted by one bit to the right and a "0" is introduced in the place of the most significant bit, now vacant. The content of portion MDH of register DVD then directly corresponds to the remainder of the division if it is a division of unsigned numbers .

In a division of signed numbers in which the remainder is negative, which corresponds to the case where the dividend is negative, the sign of the remainder is restored in a step 10 by taking the complement to two of the content of portion MDH. Step

10 is only carried out if necessary.

For the quotient, the content of portion MDL of register DVD directly corresponds, in the case of a division of unsigned numbers, to the 16 bits of the quotient. In a division of signed numbers in which the quotient is negative, which corresponds to the case where the divider and the dividend have opposite signs, portion MDL of register DVD provides the absolute value of the quotient. The quotient is obtained in a step 11, by transformation of the absolute value of the quotient into a signed number. Like step 10, step 11 is only carried out if necessary.

After step 11, the result of the division, that is, the quotient and the remainder are determined. Steps 3 to 9 altogether correspond to 18 clock cycles (16 cycles for the itera- tions, one cycle for step 3 and one cycle for step 9) . Steps 1, 2, 10, and 11, when carried out, have a duration of one cycle each.

Before describing the determination of the flags by a microprocessor using the flowchart of Fig. 1, a simple example of division of unsigned numbers will be described in relation with

Figs. 2a to 2h. This example, mainly intended for illustrating steps 6 and 7 of the flowchart, relates to the division of 7 by 2, coded over four bits.

In Fig. 2a, register DVD is an 8-bit register. To be rigorous, a 9-bit register should have been taken, but since the operands are unsigned, a ninth location is not useful for regis- ter DVD. Portion MDL of register DVD (bits bO to b3) contains bits "0111" (7 in binary notation), and portion MDH of register DVD (bits b4 to b7) is loaded with "0"s.

Fig. 2b shows the content of divider register DVS. Register DVS here includes 4 bits and it is loaded with the bits of the divider, that is, "0010". The content of register DVS will not be modified during the division.

Figs. 2cl and 2c2 illustrate step 3. In Fig. 3cl, the content of register DVD is shifted by one location to the left. The most significant bit of register DVD is lost. In place of bit bO, now vacant, a "0" is placed as shown in Fig. 2c2.

Then, the iteration loop is started for the first time. Portion MDH of register DVD ("0000") is compared (step 4) to the content of register DVS ("0010") . Since DVS > MDH, difference MDH - DVS is negative and it is proceeded to step 7.

The content of register DVD of Fig. 2c2 is shifted by one location to the left and a "0" is placed at bO. The content of register DVD then is "00011100", as illustrated in Fig. 2d.

The first iteration is over. Four iterations have to be performed, and step 4 is resumed.

During the second iteration, the content of MDH

("0001") is still smaller than DVS ("0010"). Step 7 is resumed.

At the end of the second iteration, the content of register DVD is "00111000" (Fig. 2e) . In the third iteration, at step 4, the content of MDH

("0011") now is greater than DVS ("0010") . Step 6 is then carried out. First, MDH is replaced with difference MDH - DVS, equal to

"0001". The content of register DVD then is "00011000" (Fig.

2f1) . Register DVD is then altogether shifted by one bit to the left and a 1 is introduced in the place of least significant bit bO. It should be noted that, each time the content of register DVD is shifted by one bit to the left, the leftmost bit is lost and is replaced with its right-hand neighbor. At the end of the third iteration, the content of register DVD is "00110001" (Fig. 2f2) . One last iteration must be carried out. The content of portion MDH of register DVD ("0011") is then again compared to the content of register DVS ("0010") . MDH - DVS is greater than or equal to 0 and step 6 is carried out. Portion MDH of register DVD is thus replaced with the result of subtraction MDH - DVS, equal to "0001" (Fig. 2gl) . Then, register DVD is moved by one bit to the left and bit bO is set to 1. Fig. 2g2 illustrates the content of register DVD ("00100011") at the end of the fourth and last iteration.

It is then proceeded to step 9. Portion MDH of register DVD ("0010") is shifted by one bit to the right and a 0 is introduced in the place of the most significant bit, b7. As illustrated in Fig. 2h, the content of register DVD then is "00010011". Since the division is unsigned, portion MDL of register DVD ("0011") directly provides the quotient and portion MDH ("0001") provides the remainder. This effectively gives 7/2 = 3 ("0011") with a remainder equal to 1.

To determine the flags before having determined the quotient and the remainder, the applicant has first endeavored to find, for the different flags, expressions which do not use the quotient or the remainder. Further, the expressions chosen by the applicant for the different flags use values or partial results appearing in the first cycles of the division. Determination of negative flag N

When performing a division, the microprocessor knows whether it is a division of signed numbers or of unsigned numbers . It also knows the values of the dividend and of the divider.

In the case of a division of signed numbers, to find flag N (which corresponds in this case to the quotient sign) , the microprocessor performs at the beginning of the division, for example, at the same time as step 1, logic operation "XOR" between the most significant bit of the dividend (representative of the sign of the dividend) and the most significant bit of the divider (representative of the sign of the divider) . The XOR function can be implemented by a logic circuit, easily implemented at a hardware level and taking little room. The XOR opera- tion can also be performed by the microprocessor calculation unit. The result of the above XOR operation directly provides the value of flag N, available as soon as the first division cycle.

In the case of a division of unsigned numbers, the subtraction of a first and of a second number of 32 bits each is performed. The first 32-bit number is formed of the 32 bits of the dividend, if the dividend has 32 bits. If the dividend has 16 bits, the first 32-bit number is formed by taking "0s" for the 16 most significant bits and the 16 bits of the dividend for the least significant bits. The second 32-bit number is formed by taking the 16 bits of the divider as the most significant bits and "0s" for the 16 least significant bits. The subtraction of the first and second numbers is performed by the microprocessor by means of a 33-bit subtractor, to avoid loosing a possible overflow bit. If the second number is smaller than the first number, flag N is set to "1". It is set to "0" in the opposite case. The above operation is very fast and the value of flag N can also be obtained, in the case of a division of unsigned numbers, as soon as the first cycle of the division. The above subtraction may also be performed, to determine flag N, with 33- bit numbers obtained by placing a "0" respectively before the 32 bits of the first and second 32-bit numbers, the subtractor remaining a 33-bit subtractor. This is advantageous since the first 33-bit number corresponds to the content of dividend regis- ter DVD at the end of step 2. The microprocessor then uses the content of register DVD at the end of step 2 and the determination of flag N is performed during step 3.

As a conclusion, the value of negative flag N can be determined during the very first cycles of the division, and even as soon as the first cycle of the division. Its determination only requires, at most, the adding of a circuit implementing the XOR function and 33-bit subtractor, for unsigned numbers. Determination of zero flag Z

To determine zero flag Z, the four possible cases of the division are considered. Table 1 hereafter considers these cases and indicates the mathematical conditions which must be fulfilled for zero flag Z to be equal to 1. Table 1

In table 1, "D" designates the dividend; "d" designate the divider; "Abs (D) " is the absolute value of the dividend; "Abs (d) " is the absolute value of the divider,- "Dm" represents the 16 most significant bits of the dividend; "Dl" represents the 16 least significant bits of the dividend; "Abs(D)m" represents the 16 most significant bits of the absolute value of the dividend; "Abs(D)l" represents the 16 least significant bits of the absolute value of the dividend.

When the dividend is zero (D = 0) , the zero flag is set to "1" in the four cases.

Otherwise, for a division in which the dividend is a sixteen-bit number, the zero flag is further set to "1" if the absolute value of the divider is greater than the absolute value of the dividend in the case of a division of signed numbers and, in the case of a division of unsigned numbers, if the divider is greater than the dividend. For a 32-bit dividend, the zero flag is further set to

"1" if, in the case of a division of unsigned numbers, the 16 most significant bits are zero and if the divider is greater than the 16 least significant bits of the dividend. For a division of signed numbers, the conditions for setting the zero flag to "1" are conditions equivalent to those of the division of unsigned numbers, but they now involve the absolute values. The calculation of flag Z only requires a comparison over 16 bits. The 17-bit subtractor used to perform the iterations of the division can be used to perform the required comparisons to determine flag Z (according to cases, d > Dl, d > D, Abs(d) > Abs(D)l, and Abs(d) > Abs(D)l). In this case, the value of zero flag Z can be obtained in the first cycle in the case of a division of unsigned numbers and after the determination of the absolute values of the operands (steps 1 and 2) for a division of signed numbers. The required AND and OR gates are easy to implement in the circuit. The functions that they implement can further easily be carried out by the microprocessor itself. Determination of overflow flag V

For flag V, the applicant has also attempted to establish expressions that can be calculated early enough in the division. Table 2 hereafter sums up the four cases to be distinguished.

Table 2

In table 2, in addition to the abbreviations already defined in relation with table 1, abbreviation "Abs '(d)" represents a 17-bit number formed of one "0" as the most significant bit followed by the 16 bits of the absolute value of the divider. Abbreviation "d^MI represents a 17-bit number formed of one "0" as the most significant bit followed by the 16 bits of the divider. "Abs '(d)" and "d¹" thus correspond to the content of register DVS, loaded in step 1.

"Abs' (D)m" represents a 17-bit number formed of 17 most significant bits of the absolute value of the dividend. "Abs' (D)m" corresponds to the 17 most significant bits of register DVD as it is at the end of step 3. Abbreviation "D'm" represents a 17-bit number formed of one "0" as the most significant bit, followed by the 16 most significant bits of the dividend. "Abs¹ (D)m" and "D'm" both correspond to the 17 most significant bits (portion MDH) of register DVD as it appears at the beginning of step 4 of the first iteration, since the shifting by one location to the left of register DVD at step 3 does not occur in the case of a division of unsigned numbers with a 32-bit divider. The determination of the overflow flag is performed as follows .

In all cases, if the divider is zero, overflow flag V is set to 1, which is normal, since, in this case, the division cannot be performed. hen the dividend is a 16-bit number, in the case of a division of unsigned numbers, there is a single case where flag V is set to 1, which is the case where the divider is zero. In the case of a division of signed numbers, flag V is also set to "1" when the dividend corresponds to the minimum negative number (8000jj/ index H indicating a hexadecimal notation) and the divider corresponds to the maximum positive number (FFFF_H) . Thus, for 16-bit dividends, the microprocessor has all the required data to provide the value of overflow flag V almost immediately.

When the dividend is a 32-bit number, for unsigned divisions, the overflow flag is at 1 if, besides the case where d = 0, d' is smaller than or equal to D'm. For signed divisions, the overflow flag is at 1 if Abs' (d) is smaller than Abs' (D)m. As seen hereabove, d' and Abs' (d) correspond to the content of divider register DVS. Further, D'm and Abs' (D)m correspond to portion MDH of dividend register DVD of the beginning of step 4 of the first iteration.

Accordingly, it is possible to use the calculation of difference MDH - DVS performed in step 4 during the first iteration of the division to determine overflow flag V. If MDH is greater than or equal to DVS (unsigned operands) or MDH is strictly greater than DVS (signed operands), flag V is set to 1. The determination of flag V thus is performed in this case during the fourth clock cycle and requires no additional hardware element .

It should be noted that when flag V is at 1, the result of the division cannot be used, neither can flags N and Z. Accordingly, the precocious knowledge of value 1 for flag V enables stopping the calculation of the division and, when possible, of the other flags, if they have not already been determined. By means of the above mathematical expressions, the flags are calculated during the very first cycles of the division. In the worst case, the flags are known after the first four cycles of the division. The microprocessor can then take measures required by the knowing of the flags or, if flag V is at 1, stop the division.

Fig. 3 shows the flowchart of Fig. 1 with an indication of the steps in which the flags are calculated in a practical example of implementation. In this example, the negative flag and the zero flag are both calculated during step 3, and the overflow flag is calculated during the first iteration of the division.

As a conclusion, the present invention provides a flag calculation performed before determining the result of the division. Due to the expressions chosen for the flags, few additional hardware elements are required and the flag calculation easily integrates in the division algorithm. In the present invention, the flags may be obtained at most in four clock cycles, to be compared with the twenty cycles required in prior art. Indeed, in prior art, the actual division requires 16 cycles, to which must be added, if necessary, one cycle to calculate the absolute value of the dividend, one cycle to calculate the absolute value of the divider, one cycle to provide the signed remainder, and one cycle to provide the signed quotient, the determination of the flags only taking place after this.

Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, the present invention may apply to other cases than signed or unsigned divisions and 16- or 32-bit operands.

Those skilled in the art will readily adapt the principles described in the present invention to calculate in other cases flags of the division soon enough in the division cycle. For example, conditions similar to those described may be determined for flags Z, N, and V in the case of divisions with operands of 32, 64 bits, etc...

The flowchart of Fig. 1 has been given as an example only, and may be modified. For example, steps 1 and 10 may be respectively carried out after steps 2 and 11.

The present invention also applies to other methods for determining the result of a division.

The described hardware has been described as an example only and may be modified by those skilled in the art without departing from the field of the present invention.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accord- ingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.

What is claimed is:

Claims

1. A method for performing a division of a dividend by a divider including a step of determining a result of the division and a step of determining at least one flag associated with the result of the division, wherein step of determining said flag occurs before the end of the step of determining said result .

2. The method of claim 1, wherein the step of determining said flag starts substantially at the same time as the step of determining said result.

3. The method of claim 1, wherein said flag belongs to a group including a negative flag (N) , a zero flag (Z) , and an overflow flag (V) .

4. The method of any of claims 1 to 3, wherein the division is a division of signed numbers or a division of unsigned numbers, and wherein the divider is a 16-bit number and the dividend is a 16- or 32-bit number.

5. The method of claim 4, wherein, in the case of a division of signed numbers, the value of the negative flag (N) is provided by the result of the logic operation (most significant bit of the dividend) XOR (most significant bit of the divider) , and wherein, in the case of a division of unsigned numbers and of a 16-bit dividend, the negative flag (N) is set to "1" if the divider is smaller than the dividend, and, in the case of a divi- sion of unsigned numbers and of a 32-bit dividend, the negative flag (N) is set to "1" if the divider is smaller than the 16 most significant bits of the dividend.

6. The method of claim 4, wherein the zero flag (Z) is set to "1" if the following conditions are fulfilled:

in which "D" designates the dividend; "d" designate the divider; "Abs (D) " is the absolute value of the dividend; "Abs (d) " is the absolute value of the divider,- "Dm" represents the 16 most significant bits of the dividend; "Dl" represents the 16 least significant bits of the dividend; "Abs(D)m" represents the 16 most significant bits of the absolute value of the dividend; "Abs(D)l" represents the 16 least significant bits of the absolute value of the dividend.

7. The method of claim 4, wherein the overflow flag (V) is set to "1" if the following conditions are fulfilled:

wherein "D" designates the dividend; "d" designate the divider; "Abs ' (d) " is a 17-bit number formed of one zero as the most significant bit followed by the 16 bits of the absolute value of the divider,- "Abs'(D)m" represents the 17 most significant bits of the absolute value of the dividend; "d'" is a 17-bit number formed of one zero as the most significant bit followed by the 16 bits of the divider,- "D'm" is a 17-bit number formed of one zero as the most significant bit, followed by the 16 most significant bits of the dividend.

8. The method of claim 4, wherein the step of determining a result of the division includes the steps of: a) loading a 33-bit dividend register (DVD) with a number, the least significant bits of which correspond to the bits of the dividend or of its absolute value and the other bit(s) of which have value "0", b) loading a 17-bit divider register (DVS) with a number, the 16 least significant bits of which correspond to the bits of the divider or of its absolute value and the most significant bit of which is "0", c) shifting (3) by one bit to the left the content of the dividend register and putting a "0" in the place of the least significant bit, in the case where the division is a division of signed numbers and in the case where, the division being a division of unsigned numbers, the dividend is a 16-bit number, d) performing 16 iterations, each iteration including the steps of: dl) calculating the difference between the number formed by the 17 most significant bits (MDH) of the dividend register and the content of the divider register (4) , d2) if said difference is positive or zero (5) , replacing the 17 most significant bits of the dividend register with the 17 bits of said difference, shifting by one bit to the left the content of the dividend register and introducing a "1" in the place of the least significant bit of the dividend register (6) , d3) if said difference is negative, shifting by one bit to the left the content of the dividend register and introducing a "0" in the place of the least significant bit of the dividend register (7) , e) when the iterations are over, providing the result of the division from the content of the dividend register (9, 10, 11) .

9. The method of claim 8, wherein the negative flag and the zero flag are calculated at the latest during shifting step c) and the overflow flag is calculated at the latest during the first iteration of step d) .