EP1371139A2 - Low-noise load pump for phase-locking loop - Google Patents

Low-noise load pump for phase-locking loop

Info

Publication number
EP1371139A2
EP1371139A2 EP01990618A EP01990618A EP1371139A2 EP 1371139 A2 EP1371139 A2 EP 1371139A2 EP 01990618 A EP01990618 A EP 01990618A EP 01990618 A EP01990618 A EP 01990618A EP 1371139 A2 EP1371139 A2 EP 1371139A2
Authority
EP
European Patent Office
Prior art keywords
current
charge pump
current source
node
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01990618A
Other languages
German (de)
French (fr)
Inventor
Serge Ramet
Sébastien RIEUBON
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of EP1371139A2 publication Critical patent/EP1371139A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present invention relates to phase locked loops, and in particular the charge pumps contained in some of them.
  • FIG. 1 represents a conventional phase locked loop, comprising a charge pump 1.
  • a reference frequency Fref coming from a quartz oscillator is applied to a frequency divider 3.
  • the frequency divider 3 is a divider by R and it provides an Fdiv signal whose frequency is equal to Fref / R.
  • the signal Fdiv is supplied to a phase comparator 5.
  • the phase comparator 5 also receives a signal Fcomp whose frequency corresponds to the frequency Fvco of the signal at the output of the phase locked loop, divided by a predetermined number N.
  • the phase comparator 5 compares the phases of the Fdiv and Fcomp signals.
  • the phase comparator 5 emits a positive pulse on an output U if the signal Fdiv is ahead of the signal Fcomp, and a positive pulse on an output D if the signal Fcomp is ahead of the signal Fdiv.
  • the signals from the outputs U and D of the phase comparator are supplied to the charge pump 1.
  • the charge pump 1 drives a loop filter 7.
  • the charge pump 1 comprises a first current source 6A supplying a current II.
  • the current source 6A is coupled to the output OUT of the charge pump by means of a switch Sa.
  • the switch Sa is controlled by the signal U supplied by the phase comparator. When the signal U is in the high state, the switch Sa is closed, and the current II is supplied by the charge pump to the loop filter 7.
  • the charge pump comprises a second current source 6B through which a current 12
  • the current source 6B is coupled to the output of the charge pump via a switch Sb.
  • the switch Sb is controlled by the signal D supplied by the phase comparator 5. When the signal D is in the high state, the switch Sb is closed, and the current 12 is absorbed by the charge pump coming from the filter of loop 7.
  • the loop filter 7 outputs a control voltage Uc.
  • the voltage Uc controls a voltage-controlled oscillator 9.
  • the oscillator 9 supplies a frequency signal Fvco, at the output of the phase-locked loop.
  • the output of the oscillator 9 drives a frequency divider 11.
  • the frequency divider 11 divides the frequency Fvco by N and supplies the signal Fcomp to the phase comparator 5.
  • phase locked loop is as follows. For simplicity, we will consider that the loop filter 7 is only formed by a capacitor Cf connected between the output of the charge pump and the ground, the control voltage Uc being the voltage across the capacitor Cf. If the rising edge of the signal Fdiv arrives before the rising edge of the signal Fcomp, the output U of the phase comparator goes high.
  • the switch Sa then closes and the current II charges the capacity Cf of the loop filter 7.
  • the charging of the capacity Cf takes place during the time tempst of closing of the switch Sa.
  • the duration ⁇ t is equal to the interval of time separating the rising edges of the signals Fdiv and Fcomp. Load stored by the capacitor Cf thus increases by Il. ⁇ t, and the control voltage Uc increases.
  • the voltage-controlled oscillator 9 provides a signal of higher frequency Fvco and the difference between the phases of the signals Fdiv and Fcomp decreases. At equilibrium, the signals Fdiv and Fcomp have the same phase.
  • the phases of the signals Fdiv and Fco p are equal to the nearest static phase difference (it is recalled that the static phase difference is the phase difference presented by the phase locked loop when the latter is stabilized, this phase difference does not generally cause any charge variation in the loop filter 7). It is assumed here that the static phase difference is small enough to be neglected.
  • the frequency delivered by the oscillator 9 is too high, the rising edge of the signal Fcomp arrives before the rising edge of the signal Fdiv.
  • a positive pulse on terminal D then closes the switch Sb for a time ⁇ 't, in principle equal to the time interval between the appearance of the rising edges of the signals Fcomp and Fdiv.
  • Current 12 discharges capacitor Cf, its quantity of charge decreasing by I2. ⁇ 't.
  • the voltage Uc decreases and the frequency at the output of the oscillator 9 decreases.
  • the phase locked loop is stabilized and the phases of the Fdiv and Fcomp signals are the same.
  • FIGS. 2a to 2e illustrate the case where the frequency Fvco is lower than what is desired.
  • the rising edge of the signal Fdiv (FIG. 2a) occurs at an instant tl prior to the instant t2 at which the rising edge of the signal Fcomp occurs (FIG. 2b).
  • the signal U goes to the high state at the instant tl, but, as can be seen on the timing diagram illustrating the signal U (FIG. 2c), the signal U remains in the high state after the instant t2, and until t3.
  • the signal D (FIG. 2d) also goes high, which closes the switch Sb.
  • the loop filter 7 is crossed by the current 11-12 (FIG.
  • the capacitor Cf receives a small amount of electric charge equal to (Il-I2) x (t3-t2) .
  • the difference 11-12, positive or negative, is a residual intensity resulting from technological disparities affecting the current sources 6A and 6B.
  • the duration t3-t2 is chosen to be sufficient for each of the switches Sa and Sb to have time to close during this duration. Thus, even when the duration t2-tl is very short, the switches Sa or Sb have in all cases the time to close and the charge pump can inject (respectively draw) the current II (respectively 12) satisfactorily.
  • the signals Fdiv and Fcomp are in phase. Their rising edges both appear at the instant t'1.
  • the signals U and D both go high at time t'1, and remain high until time t'3.
  • the duration t'3-t'l is equal to the duration t3-t2.
  • the current lout at the outlet of the charge pump is equal to the difference 11-12. This difference causes a disruption of the frequency of the oscillator 9 which the loop will seek to compensate by producing a static phase difference, from which it results, in the power spectrum of the signal at the output of the phase locked loop, undesirable noise in the form of lines.
  • the phase-locked loop has a pass band, determined by the loop filter 7. In this pass band, the noise of the charge pump is predominant and it is desirable to reduce it.
  • An object of the present invention is to provide a charge pump for phase locked loop such that the noise due to the charge pump is very attenuated.
  • Another object of the present invention is to provide a charge pump in which errors due to technological dispersion are avoided.
  • Another object of the present invention is to provide a charge pump allowing the use of smaller components and allowing better integration.
  • Another object of the present invention is to provide a charge pump which consumes little.
  • the present invention provides a charge pump for phase-locked loop comprising a first current source, a second current source, several switches suitable for putting the first and / or the second current source in communication with the charge pump outlet.
  • the second current source is controlled by a control means capable of memorizing a quantity corresponding to the value of the current supplied by the first current source, so that the value of the current supplied by the second current source is substantially equal to the value of the current supplied by the first current source, the control means comprising a first branch comprising a first storage means and a second branch comprising a second storage means.
  • the control means memorizes said quantity shortly before the first and / or second current source is put into communication with the output of the charge pump.
  • the first current source is connected between a first supply voltage and a first node, and in which the switches comprise:
  • a first switch connected between the first node and the output of the charge pump, controlled by a first control signal
  • a fourth switch connected between the second node and the third node, controlled by the inverse of the second control signal, and the second current source is connected between the third node and a second supply voltage.
  • the first branch comprises a first capacitor coupled to the second node.
  • the second branch comprises a fifth switch connected between the second node and the output of the control means.
  • the second branch comprises a second capacitor coupled to the second node via the fifth switch.
  • the second current source is produced by a first transistor, of MOS type, of a first type of conductivity.
  • the first current source is produced by a second transistor, of a second type of conductivity, and is part of a current mirror, the current passing through the first current source being equal at ⁇ times the value of a reference current of the current mirror, with ⁇ greater than one.
  • the first switch is formed of a third transistor of the second conductivity type
  • the second switch is formed of a fourth transistor of the second conductivity type
  • the third switch is formed of a fifth transistor of the first conductivity type
  • the fourth switch is formed of a sixth transistor of the first conductivity type.
  • the first supply voltage is a positive voltage
  • the second supply voltage is the ground voltage
  • the transistors of the first conductivity type are N-channel MOS transistors and the transistors of the second type of conductivity are P-channel MOS transistors.
  • FIG. 3 represents an embodiment of a charge pump for phase-locked loop according to the present invention.
  • the charge pump is supplied by a first supply voltage VDD and a second supply voltage VSS.
  • the voltage VSS is the voltage of the ground (0 volts) and the voltage VDD is a positive voltage with respect to the ground.
  • the charge pump comprises a current source 14 disposed between the supply voltage VDD and a node A of the charge pump.
  • the current source 14 supplies a load current II, intended to supply a loop filter connected at the output of the charge pump when a control signal U supplied by a phase comparator situated upstream of the charge pump is equal to 1.
  • the current source 14 comprises a PMOS transistor MPI, the source of which is connected to the voltage VDD and the drain of which is connected to the node A.
  • the transistor II is crossed by the current II.
  • the gate of the MPI transistor is connected to the gate of a PMOS transistor MP2.
  • the source of the transistor MP2 is connected to the voltage VDD.
  • the drain of the transistor MP2 is connected to the gate of the transistor MP2.
  • the transistor MP2 is crossed by a reference current Iref.
  • the current source 14 is therefore produced using a current mirror.
  • the reference current Iref will not be chosen equal to II, but the geometry of the transistors MPI and MP2 will be chosen so that the current Il is equal to ⁇ .Iref, with ⁇ greater than 1.
  • the consumption and the surface of the charge pump will be reduced.
  • a first pair of switches is connected, each switch being formed by a PMOS transistor, Ml and M2 respectively.
  • the transistor M1 has its source connected to the node A and its drain connected to the output OUT of the charge pump.
  • the gate of the transistor Ml is controlled by a signal U, corresponding to the inverse of the signal U provided by the comparator phase tor.
  • the transistor M2 has its source connected to the node A and its drain connected to a node B of the charge pump.
  • the gate of transistor M2 is controlled by the signal U from the phase comparator.
  • the reverse signals U and U must partially overlap to ensure continuous conduction of the current source 14.
  • a second pair of switches consisting of two transistors M3 and M4, is connected to node B and to the output OUT.
  • the transistor M3 is an NMOS transistor, the drain of which is connected to the output OUT and the source to a node C of the charge pump.
  • the gate of transistor M3 is controlled by the output D of the phase comparator.
  • the transistor M4 is an NMOS transistor, the drain of which is connected to the node B and the source to the node C.
  • the gate of the transistor M4 is controlled by a signal D, which is the inverse of the signal D.
  • the inverse signals D and will partially overlap to ensure continuous conduction of the current source 14.
  • a current source 16 is disposed between the node C and the second supply voltage VSS.
  • the current source 16 is a controllable current source.
  • Current 12 which crosspiece is a function of a control signal UC2 supplied to a source control terminal 16.
  • the source 16 is formed of an NMOS transistor MN1, the drain of which is connected to the node C and the source of which is connected to the voltage VSS.
  • the gate of transistor MN1 receives the control signal UC2.
  • the control signal UC2 is a voltage signal.
  • the voltage UC2 corresponds to the voltage between the gate and source of the transistor MN1.
  • the transistor MN1 is traversed by the current 12.
  • the value of the drain current is, in the first order, unequivocally linked to the value of the gate-source voltage, the current discharge 12 depends on the control voltage UC2 unequivocally.
  • the control terminal of the current source 16 is attacked by a control circuit 18 supplying the voltage UC2.
  • the circuit 18 comprises a first branch formed by a capacitor C1 connected between the node B and the supply voltage VSS.
  • the circuit 18 comprises a second branch, also connected between the node B and the supply voltage VSS, comprising a switch S connected in series with a capacitor C2.
  • the switch S is connected between the node B and the output of the circuit 18 supplying the voltage UC2.
  • the capacitor C2 is connected between the output of the circuit 18 and the second supply voltage VSS.
  • Switch S is controlled by an AZ signal.
  • the switch S is open (node B isolated from the output of circuit 18) when the signal AZ is equal to 1.
  • the switch S is closed (node B in communication with the output of circuit 18) when the signal AZ is equal at 0.
  • the signal AZ is shown ( Figure 2f).
  • the signal AZ also is equal to 0.
  • the only transistors passing through the pairs of switches are the transistors M2 and M4.
  • the switch S is closed and the node B is in communication with the output of the circuit 18.
  • the transistors Ml and M3 being blocked, no current flows through the output OUT.
  • the current II arriving at the node A crosses the transistor M2 and arrives at the node B.
  • part of the current II is used to charge the capacitor Cl and, by means of the closed switch S, the capacitor C2.
  • the part of the current II which has not been used to charge the capacitors Cl and C2 passes through the transistor M4 and the transistor MN1.
  • the capacitors C1 and C2 are charged and do not absorb any current. Consequently, the current II supplied by the current source 14 passes completely through the current source 16, and, therefore, the current source 16 is traversed by a current 12 strictly equal to the current II.
  • This last point is particularly important. Indeed, in the prior art, even if we try to ensure that the current sources 6A and 6B are identical, the technological dispersions cause, as we have seen, that the current It is never strictly equal to 12.
  • current II is in principle a constant current, current II is affected by noise. Current II is thus subjected to variations, small, of course, but introducing noise at the output of the phase locked loop when the charge pump is in communication with the loop filter.
  • the capacitor C2 can be omitted. Indeed, the value of this capacitor is low, typically of the order of 5 picofarads. If the transistor MN1 is produced so that its parasitic gate-source capacitance is sufficient, for example using a transistor of sufficient dimensions, the parasitic capacitance of the transistor MN1 can serve as capacitor C2 and the latter can be eliminated.
  • the signal U goes to "1". This has the effect of turning on the transistor Ml and blocking the transistor M2.
  • Current II arriving at node A is then directed to output OUT and injected into the loop filter to reduce the phase difference between the signals Fdiv and Fcomp.
  • the signal D remains equal to "0".
  • the transistor M3 therefore remains blocked, and the transistor M4 remains on.
  • the current 12 passing through the current source 16 is supplied by the capacitor C1, which is discharged at constant current by the transistors M4 and MN1.
  • the value of the voltage UC2 does not vary appreciably between the instants tl and t2, and the current 12, between the instants tl and t2, remains equal to the value of the current II at the instant t0.
  • the capacity of the capacitor C1 is chosen to be large enough to be able to supply the current 12 for a sufficient duration corresponding to the phase difference between Fdiv and Fcomp.
  • a typical value of the capacitor Cl is about 30 picofarads.
  • the source of II is affected by noise which can be broken down into low frequency noise and high frequency noise.
  • noise which can be broken down into low frequency noise and high frequency noise.
  • the low frequency noise having been memorized at the instant t0 by the current 12, the current supplied at the output OUT is free from the low frequency noise affecting the source II, which represents a considerable advantage compared to one prior art.
  • the signal AZ goes to "1" and the switch S closes.
  • the signals U, D and AZ all being equal to "0".
  • the capacitors C1 and C2 are charged, and the current 12 is strictly equal to the current II.
  • the instant t4 is chosen so that the switches of the first and of the second pair of switches have had time to switch.
  • the instant t4 can be chosen within a relatively long time range.
  • the circuit 18 is a circuit for controlling the current source 16, which ensures that the current 12 passing through the current source 16 follows the variations of the current II passing through the current source 14.
  • the means 18 stores the value of current II and, when the two current sources 14 and 16 are in communication with the output OUT, the value of current 12 supplied by the source of current 16 is equal to the memorized value of current II.
  • this allows on the one hand a reduction in the residual current 11-12 supplied at the output of the charge pump when each of the sources is in communication with the loop filter, and on the other hand a suppression low frequency noise in the current supplied by the charge pump.
  • Another advantage of the charge pump according to the present invention is that it is easily integrated. It can use smaller transistors and consumes less than in the prior art. To have a good pairing on the current mirrors and to have a low low frequency noise, it is conventionally necessary to provide large transistors. As, according to the invention, a storage is carried out and therefore the low frequency noise and the difference 11-12 are eliminated, it is possible to use transistors MPI, MP2 and MN1 which are smaller than in the prior art. In addition, conventionally, to reduce the low frequency noise in the loop, the current of sources II and 12 is increased (the noise of a MOS transistor increases in VI but the gain of this noise towards the output is in l / l) . As the low frequency noise is suppressed, the current value can be reduced. The Iref-Il factor is also a reason for the drop in consumption. Of course, the present invention is susceptible to various variants and modifications which will appear to those skilled in the art.
  • the voltage VDD was a positive supply voltage and the voltage VSS a supply voltage equal to 0 (ground voltage).
  • the voltage VSS can be different, for example negative with respect to the ground of the circuit.
  • the polarities of the VDD and VSS voltages can be reversed. In this case, the N type transistors will be replaced by P type transistors, and vice versa.
  • the MOS transistors of the embodiment described can be replaced by bipolar transistors if desired, but, in this case, the current source 16 must be produced so that it takes only a negligible current on its control terminal, so that the voltage on its control terminal, if the current source 16 is voltage controlled, remains at a constant value.
  • switch S has not been specifically described.
  • it can be any suitable switching device, for example an MOS transistor connected and controlled appropriately.

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Abstract

The invention concerns a load pump for phase-locking loop comprising a first current source (14), a second current source (16), several switches (M1, M2, M3, M4) adapted to communicate the first and/or the second current source with the load pump output (OUT). The second current source is driven by control means (18) adapted to store a physical quantity corresponding to the value of the current (l1) supplied by the first current source (14), so that the value of current (l2) supplied by the second current source is substantially equal to the value of current (l1) supplied by the first current source.

Description

POMPE DE CHARGE A FAIBLE BRUIT POUR BOUCLE A VERROUILLAGE DE LOW NOISE CHARGING PUMP FOR LOCKING LOOP
PHASEPHASE
La présente invention concerne les boucles à verrouillage de phase, et en particulier les pompes de charge contenues dans certaines de celles-ci.The present invention relates to phase locked loops, and in particular the charge pumps contained in some of them.
La figure 1 représente une boucle à verrouillage de phase classique, comportant une pompe de charge 1. Une fréquence de référence Fref issue d'un oscillateur à quartz est appliquée à un diviseur de fréquence 3. Le diviseur de fréquence 3 est un diviseur par R et il fournit un signal Fdiv dont la fréquence est égale à Fref/R. Le signal Fdiv est fourni à un comparateur de phase 5. Le comparateur de phase 5 reçoit également un signal Fcomp dont la fréquence correspond à la fréquence Fvco du signal en sortie de la boucle à verrouillage de phase, divisée par un nombre prédéterminé N. Le comparateur de phase 5 compare les phases des signaux Fdiv et Fcomp. Le comparateur de phase 5 émet une impulsion positive sur une sortie U si le signal Fdiv est en avance sur le signal Fcomp, et une impulsion positive sur une sortie D si le signal Fcomp est en avance sur le signal Fdiv. Les signaux issus des sorties U et D du comparateur de phase sont fournis à la pompe de charge 1. La pompe de charge 1 attaque un filtre de boucle 7. La pompe de charge 1 comprend une première source de courant 6A fournissant un courant II . La source de courant 6A est couplée à la sortie OUT de la pompe de charge par 1 ' intermédiaire d'un commutateur Sa. Le commutateur Sa est commandé par le signal U fourni par le comparateur de phase. Lorsque le signal U est à l'état haut, le commutateur Sa est fermé, et le courant II est fourni par la pompe de charge au filtre de boucle 7. La pompe de charge comprend une deuxième source de courant 6B traversée par un courant 12. La source de courant 6B est couplée à la sortie de la pompe de charge par l'intermédiaire d'un commutateur Sb. Le commutateur Sb est commandé par le signal D fourni par le comparateur de phase 5. Lorsque le signal D est à l'état haut, le commutateur Sb est fermé, et le courant 12 est absorbé par la pompe de charge en provenance du filtre de boucle 7.FIG. 1 represents a conventional phase locked loop, comprising a charge pump 1. A reference frequency Fref coming from a quartz oscillator is applied to a frequency divider 3. The frequency divider 3 is a divider by R and it provides an Fdiv signal whose frequency is equal to Fref / R. The signal Fdiv is supplied to a phase comparator 5. The phase comparator 5 also receives a signal Fcomp whose frequency corresponds to the frequency Fvco of the signal at the output of the phase locked loop, divided by a predetermined number N. The phase comparator 5 compares the phases of the Fdiv and Fcomp signals. The phase comparator 5 emits a positive pulse on an output U if the signal Fdiv is ahead of the signal Fcomp, and a positive pulse on an output D if the signal Fcomp is ahead of the signal Fdiv. The signals from the outputs U and D of the phase comparator are supplied to the charge pump 1. The charge pump 1 drives a loop filter 7. The charge pump 1 comprises a first current source 6A supplying a current II. The current source 6A is coupled to the output OUT of the charge pump by means of a switch Sa. The switch Sa is controlled by the signal U supplied by the phase comparator. When the signal U is in the high state, the switch Sa is closed, and the current II is supplied by the charge pump to the loop filter 7. The charge pump comprises a second current source 6B through which a current 12 The current source 6B is coupled to the output of the charge pump via a switch Sb. The switch Sb is controlled by the signal D supplied by the phase comparator 5. When the signal D is in the high state, the switch Sb is closed, and the current 12 is absorbed by the charge pump coming from the filter of loop 7.
Le filtre de boucle 7 fournit en sortie une tension de commande Uc . La tension Uc commande un oscillateur commandé en tension 9. L'oscillateur 9 fournit un signal de fréquence Fvco, en sortie de la boucle à verrouillage de phase. La sortie de l'oscillateur 9 attaque un diviseur de fréquence 11. Le diviseur de fréquence 11 divise la fréquence Fvco par N et fournit le signal Fcomp au comparateur de phase 5.The loop filter 7 outputs a control voltage Uc. The voltage Uc controls a voltage-controlled oscillator 9. The oscillator 9 supplies a frequency signal Fvco, at the output of the phase-locked loop. The output of the oscillator 9 drives a frequency divider 11. The frequency divider 11 divides the frequency Fvco by N and supplies the signal Fcomp to the phase comparator 5.
Le fonctionnement de la boucle à verrouillage de phase est le suivant . Pour simplifier, on va considérer que le filtre de boucle 7 est seulement formé d'un condensateur Cf relié entre la sortie de la pompe de charge et la masse, la tension de commande Uc étant la tension aux bornes du condensateur Cf . Si le front montant du signal Fdiv arrive avant le front montant du signal Fcomp, la sortie U du comparateur de phase passe à l'état haut.The operation of the phase locked loop is as follows. For simplicity, we will consider that the loop filter 7 is only formed by a capacitor Cf connected between the output of the charge pump and the ground, the control voltage Uc being the voltage across the capacitor Cf. If the rising edge of the signal Fdiv arrives before the rising edge of the signal Fcomp, the output U of the phase comparator goes high.
Le commutateur Sa se ferme alors et le courant II charge la capacité Cf du filtre de boucle 7. La charge de la capacité Cf se fait pendant le temps Δt de fermeture du commutateur Sa. En principe, la durée Δt est égale à l'intervalle de temps séparant les flancs de montée des signaux Fdiv et Fcomp. La charge emmagasinée par le condensateur Cf augmente ainsi de Il.Δt, et la tension de commande Uc augmente. Par suite, l'oscillateur commandé en tension 9 fournit un signal de fréquence Fvco plus élevée et 1 'écart entre les phases des signaux Fdiv et Fcomp diminue. A l'équilibre, les signaux Fdiv et Fcomp ont une même phase. La fréquence fournie par l'oscillateur commandé en tension 9 est alors à la valeur souhaitée Fvco = Fref . (N/R) . En toute rigueur, les phases des signaux Fdiv et Fco p sont égales à l'écart de phase statique près (on rappelle que l'écart de phase statique est l'écart de phase présenté par la boucle à verrouillage de phase lorsque celle-ci est stabilisée, cet écart de phase n'entraînant globalement aucune variation de charge dans le filtre de boucle 7) . On suppose ici que l'écart de phase statique est suffisamment faible pour être négligé. Inversement, si la fréquence délivrée par l'oscillateur 9 est trop élevée, le front montant du signal Fcomp arrive avant le front montant du signal Fdiv. Une impulsion positive sur la borne D ferme alors le commutateur Sb pendant un temps Δ't, en principe égal à l'intervalle de temps entre l'apparition des fronts montant des signaux Fcomp et Fdiv. Le courant 12 décharge le condensateur Cf, sa quantité de charge décroissant de I2.Δ't. La tension Uc décroît et la fréquence en sortie de l'oscillateur 9 diminue. A l'équilibre, la boucle à verrouillage de phase est stabilisée et les phases des signaux Fdiv et Fcomp sont les mêmes.The switch Sa then closes and the current II charges the capacity Cf of the loop filter 7. The charging of the capacity Cf takes place during the time tempst of closing of the switch Sa. In principle, the duration Δt is equal to the interval of time separating the rising edges of the signals Fdiv and Fcomp. Load stored by the capacitor Cf thus increases by Il.Δt, and the control voltage Uc increases. As a result, the voltage-controlled oscillator 9 provides a signal of higher frequency Fvco and the difference between the phases of the signals Fdiv and Fcomp decreases. At equilibrium, the signals Fdiv and Fcomp have the same phase. The frequency supplied by the voltage-controlled oscillator 9 is then at the desired value Fvco = Fref. (N / R). Strictly speaking, the phases of the signals Fdiv and Fco p are equal to the nearest static phase difference (it is recalled that the static phase difference is the phase difference presented by the phase locked loop when the latter is stabilized, this phase difference does not generally cause any charge variation in the loop filter 7). It is assumed here that the static phase difference is small enough to be neglected. Conversely, if the frequency delivered by the oscillator 9 is too high, the rising edge of the signal Fcomp arrives before the rising edge of the signal Fdiv. A positive pulse on terminal D then closes the switch Sb for a time Δ't, in principle equal to the time interval between the appearance of the rising edges of the signals Fcomp and Fdiv. Current 12 discharges capacitor Cf, its quantity of charge decreasing by I2.Δ't. The voltage Uc decreases and the frequency at the output of the oscillator 9 decreases. At equilibrium, the phase locked loop is stabilized and the phases of the Fdiv and Fcomp signals are the same.
Le fonctionnement décrit précédemment est défectueux dans le cas où les impulsions sur les bornes U ou D sont de très courte durée. En effet, le temps nécessaire pour actionner les commutateurs Sa ou Sb peut s'avérer supérieur à la durée de l'impulsion produite par le comparateur de phase. Dans ce cas, les commutateurs Sa ou Sb n'ont pas le temps de se fermer et ne remplissent pas leur fonction. Une solution à ce problème consiste à fermer le commutateur commandé Sa ou Sb pendant une durée plus longue, et à fermer parallèlement l'autre des commutateurs, comme cela est illustré par les diagrammes des figures 2a à 2e.The operation described above is defective in the event that the pulses on terminals U or D are of very short duration. In fact, the time required to actuate the switches Sa or Sb may prove to be greater than the duration of the pulse produced by the phase comparator. In this case, the switches Sa or Sb do not have time to close and do not fulfill their function. One solution to this problem consists in closing the controlled switch Sa or Sb for a longer period of time, and in parallel closing the other of the switches, as illustrated by the diagrams in Figures 2a to 2e.
Les figures 2a à 2e illustrent le cas où la fréquence Fvco est plus faible que ce qui est souhaité. Dans ce cas, le front montant du signal Fdiv (figure 2a) se produit à un instant tl antérieur à 1 ' instant t2 auquel se produit le front montant du signal Fcomp (figure 2b) . Le signal U passe à l'état haut à l'instant tl, mais, comme cela peut être vu sur le chronogramme illustrant le signal U (figure 2c), le signal U reste à l'état haut après l'instant t2, et ce jusqu'à un instant t3. Pendant la durée t3-t2, le signal D (figure 2d) passe également à l'état haut, ce qui ferme le commutateur Sb. Pendant la durée t3-t2, le filtre de boucle 7 est traversé par le courant 11-12 (figure 2e) et le condensateur Cf reçoit une faible quantité de charge élec- trique égale à (Il-I2)x(t3-t2) . La différence 11-12, positive ou négative, est une intensité résiduelle résultant de disparités technologiques affectant les sources de courant 6A et 6B. La durée t3-t2 est choisie suffisante pour que chacun des commutateurs Sa et Sb ait le temps de se fermer pendant cette durée. Ainsi, même lorsque la durée t2-tl est très faible, les commutateurs Sa ou Sb ont dans tous les cas le temps de se fermer et la pompe de charge peut injecter (respectivement prélever) le courant II (respectivement 12) de façon satisfaisante.FIGS. 2a to 2e illustrate the case where the frequency Fvco is lower than what is desired. In this case, the rising edge of the signal Fdiv (FIG. 2a) occurs at an instant tl prior to the instant t2 at which the rising edge of the signal Fcomp occurs (FIG. 2b). The signal U goes to the high state at the instant tl, but, as can be seen on the timing diagram illustrating the signal U (FIG. 2c), the signal U remains in the high state after the instant t2, and until t3. During the period t3-t2, the signal D (FIG. 2d) also goes high, which closes the switch Sb. During the period t3-t2, the loop filter 7 is crossed by the current 11-12 (FIG. 2e) and the capacitor Cf receives a small amount of electric charge equal to (Il-I2) x (t3-t2) . The difference 11-12, positive or negative, is a residual intensity resulting from technological disparities affecting the current sources 6A and 6B. The duration t3-t2 is chosen to be sufficient for each of the switches Sa and Sb to have time to close during this duration. Thus, even when the duration t2-tl is very short, the switches Sa or Sb have in all cases the time to close and the charge pump can inject (respectively draw) the current II (respectively 12) satisfactorily.
A l'équilibre, comme cela est représenté en figures 2a à 2e après l'instant t'O, les signaux Fdiv et Fcomp sont en phase . Leurs fronts montants apparaissent tous deux à 1 ' instant t'1. Les signaux U et D passent tous deux à l'état haut à l'instant t'1, et restent à l'état haut jusqu'à l'instant t'3. La durée t'3-t'l est égale à la durée t3-t2. Comme cela peut être vu en figure 2e, à l'équilibre, le courant lout en sortie de la pompe de charge est égal à la différence 11-12. Cette différence provoque un dérèglement de la fréquence de 1 ' oscillateur 9 que la boucle va chercher à compenser en produisant un écart de phase statique, d'où il résulte, dans le spectre de puissance du signal en sortie de la boucle à verrouillage de phase, un bruit indésirable sous forme de raies.At equilibrium, as shown in FIGS. 2a to 2e after the instant t'O, the signals Fdiv and Fcomp are in phase. Their rising edges both appear at the instant t'1. The signals U and D both go high at time t'1, and remain high until time t'3. The duration t'3-t'l is equal to the duration t3-t2. As can be seen in Figure 2e, at equilibrium, the current lout at the outlet of the charge pump is equal to the difference 11-12. This difference causes a disruption of the frequency of the oscillator 9 which the loop will seek to compensate by producing a static phase difference, from which it results, in the power spectrum of the signal at the output of the phase locked loop, undesirable noise in the form of lines.
Par ailleurs, la boucle à verrouillage de phase présente une bande passante, déterminée par le filtre de boucle 7. Dans cette bande passante, le bruit de la pompe de charge est prépondérant et il est souhaitable de le diminuer.Furthermore, the phase-locked loop has a pass band, determined by the loop filter 7. In this pass band, the noise of the charge pump is predominant and it is desirable to reduce it.
En outre, les pompes de charge de l'art antérieur consomment beaucoup et occupent une place relativement importante. Un objet de la présente invention est de prévoir une pompe de charge pour boucle à verrouillage de phase telle que le bruit dû à la pompe de charge soit très atténué.In addition, the charge pumps of the prior art consume a lot and occupy a relatively large space. An object of the present invention is to provide a charge pump for phase locked loop such that the noise due to the charge pump is very attenuated.
Un autre objet de la présente invention est de prévoir une pompe de charge dans laquelle des erreurs dues à des disper- sions technologiques sont évitées.Another object of the present invention is to provide a charge pump in which errors due to technological dispersion are avoided.
Un autre objet de la présente invention est de prévoir une pompe de charge permettant d'utiliser des composants plus petits et permettant une meilleure intégration.Another object of the present invention is to provide a charge pump allowing the use of smaller components and allowing better integration.
Un autre objet de la présente invention est de prévoir une pompe de charge qui consomme peu.Another object of the present invention is to provide a charge pump which consumes little.
Pour atteindre ces objets, la présente invention prévoit une pompe de charge pour boucle à verrouillage de phase comportant une première source de courant, une deuxième source de courant, plusieurs commutateurs propres à mettre en communication la première et/ou la deuxième source de courant avec la sortie de la pompe de charge. La deuxième source de courant est commandée par un moyen de commande propre à mémoriser une grandeur correspondant à la valeur du courant fourni par la première source de courant, de sorte que la valeur du courant fourni par la deuxième source de courant est sensiblement égale à la valeur du courant fourni par la première source de courant, le moyen de commande comprenant une première branche comportant un premier moyen de mémorisation et une deuxième branche comportant un deuxième moyen de mémorisation. Selon un mode de réalisation de la présente invention, le moyen de commande mémorise ladite grandeur peu avant la mise en communication de la première et/ou de la seconde source de courant avec la sortie de la pompe de charge. Selon un mode de réalisation de la présente invention, la première source de courant est connectée entre une première tension d'alimentation et un premier noeud, et dans laquelle les commutateurs comprennent :To achieve these objects, the present invention provides a charge pump for phase-locked loop comprising a first current source, a second current source, several switches suitable for putting the first and / or the second current source in communication with the charge pump outlet. The second current source is controlled by a control means capable of memorizing a quantity corresponding to the value of the current supplied by the first current source, so that the value of the current supplied by the second current source is substantially equal to the value of the current supplied by the first current source, the control means comprising a first branch comprising a first storage means and a second branch comprising a second storage means. According to an embodiment of the present invention, the control means memorizes said quantity shortly before the first and / or second current source is put into communication with the output of the charge pump. According to an embodiment of the present invention, the first current source is connected between a first supply voltage and a first node, and in which the switches comprise:
- un premier commutateur connecté entre le premier noeud et la sortie de la pompe de charge, commandé par un premier signal de commande,a first switch connected between the first node and the output of the charge pump, controlled by a first control signal,
- un deuxième commutateur connecté entre le premier noeud et un deuxième noeud, commandé par l'inverse du premier signal de commande, - un troisième commutateur connecté entre la sortie de la pompe de charge et un troisième noeud, commandé par un deuxième signal de commande,- a second switch connected between the first node and a second node, controlled by the inverse of the first control signal, - a third switch connected between the output of the charge pump and a third node, controlled by a second control signal ,
- un quatrième commutateur connecté entre le deuxième noeud et le troisième noeud, commandé par 1 ' inverse du deuxième signal de commande, et la deuxième source de courant est connectée entre le troisième noeud et une deuxième tension d ' alimentation.- A fourth switch connected between the second node and the third node, controlled by the inverse of the second control signal, and the second current source is connected between the third node and a second supply voltage.
Selon un mode de réalisation de la présente invention, la première branche comprend un premier condensateur couplé au deuxième noeud.According to an embodiment of the present invention, the first branch comprises a first capacitor coupled to the second node.
Selon un mode de réalisation de la présente invention, la deuxième branche comprend un cinquième commutateur connecté entre le deuxième noeud et la sortie du moyen de commande.According to an embodiment of the present invention, the second branch comprises a fifth switch connected between the second node and the output of the control means.
Selon un mode de réalisation de la présente invention, la deuxième branche comprend un deuxième condensateur couplé au deuxième noeud par l'intermédiaire du cinquième commutateur.According to an embodiment of the present invention, the second branch comprises a second capacitor coupled to the second node via the fifth switch.
Selon un mode de réalisation de la présente invention, la deuxième source de courant est réalisée par un premier transistor, de type MOS, d'un premier type de conductivité. Selon un mode de réalisation de la présente invention, la première source de courant est réalisée par un deuxième transistor, d'un deuxième type de conductivité, et fait partie d'un miroir de courant, le courant traversant la première source de courant étant égal à α fois la valeur d'un courant de référence du miroir de courant, avec α supérieur à un.According to an embodiment of the present invention, the second current source is produced by a first transistor, of MOS type, of a first type of conductivity. According to an embodiment of the present invention, the first current source is produced by a second transistor, of a second type of conductivity, and is part of a current mirror, the current passing through the first current source being equal at α times the value of a reference current of the current mirror, with α greater than one.
Selon un mode de réalisation de la présente invention, le premier commutateur est formé d'un troisième transistor du deuxième type de conductivité, le deuxième commutateur est formé d'un quatrième transistor du deuxième type de conductivité, le troisième commutateur est formé d'un cinquième transistor du premier type de conductivité, et le quatrième commutateur est formé d'un sixième transistor du premier type de conductivité.According to an embodiment of the present invention, the first switch is formed of a third transistor of the second conductivity type, the second switch is formed of a fourth transistor of the second conductivity type, the third switch is formed of a fifth transistor of the first conductivity type, and the fourth switch is formed of a sixth transistor of the first conductivity type.
Selon un mode de réalisation de la présente invention, la première tension d'alimentation est une tension positive, la deuxième tension d'alimentation est la tension de la masse, et les transistors du premier type de conductivité sont des transistors MOS à canal N et les transistors du deuxième type de conductivité sont des transistors MOS à canal P. Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles : la figure 1 représente une boucle à verrouillage de phase classique comportant une pompe de charge ; les figures 2a à 2e représentent des chronogrammes illustrant le fonctionnement de la boucle à verrouillage de phase de la figure 1 et la figure 2f représente un chronogramme illustrant le fonctionnement d'une pompe de charge selonAccording to an embodiment of the present invention, the first supply voltage is a positive voltage, the second supply voltage is the ground voltage, and the transistors of the first conductivity type are N-channel MOS transistors and the transistors of the second type of conductivity are P-channel MOS transistors. These objects, characteristics and advantages, as well as others of the present invention, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: FIG. 1 represents a conventional phase-locked loop comprising a charge pump; Figures 2a to 2e represent timing diagrams illustrating the operation of the phase locked loop of Figure 1 and Figure 2f shows a timing diagram illustrating the operation of a charge pump according to
1 ' invention ; et la figure 3 représente un mode de réalisation particulier de la présente invention.The invention; and Figure 3 shows a particular embodiment of the present invention.
En figure 3, de mêmes références désignent de même éléments qu'en figures 1 et 2. La figure 3 représente un mode de réalisation d'une pompe de charge pour boucle à verrouillage de phase selon la présente invention. La pompe de charge est alimentée par une première tension d'alimentation VDD et une seconde tension d'alimentation VSS. Dans le mode de réalisation représenté, la tension VSS est la tension de la masse (0 volt) et la tension VDD est une tension positive par rapport à la masse.In FIG. 3, the same references designate the same elements as in FIGS. 1 and 2. FIG. 3 represents an embodiment of a charge pump for phase-locked loop according to the present invention. The charge pump is supplied by a first supply voltage VDD and a second supply voltage VSS. In the embodiment shown, the voltage VSS is the voltage of the ground (0 volts) and the voltage VDD is a positive voltage with respect to the ground.
La pompe de charge comprend une source de courant 14 disposée entre la tension d'alimentation VDD et un noeud A de la pompe de charge. La source de courant 14 fournit un courant de charge II, destiné à alimenter un filtre de boucle connecté en sortie de la pompe de charge lorsqu'un signal de commande U fourni par un comparateur de phase situé en amont de la pompe de charge est égal à 1. Dans le mode de réalisation représenté, la source de courant 14 comprend un transistor PMOS MPI, dont la source est reliée à la tension VDD et dont le drain est relié au noeud A. Le transistor MPI est traversé par le courant II . La grille du transistor MPI est reliée à la grille d'un transistor PMOS MP2. La source du transistor MP2 est reliée à la tension VDD. Le drain du transistor MP2 est connecté à la grille du transistor MP2. Le transistor MP2 est traversé par un courant de référence Iref. La source de courant 14 est donc réalisée à l'aide d'un miroir de courant. De manière avantageuse, le courant de référence Iref ne sera pas choisi égal à II, mais la géométrie des transistors MPI et MP2 sera choisie de sorte que le courant Il soit égal à α.Iref, avec α supérieur à 1. Ainsi, la consommation et la surface de la pompe de charge seront diminuées . Au noeud A, est connecté un premier couple de commutateurs, chaque commutateur étant formé d'un transistor PMOS, respectivement Ml et M2. Le transistor Ml a sa source connectée au noeud A et son drain connecté à la sortie OUT de la pompe de charge. La grille du transistor Ml est commandée par un signal U, correspondant à l'inverse du signal U fourni par le compara- teur de phase. Lorsque U est égal à "0" (U=l) , le transistor Ml est passant . Le transistor M2 a sa source reliée au noeud A et son drain relié à un noeud B de la pompe de charge. La grille du transistor M2 est commandée par le signal U issu du comparateur de phase . Le transistor M2 est passant lorsque le signal U est à un niveau bas (U=0) . Les signaux inverses U et U devront se recouvrir partiellement pour assurer une conduction continue de la source de courant 14.The charge pump comprises a current source 14 disposed between the supply voltage VDD and a node A of the charge pump. The current source 14 supplies a load current II, intended to supply a loop filter connected at the output of the charge pump when a control signal U supplied by a phase comparator situated upstream of the charge pump is equal to 1. In the embodiment shown, the current source 14 comprises a PMOS transistor MPI, the source of which is connected to the voltage VDD and the drain of which is connected to the node A. The transistor II is crossed by the current II. The gate of the MPI transistor is connected to the gate of a PMOS transistor MP2. The source of the transistor MP2 is connected to the voltage VDD. The drain of the transistor MP2 is connected to the gate of the transistor MP2. The transistor MP2 is crossed by a reference current Iref. The current source 14 is therefore produced using a current mirror. Advantageously, the reference current Iref will not be chosen equal to II, but the geometry of the transistors MPI and MP2 will be chosen so that the current Il is equal to α.Iref, with α greater than 1. Thus, the consumption and the surface of the charge pump will be reduced. At node A, a first pair of switches is connected, each switch being formed by a PMOS transistor, Ml and M2 respectively. The transistor M1 has its source connected to the node A and its drain connected to the output OUT of the charge pump. The gate of the transistor Ml is controlled by a signal U, corresponding to the inverse of the signal U provided by the comparator phase tor. When U is equal to "0" (U = l), the transistor Ml is conducting. The transistor M2 has its source connected to the node A and its drain connected to a node B of the charge pump. The gate of transistor M2 is controlled by the signal U from the phase comparator. The transistor M2 is on when the signal U is at a low level (U = 0). The reverse signals U and U must partially overlap to ensure continuous conduction of the current source 14.
Un deuxième couple de commutateurs, constitué de deux transistors M3 et M4, est connecté au noeud B et à la sortie OUT. Le transistor M3 est un transistor NMOS, dont le drain est connecté à la sortie OUT et la source à un noeud C de la pompe de charge. La grille du transistor M3 est commandée par la sortie D du comparateur de phase. Le transistor M3 est passant lorsque le signal D est à un niveau haut (D=l) . Le transistor M4 est un transistor NMOS, dont le drain est relié au noeud B et la source au noeud C. La grille du transistor M4 est commandée par un signal D , qui est l'inverse du signal D. Les signaux inverses D et devront se recouvrir partiellement pour assurer une conduction continue de la source de courant 14.A second pair of switches, consisting of two transistors M3 and M4, is connected to node B and to the output OUT. The transistor M3 is an NMOS transistor, the drain of which is connected to the output OUT and the source to a node C of the charge pump. The gate of transistor M3 is controlled by the output D of the phase comparator. The transistor M3 is on when the signal D is at a high level (D = 1). The transistor M4 is an NMOS transistor, the drain of which is connected to the node B and the source to the node C. The gate of the transistor M4 is controlled by a signal D, which is the inverse of the signal D. The inverse signals D and will partially overlap to ensure continuous conduction of the current source 14.
L'état des transistors Ml à M4 en fonction des valeurs de U et D peut être résumé dans les deux tableaux suivants :The state of the transistors Ml to M4 as a function of the values of U and D can be summarized in the following two tables:
Une source de courant 16 est disposée entre le noeud C et la deuxième tension d'alimentation VSS. La source de courant 16 est une source de courant commandable. Le courant 12 qui la traverse est fonction d'un signal de commande UC2 fourni à une borne de commande de la source 16.A current source 16 is disposed between the node C and the second supply voltage VSS. The current source 16 is a controllable current source. Current 12 which crosspiece is a function of a control signal UC2 supplied to a source control terminal 16.
Dans le mode de réalisation représenté, la source 16 est formée d'un transistor NMOS MN1, dont le drain est relié au noeud C et la source est reliée à la tension VSS. La grille du transistor MN1 reçoit le signal de commande UC2. Dans le mode de réalisation représenté, le signal de commande UC2 est un signal de tension. La tension UC2 correspond à la tension entre la grille et source du transistor MN1. Le transistor MN1 est tra- versé par le courant 12. Comme, dans un transistor MOS en régime saturé, la valeur du courant de drain est, au premier ordre, reliée de manière biunivoque à la valeur de la tension grille- source, le courant de décharge 12 dépend de la tension de commande UC2 de manière biunivoque. La borne de commande de la source de courant 16 est attaquée par un circuit de commande 18 fournissant la tension UC2. Dans le mode de réalisation représenté, le circuit 18 comprend une première branche formée d'un condensateur Cl connecté entre le noeud B et la tension d'alimentation VSS. Le circuit 18 comprend une deuxième branche, également connectée entre le noeud B et la tension d'alimentation VSS, comportant un commutateur S connecté en série avec un condensateur C2. Le commutateur S est relié entre le noeud B et la sortie du circuit 18 fournissant la tension UC2. Le condensateur C2 est connecté entre la sortie du circuit 18 et la deuxième tension d'alimentation VSS. Le commutateur S est commandé par un signal AZ. L'interrupteur S est ouvert (noeud B isolé de la sortie du circuit 18) lorsque le signal AZ est égal à 1. L'interrupteur S est fermé (noeud B en communication avec la sortie du circuit 18) lorsque le signal AZ est égal à 0.In the embodiment shown, the source 16 is formed of an NMOS transistor MN1, the drain of which is connected to the node C and the source of which is connected to the voltage VSS. The gate of transistor MN1 receives the control signal UC2. In the embodiment shown, the control signal UC2 is a voltage signal. The voltage UC2 corresponds to the voltage between the gate and source of the transistor MN1. The transistor MN1 is traversed by the current 12. As, in a MOS transistor in saturated regime, the value of the drain current is, in the first order, unequivocally linked to the value of the gate-source voltage, the current discharge 12 depends on the control voltage UC2 unequivocally. The control terminal of the current source 16 is attacked by a control circuit 18 supplying the voltage UC2. In the embodiment shown, the circuit 18 comprises a first branch formed by a capacitor C1 connected between the node B and the supply voltage VSS. The circuit 18 comprises a second branch, also connected between the node B and the supply voltage VSS, comprising a switch S connected in series with a capacitor C2. The switch S is connected between the node B and the output of the circuit 18 supplying the voltage UC2. The capacitor C2 is connected between the output of the circuit 18 and the second supply voltage VSS. Switch S is controlled by an AZ signal. The switch S is open (node B isolated from the output of circuit 18) when the signal AZ is equal to 1. The switch S is closed (node B in communication with the output of circuit 18) when the signal AZ is equal at 0.
Pour expliquer le fonctionnement de la pompe de charge selon la présente invention, on se reportera aux chronogrammes de la figure 2, dans lesquels, outre les signaux utilisés pour expliquer le fonctionnement de la pompe de charge de l'art anté- rieur, le signal AZ est représenté (figure 2f) . Dans une première phase, allant jusqu'à l'instant tO, on a U = D = 0. Le signal AZ aussi est égal à 0. Les seuls transistors passants des couples de commutateurs sont les transistors M2 et M4. L ' interrupteur S est fermé et le noeud B est en communication avec la sortie du circuit 18. Les transistors Ml et M3 étant bloqués, aucun courant ne transite par la sortie OUT. Le courant II arrivant au noeud A traverse le transistor M2 et parvient au noeud B. Dans un premier temps, une partie du courant II sert à charger le condensateur Cl et, par l'intermédiaire du commutateur S fermé, le condensateur C2. La partie du courant II qui n'a pas servi à charger les condensateurs Cl et C2 traverse le transistor M4 et le transistor MN1. A l'équilibre, les condensateurs Cl et C2 sont chargés et n'absorbent aucun courant. Par conséquent, le courant II fourni par la source de courant 14 traverse totalement la source de courant 16, et, de ce fait, la source de courant 16 est parcourue par un courant 12 rigoureusement égal au courant II. Ce dernier point est particulièrement important. En effet, dans l'art antérieur, même si l'on essaye de faire en sorte que les sources de courant 6A et 6B soient identiques, les dispersions technologiques font, comme on l'a vu, que le courant Il n'est jamais rigoureusement égal à 12.To explain the operation of the charge pump according to the present invention, reference will be made to the timing diagrams of FIG. 2, in which, in addition to the signals used to explain the operation of the charge pump of the prior art, the signal AZ is shown (Figure 2f). In a first phase, going up to time t0, we have U = D = 0. The signal AZ also is equal to 0. The only transistors passing through the pairs of switches are the transistors M2 and M4. The switch S is closed and the node B is in communication with the output of the circuit 18. The transistors Ml and M3 being blocked, no current flows through the output OUT. The current II arriving at the node A crosses the transistor M2 and arrives at the node B. Firstly, part of the current II is used to charge the capacitor Cl and, by means of the closed switch S, the capacitor C2. The part of the current II which has not been used to charge the capacitors Cl and C2 passes through the transistor M4 and the transistor MN1. At equilibrium, the capacitors C1 and C2 are charged and do not absorb any current. Consequently, the current II supplied by the current source 14 passes completely through the current source 16, and, therefore, the current source 16 is traversed by a current 12 strictly equal to the current II. This last point is particularly important. Indeed, in the prior art, even if we try to ensure that the current sources 6A and 6B are identical, the technological dispersions cause, as we have seen, that the current It is never strictly equal to 12.
A l'instant tO, peu avant l'arrivée du front montant du signal Fdiv à 1 ' instant tl (on rappelle que la figure 2 se place dans le cas où le signal Fdiv est en avance sur le signalAt time t0, shortly before the rising edge of signal Fdiv arrives at time tl (it should be recalled that FIG. 2 takes place in the case where the signal Fdiv is ahead of the signal
Fcomp, mais le raisonnement est semblable et se déduit facilement dans le cas où le signal Fcomp est en avance sur le signal Fdiv) , le signal AZ passe à "1" et le commutateur S s'ouvre. L'ouverture du commutateur S a pour effet d'isoler la capacité C2 du noeud B. La capacité C2 présente à ses bornes une tension UC2, qui va rester constante car la grille du transistor MN1 n'absorbe pas de courant. La tension UC2 restant constante, le courant 12 traversant la source de courant 16 va rester constant et rigoureusement égal à la valeur du courant II à l'instant to. Le circuit 18 agit donc comme un moyen de mémorisation de la valeur du courant II avant fermeture d'un des transistors Ml et M3. De préférence, l'instant to sera choisi aussi proche que possible de l'instant tl, pour que la mémorisation du courant II porte sur une valeur de II aussi proche que possible de 1 ' instant où la pompe de charge est en communication avec le filtre de boucle. On rappelle que, bien que le courant II soit en principe un courant constant, le courant II est affecté par du bruit. Le courant II est ainsi soumis à des variations, faibles, certes, mais introduisant du bruit en sortie de la boucle à verrouillage de phase lorsque la pompe de charge est en communication avec le filtre de boucle .Fcomp, but the reasoning is similar and is easily deduced in the case where the signal Fcomp is ahead of the signal Fdiv), the signal AZ goes to "1" and the switch S opens. The opening of the switch S has the effect of isolating the capacitor C2 from the node B. The capacitor C2 has a voltage UC2 at its terminals, which will remain constant because the gate of the transistor MN1 does not absorb current. The voltage UC2 remaining constant, the current 12 passing through the current source 16 will remain constant and strictly equal to the value of the current II at the instant to. Circuit 18 therefore acts as a means of memorization of the value of the current II before closing of one of the transistors Ml and M3. Preferably, the instant to be chosen as close as possible to the instant tl, so that the memorization of the current II relates to a value of II as close as possible to the instant when the charge pump is in communication with the loop filter. It will be recalled that, although current II is in principle a constant current, current II is affected by noise. Current II is thus subjected to variations, small, of course, but introducing noise at the output of the phase locked loop when the charge pump is in communication with the loop filter.
On notera ici que le condensateur C2 peut être omis. En effet, la valeur de ce condensateur est faible, typiquement de l'ordre de 5 picofarads. Si le transistor MN1 est réalisé pour que sa capacité parasite grille-source soit suffisante, par exemple à l'aide d'un transistor de dimensions suffisantes, la capacité parasite du transistor MN1 peut servir de condensateur C2 et ce dernier peut être supprimé.It will be noted here that the capacitor C2 can be omitted. Indeed, the value of this capacitor is low, typically of the order of 5 picofarads. If the transistor MN1 is produced so that its parasitic gate-source capacitance is sufficient, for example using a transistor of sufficient dimensions, the parasitic capacitance of the transistor MN1 can serve as capacitor C2 and the latter can be eliminated.
A l'instant tl, le signal U passe à "1". Cela a pour effet de rendre passant le transistor Ml et de bloquer le transistor M2. Le courant II parvenant au noeud A est alors dirigé vers la sortie OUT et injecté dans le filtre de boucle pour diminuer 1 'écart de phase entre les signaux Fdiv et Fcomp . Entre les instants tl et t2, le signal D reste égal à "0". Le transistor M3 reste donc bloqué, et le transistor M4 reste passant . Le courant 12 traversant la source de courant 16 est fourni par le condensateur Cl, qui se décharge à courant constant par les transistors M4 et MN1. La valeur de la tension UC2 ne varie pas de manière sensible entre les instants tl et t2, et le courant 12, entre les instants tl et t2, reste égal à la valeur du courant II à 1 ' instant tO . La capacité du condensateur Cl est choisie suffisamment grande pour pouvoir fournir le courant 12 pendant une durée suffisante correspondant à 1 ' écart de phase entre Fdiv et Fcomp . Une valeur typique de la capacité du condensateur Cl est de 30 picofarads environ. A l'instant t2, le signal D passe à "1", les signaux U et AZ restant à "1". Alors, le transistor M3 devient passant et le transistor M4 se bloque. La source de courant 16 est alors en liaison avec la sortie OUT, et le courant transitant par la sor- tie OUT est égal au courant II fourni par la source 14 à l'instant t2 diminué du courant 12, égal, rappelons-le, au courant II fourni par la source 14 à 1 ' instant tO . Comme 1 ' intervalle de temps entre t2 et tO est faible, la valeur du courant II a peu varié entre ces deux instants. De fait, on peut considérer que la source de II est affectée d'un bruit que l'on peut décomposer en un bruit basse fréquence et un bruit haute fréquence. Entre les instants tO et t2, seul le bruit haute fréquence du courant Il a varié. Le bruit basse fréquence ayant été mémorisé à l'instant tO par le courant 12, le courant fourni en sortie OUT est exempt du bruit basse fréquence affectant la source II, ce qui représente un avantage considérable par rapport à 1 ' art antérieur. Plus l'instant tO est proche de l'instant tl, meilleure est 1 ' élimination du bruit et plus faible est le courant résiduel transitant par la sortie OUT. Ainsi, il sera avantageux de faire s'ouvrir le commutateur S aussi près possible de 1 ' instant tl .At time tl, the signal U goes to "1". This has the effect of turning on the transistor Ml and blocking the transistor M2. Current II arriving at node A is then directed to output OUT and injected into the loop filter to reduce the phase difference between the signals Fdiv and Fcomp. Between times tl and t2, the signal D remains equal to "0". The transistor M3 therefore remains blocked, and the transistor M4 remains on. The current 12 passing through the current source 16 is supplied by the capacitor C1, which is discharged at constant current by the transistors M4 and MN1. The value of the voltage UC2 does not vary appreciably between the instants tl and t2, and the current 12, between the instants tl and t2, remains equal to the value of the current II at the instant t0. The capacity of the capacitor C1 is chosen to be large enough to be able to supply the current 12 for a sufficient duration corresponding to the phase difference between Fdiv and Fcomp. A typical value of the capacitor Cl is about 30 picofarads. At time t2, the signal D goes to "1", the signals U and AZ remaining at "1". Then, the transistor M3 turns on and the transistor M4 is blocked. The current source 16 is then in connection with the output OUT, and the current flowing through the output OUT is equal to the current II supplied by the source 14 at the time t2 minus the current 12, equal, remember, at the current II supplied by the source 14 at the instant t0. As the time interval between t2 and t0 is small, the value of the current II varied little between these two instants. In fact, it can be considered that the source of II is affected by noise which can be broken down into low frequency noise and high frequency noise. Between the instants t0 and t2, only the high frequency noise of the current Il varied. The low frequency noise having been memorized at the instant t0 by the current 12, the current supplied at the output OUT is free from the low frequency noise affecting the source II, which represents a considerable advantage compared to one prior art. The closer the instant t0 to the instant tl, the better the noise elimination and the lower the residual current flowing through the output OUT. Thus, it will be advantageous to make the switch S open as close as possible to the instant t1.
A 1 ' instant t3, les signaux U et D passent tous deux à "0", le signal AZ restant à "1". Dans ce cas, les transistors Ml et M3 se bloquent et les transistors M2 et M4 deviennent pas- sants. Le courant II parvenant en A est dirigé vers le noeud B.At time t3, the signals U and D both pass to "0", the signal AZ remaining to "1". In this case, the transistors M1 and M3 are blocked and the transistors M2 and M4 become on. Current II arriving at A is directed towards node B.
La capacité Cl s 'étant déchargée pendant l'étape tl-t2, pour retrouver l'équilibre, une partie du courant II va servir à la recharger.The capacity Cl s being discharged during step tl-t2, to regain equilibrium, part of the current II will be used to recharge it.
A l'instant t4, le signal AZ passe à "1" et le commutateur S se ferme. On retrouve alors la situation précédant l'instant tO, les signaux U, D et AZ étant tous égaux à "0". Lorsque l'équilibre est atteint, les condensateurs Cl et C2 sont chargés, et le courant 12 est rigoureusement égal au courant II. L ' instant t4 est choisi de sorte que les commutateurs du premier et du deuxième couple de commutateurs aient eu le temps de commuter . L ' instant t4 peut être choisi dans une plage de temps relativement importante .At time t4, the signal AZ goes to "1" and the switch S closes. We then find the situation preceding the instant t0, the signals U, D and AZ all being equal to "0". When equilibrium is reached, the capacitors C1 and C2 are charged, and the current 12 is strictly equal to the current II. The instant t4 is chosen so that the switches of the first and of the second pair of switches have had time to switch. The instant t4 can be chosen within a relatively long time range.
Lorsque la boucle est stabilisée (après l'instant t'O), seul le bruit haute fréquence affectant les sources de courant 14 et 16 est transmis pendant la durée t'3-t'l.When the loop is stabilized (after the instant t'O), only the high frequency noise affecting the current sources 14 and 16 is transmitted for the duration t'3-t'l.
Ainsi, dans la présente invention, le circuit 18 est un circuit de commande de la source de courant 16, qui assure que le courant 12 traversant la source de courant 16 suit les variations du courant II traversant la source de courant 14. Avant que la pompe de charge ne délivre du courant sur sa sortie OUT, le moyen 18 mémorise la valeur du courant II et, lorsque les deux sources de courant 14 et 16 sont en communication avec la sortie OUT, la valeur du courant 12 fourni par la source de courant 16 est égale à la valeur mémorisée du courant II. Par rapport à l'art antérieur, cela permet d'une part une réduction du courant résiduel 11-12 fourni en sortie de la pompe de charge lorsque chacune des sources est en communication avec le filtre de boucle, et d'autre part une suppression du bruit basse fréquence dans le courant fourni par la pompe de charge. Un autre avantage de la pompe de charge selon la présente invention est qu'elle est facilement intégrable. Elle peut utiliser des transistors plus petits et consomme moins que dans 1 ' art antérieur . Pour avoir un bon appairage sur les miroirs de courant et pour avoir un faible bruit basse fréquence, il faut classiquement prévoir de gros transistors. Comme, selon l'invention, on réalise une mémorisation et que de ce fait on supprime le bruit basse fréquence et l'écart 11-12, on peut utiliser des transistors MPI, MP2 et MN1 plus petits que dans l'art antérieur. De plus, classiquement, pour diminuer le bruit basse fréquence dans la boucle, on augmente le courant des sources II et 12 (le bruit d'un transistor MOS augmente en VI mais le gain de ce bruit vers la sortie est en l/l) . Comme le bruit basse fréquence est supprimé, on peut diminuer la valeur du courant. Le facteur Iref-Il est également une raison de la baisse de consommation. Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaîtront à l'homme de 1 ' art .Thus, in the present invention, the circuit 18 is a circuit for controlling the current source 16, which ensures that the current 12 passing through the current source 16 follows the variations of the current II passing through the current source 14. Before the charge pump does not deliver current to its output OUT, the means 18 stores the value of current II and, when the two current sources 14 and 16 are in communication with the output OUT, the value of current 12 supplied by the source of current 16 is equal to the memorized value of current II. Compared to the prior art, this allows on the one hand a reduction in the residual current 11-12 supplied at the output of the charge pump when each of the sources is in communication with the loop filter, and on the other hand a suppression low frequency noise in the current supplied by the charge pump. Another advantage of the charge pump according to the present invention is that it is easily integrated. It can use smaller transistors and consumes less than in the prior art. To have a good pairing on the current mirrors and to have a low low frequency noise, it is conventionally necessary to provide large transistors. As, according to the invention, a storage is carried out and therefore the low frequency noise and the difference 11-12 are eliminated, it is possible to use transistors MPI, MP2 and MN1 which are smaller than in the prior art. In addition, conventionally, to reduce the low frequency noise in the loop, the current of sources II and 12 is increased (the noise of a MOS transistor increases in VI but the gain of this noise towards the output is in l / l) . As the low frequency noise is suppressed, the current value can be reduced. The Iref-Il factor is also a reason for the drop in consumption. Of course, the present invention is susceptible to various variants and modifications which will appear to those skilled in the art.
On a décrit le cas où la tension VDD était une tension d'alimentation positive et la tension VSS une tension d'alimentation égale à 0 (tension de la masse) . Bien entendu, la tension VSS peut être différente, par exemple négative par rapport à la masse du circuit. Aussi, les polarités des tensions VDD et VSS peuvent être inversées. Dans ce cas, les transistors de type N seront remplacés par des transistors de type P, et vice versa.We have described the case where the voltage VDD was a positive supply voltage and the voltage VSS a supply voltage equal to 0 (ground voltage). Of course, the voltage VSS can be different, for example negative with respect to the ground of the circuit. Also, the polarities of the VDD and VSS voltages can be reversed. In this case, the N type transistors will be replaced by P type transistors, and vice versa.
Également, les transistors MOS du mode de réalisation décrit peuvent être remplacés par des transistors bipolaires si cela est souhaité, mais, dans ce cas, la source de courant 16 devra être réalisée de sorte qu'elle ne prenne qu'un courant négligeable sur sa borne de commande, afin que la tension sur sa borne de commande, si la source de courant 16 est commandée en tension, reste à une valeur constante.Also, the MOS transistors of the embodiment described can be replaced by bipolar transistors if desired, but, in this case, the current source 16 must be produced so that it takes only a negligible current on its control terminal, so that the voltage on its control terminal, if the current source 16 is voltage controlled, remains at a constant value.
Enfin, le commutateur S n'a pas été décrit de manière spécifique. Bien entendu, il peut s'agir de tout dispositif commutateur approprié, par exemple d'un transistor MOS connecté et commandé de manière appropriée. Finally, the switch S has not been specifically described. Of course, it can be any suitable switching device, for example an MOS transistor connected and controlled appropriately.

Claims

REVENDICATIONS
1. Pompe de charge pour boucle à verrouillage de phase comportant une première source de courant (14) , une deuxième source de courant (16) , plusieurs commutateurs (Ml, M2, M3, M4) propres à mettre en communication la première et/ou la deuxième source de courant avec la sortie (OUT) de la pompe de charge, caractérisée en ce que la deuxième source de courant est commandée par un moyen de commande (18) propre à mémoriser une grandeur correspondant à la valeur du courant (II) fourni par la première source de courant (14) , de sorte que la valeur du courant (12) fourni par la deuxième source de courant est sensiblement égale à la valeur du courant (II) fourni par la première source de courant, le moyen de commande (18) comprenant une première branche comportant un premier moyen de mémorisation (Cl) et une deuxième branche comportant un deuxième moyen de mémorisation (C2) .1. Charge pump for phase-locked loop comprising a first current source (14), a second current source (16), several switches (Ml, M2, M3, M4) suitable for establishing communication between the first and / or the second current source with the output (OUT) of the charge pump, characterized in that the second current source is controlled by a control means (18) capable of storing a quantity corresponding to the value of the current (II ) supplied by the first current source (14), so that the value of the current (12) supplied by the second current source is substantially equal to the value of the current (II) supplied by the first current source, the means control (18) comprising a first branch comprising a first storage means (C1) and a second branch comprising a second storage means (C2).
2. Pompe de charge selon la revendication 1, dans laquelle le moyen de commande (18) mémorise ladite grandeur peu avant la mise en communication de la première et/ou de la seconde source de courant avec la sortie (OUT) de la pompe de charge .2. A charge pump according to claim 1, in which the control means (18) stores said quantity shortly before the first and / or second current source is put into communication with the output (OUT) of the pump. charge .
3. Pompe de charge selon la revendication 1 ou 2, dans laquelle la première source de courant (14) est connectée entre une première tension d'alimentation (VDD) et un premier noeud (A) , et dans laquelle les commutateurs comprennent : - un premier commutateur (Ml) connecté entre le premier noeud (A) et la sortie (OUT) de la pompe de charge, commandé par un premier signal de commande (U) , un deuxième commutateur (M2) connecté entre le premier noeud (A) et un deuxième noeud (B) , commandé par l'inverse (U) du premier signal de commande,3. Charge pump according to claim 1 or 2, in which the first current source (14) is connected between a first supply voltage (VDD) and a first node (A), and in which the switches comprise: - a first switch (Ml) connected between the first node (A) and the output (OUT) of the charge pump, controlled by a first control signal (U), a second switch (M2) connected between the first node (A ) and a second node (B), controlled by the inverse (U) of the first control signal,
- un troisième commutateur (M3) connecté entre la sortie (OUT) de la pompe de charge et un troisième noeud (C) , commandé par un deuxième signal de commande (D) , - un quatrième commutateur (M4) connecté entre le noeud (B) et le troisième noeud (C) , commandé par l'inverse (D) du deuxième signal de commande (D) , et dans laquelle la deuxième source de courant (16) est connectée entre le troisième noeud (C) et une deuxième tension d'alimentation (VSS) .- a third switch (M3) connected between the output (OUT) of the charge pump and a third node (C), controlled by a second control signal (D), - a fourth switch (M4) connected between the node (B) and the third node (C), controlled by the inverse (D) of the second control signal (D), and in which the second current source (16) is connected between the third node (C) and a second supply voltage (VSS).
4. Pompe de charge selon la revendication 1, dans laquelle la première branche comprend un premier condensateur (Cl) couplé au deuxième noeud (B) . 4. Charge pump according to claim 1, in which the first branch comprises a first capacitor (Cl) coupled to the second node (B).
5. Pompe de charge selon la revendication 1, dans laquelle la deuxième branche comprend un cinquième commutateur (S) connecté entre le deuxième noeud (B) et la sortie du moyen de commande5. A charge pump according to claim 1, in which the second branch comprises a fifth switch (S) connected between the second node (B) and the output of the control means
6. Pompe de charge selon la revendication 5, dans laquelle la deuxième branche comprend un deuxième condensateur6. Charge pump according to claim 5, in which the second branch comprises a second capacitor
(C2) couplé au deuxième noeud (B) par l'intermédiaire du cinquième commutateur (S) .(C2) coupled to the second node (B) via the fifth switch (S).
7. Pompe de charge selon l'une quelconque des revendications 1 à 6, dans laquelle la deuxième source de courant (16) est réalisée par un premier transistor (MN1) , de type MOS, d'un premier type de conductivité.7. Charge pump according to any one of claims 1 to 6, in which the second current source (16) is produced by a first transistor (MN1), of MOS type, of a first type of conductivity.
8. Pompe de charge selon l'une quelconque des revendications 1 à 7, dans laquelle la première source de courant (14) est réalisée par un deuxième transistor (MPI), d'un deuxième type de conductivité, et fait partie d'un miroir de courant, le courant (II) traversant la première source de courant étant égal à α fois la valeur d'un courant de référence (Iref) du miroir de courant, avec α supérieur à un.8. Charge pump according to any one of claims 1 to 7, in which the first current source (14) is produced by a second transistor (MPI), of a second type of conductivity, and is part of a current mirror, the current (II) passing through the first current source being equal to α times the value of a reference current (Iref) of the current mirror, with α greater than one.
9. Pompe de charge selon l'une des revendications 3 à 8, dans laquelle le premier commutateur est formé d'un troisième transistor (Ml) du deuxième type de conductivité, le deuxième commutateur est formé d'un quatrième transistor (M2) du deuxième type de conductivité, le troisième commutateur est formé d'un cinquième transistor (M3) du premier type de conductivité, et le quatrième commutateur est formé d'un sixième transistor (M4) du premier type de conductivité.9. Charge pump according to one of claims 3 to 8, in which the first switch is formed of a third transistor (MI) of the second type of conductivity, the second switch is formed of a fourth transistor (M2) of the second type of conductivity, the third switch is formed by a fifth transistor (M3) of the first type of conductivity, and the fourth switch is formed by a sixth transistor (M4) of the first type of conductivity.
10. Pompe de charge selon l'une des revendications 3 à 9, dans laquelle la première tension d'alimentation (VDD) est une tension positive, la deuxième tension d'alimentation (VSS) est la tension de la masse, et les transistors du premier type de conductivité sont des transistors MOS à canal N et les transistors du deuxième type de conductivité sont des transistors MOS à canal P. 10. Charge pump according to one of claims 3 to 9, in which the first supply voltage (VDD) is a positive voltage, the second supply voltage (VSS) is the ground voltage, and the transistors of the first conductivity type are N-channel MOS transistors and the transistors of the second conductivity type are P-channel MOS transistors
EP01990618A 2000-12-29 2001-12-28 Low-noise load pump for phase-locking loop Withdrawn EP1371139A2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0017293A FR2819123B1 (en) 2000-12-29 2000-12-29 LOW NOISE CHARGING PUMP FOR PHASE LOCKED LOOP
FR0017293 2000-12-29
PCT/FR2001/004224 WO2002054597A2 (en) 2000-12-29 2001-12-28 Low-noise load pump for phase-locking loop

Publications (1)

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EP1371139A2 true EP1371139A2 (en) 2003-12-17

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EP01990618A Withdrawn EP1371139A2 (en) 2000-12-29 2001-12-28 Low-noise load pump for phase-locking loop

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US (1) US6822520B2 (en)
EP (1) EP1371139A2 (en)
JP (1) JP2004517544A (en)
FR (1) FR2819123B1 (en)
WO (1) WO2002054597A2 (en)

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GB2410387B (en) * 2004-01-23 2006-06-21 Zarlink Semiconductor Ab PLL phase/frequency detector with fully differential output charge pump
JP2010103707A (en) * 2008-10-22 2010-05-06 Canon Inc Charge pumping circuit and clock generator
US8766683B2 (en) * 2012-08-17 2014-07-01 St-Ericsson Sa Double output linearized low-noise charge pump with loop filter area reduction

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EP0647032A3 (en) * 1993-10-05 1995-07-26 Ibm Charge pump circuit with symmetrical current output for phase-controlled loop system.
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Publication number Publication date
JP2004517544A (en) 2004-06-10
US6822520B2 (en) 2004-11-23
WO2002054597A2 (en) 2002-07-11
US20030062958A1 (en) 2003-04-03
FR2819123B1 (en) 2003-04-11
FR2819123A1 (en) 2002-07-05
WO2002054597A3 (en) 2003-03-13

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