EP1364449A1 - Circuit design for a circuit for switching currents - Google Patents

Abstract

The invention relates to a circuit design for a circuit for switching currents, comprising at least one switch element (T1...Tn, T1'...Tn'), and at least one respective main current conductor (D, S, A) for interlinking the switch element, the poles (V+, GND) of a current source and an energy accumulator (C). The aim of the invention is to reduce ohmic resistance and inductive resistance of such a circuit. To this end, an ancillary current conductor (D1, S1, A1) that has a lower current carrying capacity than the main current conductor is connected in parallel to at least one of the main current conductors (D, S, A).

Description

       

  



  Description: Circuit structure for a circuit for switching currents The invention relates to a circuit structure for a circuit for switching currents, in particular a converter as a DC / DC converter or inverter for alternating current or three-phase current.



  The circuit structure for switching large currents - for example in the case of a converter - in a confined space, at low cost and with high mass production, is particularly critical.



  For this purpose, an arrangement of discrete power semiconductors (switching transistors) with power lines of high current carrying capacity and cooling of the power semiconductors, for example by means of a water cooler, is required.



  When switching the power semiconductors quickly, a low-resistance and low-inductance connection of the components is important. However, this is only possible with simple arrangements of intermediate circuit capacitors and power semiconductors.



  If additional components, for example gate resistors, are required, a low-inductance connection of the power semiconductors to the intermediate circuit capacitors can no longer be guaranteed in all cases, since the resistors "cut" the current-carrying copper surfaces and thus increase their resistance and inductance.



  As the leakage inductances increase, the overvoltage occurring on the power semiconductors increases. At the same time, the energy stored in the leakage inductors is converted into heat. The greater the currents to be switched, the greater this heat, since the energy increases with the square of the current. With large currents, the leakage inductances must therefore be minimized, otherwise the power semiconductors can be destroyed. However, this also applies, to scale, to circuits in which lower currents flow.



  The invention has for its object to provide a circuit structure for switching currents which can be mass-produced in a confined space and at low cost and which enables both low-inductance and low-impedance connection of the power semiconductors to an intermediate circuit and a low-impedance connection to one or more intermediate circuit capacitors.



  This object is achieved by a circuit structure with the features of claim 1. Advantageous embodiments of the invention can be found in the subclaims.



  When using "thick" current conductors with high current carrying capacity (designed for the current strength of the load current), called main current conductors, which are low-resistance but more inductive, according to the invention, at least one of these main current conductors is called a further, "thin" current conductor, secondary current conductor, with lower current carrying capacity than the main current conductor, which is low-inductance but has a higher resistance, connected in parallel.



  Both goals, namely "low-resistance" and "low-inductance", are achieved separately. In the switching moment, the higher-resistance, but low-inductance connection acts first, and then, with delay, the low-resistance, higher-inductance connection.



  With this measure, the inductance and ohmic resistance of the current conductor arrangement (main and secondary current conductors connected in parallel) are reduced, the transient switch-off process of the power semiconductors is shortened, and the energy converted in the power semiconductors during the switch-off process is also reduced - the power loss is reduced reduced - and the heat is better distributed over the entire switching cycle.



  Two exemplary embodiments of the invention are explained in more detail below with the aid of a schematic drawing. FIG. 1 shows a known circuit for controlling a load by means of a switching element, FIG. 2 shows a known circuit structure for this, FIG. 3 shows a known circuit of a converter, FIG. 4a shows a first exemplary embodiment of a circuit construction for the converter according to FIG. 3, FIG. 4b shows a cross section 5a shows a second exemplary embodiment of a circuit structure for the converter according to FIG. 3, and FIG. 5b shows a cross section through the associated printed circuit board.



  If a current conductor is mentioned in the following, this can be a lead wire, a printed circuit board, a lead frame, a bus bar or the like. In the following exemplary embodiments, for the sake of simplicity, the current conductors are to be designed, for example, as circuit boards known per se (current conducting layers applied to an electrically insulating carrier material).



  FIG. 1 shows a known circuit for driving a load L, which, with a switching element T, usually a power semiconductor designed as a bipolar transistor or MOSFET, is connected in series to the poles V + and GND of an energy source. If the switching element is switched in rapid succession, an intermediate circuit capacitor C in parallel with the series connection of switching element T and load L is required.



  The current conductors through which the elements T, L and C are connected to one another and to the energy source are denoted by D, A, S and G. Via the current conductor G, the gate connection g receives its control signal for switching the switching element T on and off.



  FIG. 2 shows a known circuit structure of the circuit according to FIG. 1 on a multiple circuit board shown in cross section. The circuit board consists of two thick outer layers, an upper outer layer D and a lower outer layer, on which two electrically separate main current conductors S and A are arranged. In between is a thin inner layer G, which is electrically separated from the outer layers by non-conductive insulating plates I1 and I2.



  Connected electrically conductive surfaces are hatched and outlined in thick lines. They may be interrupted by non-hatched holes for the passage of connecting wires. Larger electrically non-conductive areas are also not hatched. The multiple circuit board is not drawn to scale. The layer thicknesses are, for example: D, S, A = 400um, G = 35um and I1, 12 = 1mm. The thin inner layer G is used here exclusively for supplying the control signal to the gate connection g of the switching element T.



  , FIG. 3 shows a partial circuit diagram of a known converter, for example in an integrated starter / generator (ISG) of a motor vehicle, namely a phase of an inverter for generating three-phase current from direct current. This circuit can also work as a DC / DC converter, for example.



  The circuit consists of a half bridge of circuit breakers, namely the series connection of a high-side switch T1 and a low-side switch T1 ', which is connected to an energy source with the poles V + and GND. Further half-bridges T2-T2 '... Tn-Tn' of this type are connected in parallel to switch high currents.



  The drain connections dl to dn of all highside switches T1 to
Tn are connected to one another and to the positive pole V + of the energy source via a first main current conductor D; the source connections sl'bis sn'all low side switches T1 'to Tn' are connected to one another and to the negative pole GND of the energy source via a second main current conductor S; the interconnected source connections sl to sn all
Highside switches T1 to Tn and drain connections dl'bis dn'all lowside switches T1'bis Tn's are connected to one another via a third main current conductor A; the gate connections gl to gn of all highside switches T1 to
Tn are connected to one another via a first further current conductor Gl, called the control current conductor;

   the gate connections gl'bis gn'all lowside switches T1'bis
Tn's are connected to each other via a second control current conductor G2; between the main current conductors D and S is at least one
DC link capacitor C is arranged, and the load lies between the main current conductors A and S.



  If the highside switches T1 to Tn are alternately controlled with the low-side switches T1'to Tn'conducting, the direct voltage which is present between the first and the second main current conductors D and S becomes an alternating voltage which is between the third and second main current conductors A and S can be tapped.



  If three such phase circuits are used and controlled accordingly, three-phase current / voltage can be tapped at their three outputs.



  According to a first exemplary embodiment, the circuit according to FIG. 3 is constructed on a multilayer printed circuit board, which is shown schematically in FIG. 4b in section and in FIG. 4a together with the components arranged on it in a top view.



  The multilayer printed circuit board according to FIG. 4b consists of four electrically conductive, mutually insulated layers, for example made of copper, the first (top) layer carrying the first main current conductor D and the fourth (bottom) layer on which the second and third main current conductors are located S and A are located, each take up the load current and therefore have a sufficient layer thickness, for example 400 μm. The second and third layers have a layer thickness of, for example, 35 μm. This will be discussed later.



  FIG. 4a shows a top view of the three main current conductors A, D and S arranged on the first and fourth layers without the second and third layers and without the intervening insulating layers, together with the components arranged thereon, the highside and low-side switches T1 to Tn, T1'bis Tn ', an intermediate circuit capacitor C and the load L.



  The high-side switches Tl ... Tn and the low-side switches Tl '... Tn' each form a row, the two rows lying opposite one another in such a way that the connections of the circuit breakers are arranged in two rows, interlocked with one another, and that their interconnected connections sl-dl '... sn-dn' are next to each other.



  For this purpose, the connections of the high-side and low-side switches are bent in such a way that the outer connections (source connection s and gate connection g) are bent at a short distance from the semiconductor housing and the middle connection (drain connection d) is bent at a greater distance from the semiconductor housing that the housing can be arranged lying on the multilayer circuit board.



  With the same dimensions as the first main current conductor D in the first layer (400um) and exactly below it in the second layer (35um) a first bypass conductor D1 is arranged, the through-connections of the connections of the components connected to the first main current conductor D for first secondary current conductor D1, both current conductors D and D1 are connected in parallel with one another.



  Likewise, a second and a third secondary current conductor S1 and AI are arranged above the two main current conductors S and A arranged in the fourth layer (400um) and just above them in the third layer (35um), the through-plating of the connections connecting the second and the second third main current conductors S and A connected components, the current conductors S with S1 and A with AI are connected in parallel to one another.



  These parallel connections of a “thick” main and a “thin” secondary conductor D-D1, S-S1 and A-A1 are indicated in FIG. 3 by thick and thin parallel lines representing the conductor and can also be seen in FIG. 4b.



  In this first exemplary embodiment, the parallel current conductors D-DI are arranged above the parallel current conductors S-S1.



  As a result of these measures, the inductance and ohmic resistance of the current conductor arrangements D-D1, S-S1 and A-Al, which are designed as printed circuit boards in this exemplary embodiment, are also reduced to one or more intermediate circuit capacitors C and to the load L, as already explained above ,



  The first and second control current conductors G1 and G2, which connect the gate connections of the highside and lowside switches to control circuits, not shown, and which are not shown in FIG. 4a, are arranged on the part of the second, thin layer which is not from the first secondary current conductor Dl is occupied. For these control signals, only thin current conductors are required, which can also be passed between the connections of the circuit breakers (in contrast to the main current conductors D, S and A carrying high currents).



  The control current conductors G1 and G2 could, however, also be arranged on the first, thick layer, insofar as this is not occupied by the main current conductor D, or distributed over this and the second, thin layer below.



  In a second exemplary embodiment, a multilayer printed circuit board is also used, which corresponds to the structure of the printed circuit board according to FIG. 4b, but with a different division. The highside and lowside switches are again opposite one another, but their connections are not interlocked. This arrangement makes the connection to the intermediate circuit capacitors less inductive, and thus further improved.



  The multilayer printed circuit board is shown schematically in FIG. 5b in section and in FIG. 5a together with the components arranged on it in plan view.



  The multilayer printed circuit board according to FIG. 5b again consists of four electrically conductive, mutually insulated layers, for example made of copper, the first (top) layer representing the first main current conductor D and the fourth (bottom) layer on which the second and third are located Main current conductors S and A are located, each take up the load current and therefore have a sufficient layer thickness, for example 400 μm. The second and third layers have a layer thickness of, for example, 35 μm.



  In this second exemplary embodiment, the parallel-connected current conductors D-DI are arranged above the parallel-connected current conductors A-A1.



  FIG. 5a shows a top view of the main current conductors A, D and S arranged on the first and fourth layers without the second and third layers and without the intervening insulating layers, together with the components arranged thereon, the high-side and low-side switches T1. Tn, Tl '... Tn', an intermediate circuit capacitor C and the load L.



  The high-side switches Tl ... Tn and the low-side switches Tl '... Tn' each form a row, the two rows not being interlocked with one another as in the exemplary embodiment according to FIG. 4a, so that the interconnected connections sl dl '... sn-dn'der circuit breakers are arranged opposite each other. For this purpose, all connections of the high-side and low-side switches are bent at the same short distance from the semiconductor housing, so that the housing can be arranged lying on the multilayer circuit board.



  With the same dimensions as the first main current conductor D in the first layer (400 .mu.m) and exactly below it, a first secondary current conductor D1 is arranged in the second layer (35 .mu.m), the through-plating of the connections of the components connected to the first main current conductor D to the first Secondary current conductor D1, both current conductors D and D1 are connected in parallel to one another.



  Likewise, a second and third secondary current conductor S1 and A1 are arranged above the two main current conductors S and A arranged in the fourth layer (400um) and just above them in the third layer (35um), the through-contacting of the connections connecting the main current conductor S and A connected components, the current conductors S with S1 and D with D1 are connected in parallel with one another.



  For the control current conductors Gl and G2, what has already been said in the first exemplary embodiment also applies here.



  1. Circuit structure for a circuit for switching currents, with at least one switching element (Tl ... Tn, Tl '... Tn'), each with a main current conductor (D, S, A) for connecting the switching element (Tl. .. Tn, Tl '... Tn'), the poles (V +, GND) of a current source, an energy store (C) and a load (L) with each other, characterized in that for each at least between the switching elements (Tl .. ,

   Tn, Tl '... Tn') or between the poles (V +, GND) of the current source and the switching elements (Tl ... Tn, Tl '... Tn') or the main current conductor (D, S, A) with high current carrying capacity each have a further secondary current conductor (D1, Sl, A1) with lower current carrying capacity than the main current conductor (D, S, A) is connected in parallel.



  2. Circuit structure according to claim 1, in particular for a converter for obtaining alternating current from a direct current, with a half-bridge circuit lying at the poles (V +, GND) of a direct current source, comprising at least one or a predetermined number of mutually parallel series circuits, each having a highside switch (T1 ... Tn) and a low-side switch (Tl '... Tn'), whose interconnected connection points (sl-dl '... sn-dn') form the AC-carrying output (A), characterized that the drain connections (dl ...

   dn) of all high-side switches (Tl ... Tn) via a first main current conductor (D), to which a first secondary current conductor (D1) with a lower current carrying capacity than the main current conductor (D) is connected in parallel, with one another and with one connection of at least one
DC link capacitor (C) connected that the source connections (sl'bis sn ') of all lowside
Switch (T1'bis Tn ') via a second main current conductor (S), the second secondary current conductor (S1) with a lower one
Current carrying capacity as the main current conductor (S) is connected in parallel, with each other, with the other connection of the at least one intermediate circuit capacitor (C) and with a connection of the load (L) that the interconnected source connections (sl to sn)

   all highside switches (T1 to Tn) and drain connections (dl'bis dn ') all lowside switches (Tl'bis Tn') via a third main current conductor (A), to which a third secondary current conductor (A1) with lower current carrying capacity than the
Main current conductor (A) is connected in parallel, connected to one another and to the other connection of the load (L), that the gate connections (gl to gn) of all highside switches (T1 to Tn) are connected to one another via a first control current conductor (G1), and that the gate connections (gl'bis gn ') of all low-side switches (Tl'bis Tn') are connected to one another via a second control current conductor (G2).



  3. Circuit structure according to claim 2, characterized in that the main current conductors (D, S, A), the secondary current conductors (D1, Sl, A1) and the control current conductors (G1, G2) are arranged one above the other in four layers which are electrically insulated from one another, wherein in the first, a thick layer, a main conductor (D,
S, A) lies, in the second, a thin layer, the secondary current conductor (D1, Sl, A1) assigned to this main current conductor and the
Control current conductors (G1, G2) lie in the fourth, a thick layer, the other two
Main current conductors (D, S, A), and in the third, a thin layer,

   the one in the fourth
Layers of main current conductors assigned to secondary current conductors (S1, Al).



  4. Circuit structure according to claim 2, characterized in that the high-side switches (Tl ... Tn) and the low-side switches (Tl '... Tn') each form a row, the two rows being opposite one another so that the one another Connected connections (sl-dl '... sn-dn') of these switches are arranged in two rows, interlocked, with the connections of the switches (Tl ... Tn, Tl '... Tn') being bent that the outer connections (sl ... sn, gl ... gn, sl '... sn', gl '... gn') are bent at a short distance from the semiconductor housing and the middle connection (dl .. ,

   dn, dl '... dn') is bent at a greater distance from the semiconductor package.



  5. Circuit structure according to claim 2, characterized in that the high-side switches (Tl ... Tn) and the low-side switches (Tl '... Tn') each form a row, the two rows being opposite one another so that the one another Connected connections (sl-dl '... sn-dn') of these switches, which are all bent at the same short distance from the semiconductor package, are opposite each other.


    

Claims

claims

1. Circuit structure for a circuit for switching currents, with at least one switching element (Tl ... Tn, Tl '... Tn'), each with a main current conductor (D, S, A) for connecting the switching element (Tl .. .Tn, Tl '... Tn'), the poles (V +, GND) of a current source, an energy store (C) and a load (L) with each other,

characterized ,

that for each at least between the switching elements (Tl ... Tn, Tl '... Tn') or between the poles (V +, GND) of the current source and the switching elements (Tl ... Tn, Tl '... Tn' ) or the energy storage device (C) arranged main current conductor (D, S, A) with high current carrying capacity each have a further secondary current conductor (Dl, Sl, AI) with lower current carrying capacity than the main current conductor (D, S, A) is connected in parallel.

2. Circuit structure according to claim 1, in particular for a converter for obtaining alternating current from a direct current, with a half-bridge circuit located at the poles (V +, GND) of a direct current source, comprising at least one or a predetermined number of mutually parallel series circuits each a highside switch (Tl ... Tn) and a low-side switch (Tl '... Tn'), the interconnected connection points (sl-dl '... sn-dn') of the AC-carrying output ( A) form

characterized , that the drain connections (dl ... dn) of all highside switches (Tl ... Tn) via a first main current conductor (D), to which a first secondary current conductor (Dl) with a lower current carrying capacity than the main current conductor (D) is connected in parallel, and with the one connection of at least one intermediate circuit capacitor (C) that the source connections (sl 'to sn') of all low-side switches (Tl 'to Tn') are connected via a second main current conductor (S) to which a second secondary current conductor (Sl) is connected Lower current carrying capacity than the main current conductor (S) is connected in parallel with each other, with the other connection of the at least one intermediate circuit capacitor (C) and with a connection of the load (L) that the interconnected source connections (sl to sn) of all highside switches (Tl to Tn) and drain connections

(dl 'to dn') of all low-side switches (Tl 'to Tn') via a third main current conductor (A), to which a third secondary current conductor (AI) with a lower current carrying capacity than the main current conductor (A) is connected in parallel, with one another and with the other Connection of the load (L) are connected such that the gate connections (gl to gn) of all highside switches (Tl to Tn) are connected to one another via a first control current conductor (Gl), and that the gate connections (gl 'to gn') of all lowside -Switches (Tl 'to Tn') are connected to each other via a second control current conductor (G2).

3. Circuit structure according to claim 2, characterized in that the main current conductor (D, S, A), the secondary current conductor

(Dl, Sl, AI) and the control current conductors (Gl, G2) are arranged one above the other in four layers which are electrically insulated from one another, a main current conductor (D, S, A) being located in the first, a thick layer, in the second, a thin layer, the secondary current conductor (Dl, Sl, AI) assigned to this main current conductor and the control current conductors (Gl, G2), and in the fourth, a thick layer, the other two main current conductors (D, S, A) lie , and in the third, a thin layer, the secondary current conductors (S1, AI) assigned to the main current conductors lying in the fourth layer.

4. Circuit structure according to claim 2, characterized in that the high-side switch (Tl ... Tn) and the low-side switch

(Tl '... Tn') each form a row, with the two rows opposite each other so that the interconnected connections (sl-dl '... sn-dn') of these switches are interlocked in two rows , are arranged, the connections of the switches (Tl ... Tn, Tl '... Tn') being bent such that the outer connections (sl ... sn, gl ... gn, sl '.. .sn ', gl' ... gn ') are bent at a short distance from the semiconductor housing and the middle connection

(dl ... dn, dl '... dn') is bent at a greater distance from the semiconductor package.

5. Circuit structure according to claim 2, characterized in that the high-side switch (Tl ... Tn) and the low-side switch

(Tl '... Tn') each form a row, the two rows being opposite each other so that the interconnected connections (sl-dl "... sn-dn ') of these switches, all at the same short distance are bent from the semiconductor housing, lie opposite one another.