EP1364406A2 - Circuit arrangement - Google Patents
Circuit arrangementInfo
- Publication number
- EP1364406A2 EP1364406A2 EP02712790A EP02712790A EP1364406A2 EP 1364406 A2 EP1364406 A2 EP 1364406A2 EP 02712790 A EP02712790 A EP 02712790A EP 02712790 A EP02712790 A EP 02712790A EP 1364406 A2 EP1364406 A2 EP 1364406A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- plate
- heat
- circuit arrangement
- chips
- inner region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01005—Boron [B]
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- H01L2924/0101—Neon [Ne]
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- H01L2924/01015—Phosphorus [P]
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- H01L2924/01019—Potassium [K]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01031—Gallium [Ga]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01052—Tellurium [Te]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01065—Terbium [Tb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Definitions
- the invention relates to a circuit arrangement, i. H. an arrangement of interconnected components. More specifically, the invention relates to a circuit arrangement with a power section.
- the circuit arrangement should therefore be suitable for high currents.
- Such a circuit arrangement has the advantage that it requires only a small amount of space due to the housing-less chips.
- a disadvantage of such a circuit arrangement is that it acts as a power module for very high currents, such as, for. B. 300 amperes continuous current, is not suitable since conductor tracks arranged in a ceramic carrier generally cannot conduct such high currents.
- Another disadvantage is that it is difficult to dissipate heat from a circuit arrangement with a ceramic carrier.
- good heat dissipation is required for high-current applications, since in this case the components generally generate a lot of heat loss, which could lead to the destruction of the components.
- the invention has for its object to provide a circuit arrangement that takes up little space and is also suitable for high currents.
- the object is achieved by a circuit arrangement with the following features:
- the circuit arrangement has a power unit which comprises heat-generating components and at least one less heat-generating component.
- the less heat-generating component is arranged in an inner region of the circuit arrangement.
- the heat-generating components are arranged around the inner region and fastened to at least one metallic body which acts as an electrical line and to which they are electrically connected.
- the body is arranged on a heat sink in an electrically insulated manner, at least in the region of the heat-generating components.
- the heat sink is configured around the inner area.
- the heat-generating components are attached directly to the body, which also serves as a carrier for the heat-generating components and as an electrical line. No further lines and wires between the heat-generating components and the body are required, which would increase the electrical resistance.
- the electrical resistance of the body is very small compared to conductor tracks arranged in an insulating carrier. The circuit arrangement is therefore suitable for high currents.
- heat generated in the heat-generating components can be dissipated very quickly, since between the heat-generating components and the heat sink, essentially only the metallic body is arranged, which has a better thermal conductivity than a ceramic carrier.
- the circuit arrangement is designed to be very space-saving since the heat sink is only arranged under the components that generate high heat loss.
- the circuit arrangement is also very compact for the reason that the heat-generating components by the less heat Constructive component are arranged around, so that connections between the components can be very short.
- the dimensions of the body depend on the current strength and the thermal conductivity to be achieved.
- the body is preferably between approximately 2 mm and 4 mm thick and essentially consists of copper. However, other materials are suitable for the body, such as. B. aluminum.
- the heat-generating components can be chips that, for. B. contain (power) transistors, diodes or IGBT's.
- the less heat-generating component can, for. B. be a capacitor.
- the chips In order to reduce the space requirement of the circuit arrangement and to improve the heat dissipation, it is advantageous if the chips have no housing.
- the circuit arrangement preferably has a logic section via which the power section can be controlled.
- the logic part is arranged above the inner area. This also has the advantage of being electrical
- connections between the logic section and the power section can be very short.
- the connections can e.g. B. realized by wire connections (bonds). Additional connection lines and sensitive and cost-intensive plug connections can be omitted.
- the circuit arrangement can have a plate which covers the inner region and is arranged above the less heat-generating component.
- the plate has at least one opening above the inner area.
- the less heat-generating component is via a first wire-shaped connection, which is passed through the opening, electrically connected to the plate.
- the plate Due to the first wire-shaped connection, the plate has unevenness. So that the logic part can be applied to a flat surface, it is advantageous to provide a carrier which is arranged above the inner region and above the plate.
- the carrier can be electrically insulated from the plate by an insulating layer.
- the surface of the carrier facing the plate has an indentation in the region of the first wire-shaped connection in order to give space to the first wire-shaped connection.
- the surface of the carrier facing away from the plate is flat.
- the logic part is arranged in an electrically insulated manner on the surface of the carrier facing away from the plate.
- the carrier is used for mechanical adaptation between the plate and the logic part.
- the logic part can simply be removed from the carrier and repaired or replaced independently of the power unit.
- the carrier preferably consists essentially of a material with high thermal conductivity so that heat generated in the logic part can be dissipated via the carrier and via the plate into the heat sink.
- the carrier consists essentially of aluminum, for example, and is between 1 and 10 mm thick.
- the circuit arrangement is particularly suitable for connecting half bridges in parallel.
- the heat-generating components are package-less first chips and second chips configured, each containing a transistor, wherein the first chips are attached to at least a first metallic body and the second chips to a second metallic body.
- the first body is designed as a rail, which extends along the outer edge of the heat sink.
- the second body is plate-shaped and covers the inner area and the inner edge of the heat sink.
- the plate is arranged on the second body in an electrically insulated manner.
- the second body has a first opening above the inner region, which is arranged below the opening of the plate and through which the first wire-shaped connection is passed.
- the second body has at least one second opening above the inner region.
- the less heat-generating component is designed as a capacitor and is electrically connected to the second body via a second wire-shaped connection which is guided through the second opening.
- the first wire-shaped connection and the second wire-shaped connection are capacitor connections.
- the first chips are electrically connected to the board via wire connections.
- the second chips are electrically connected to the first body via wire connections.
- the second body and the plate form two metal plates which are electrically insulated from one another and which are different
- the capacitor is inserted between the different potentials.
- the first chips are connected in parallel and between the first body and the plate.
- the second chips are connected in parallel and between the first body and the second body.
- a first chip and a second chip each form a half bridge.
- the half bridges are connected in parallel to each other and between the plate and the second body.
- the circumferential arrangement of the heat sink enables a particularly compact arrangement of a large number of half bridges.
- the second chips are connected to one another by the plate-shaped second body.
- first rails can be provided, which z. B. each extend along an edge of the heat sink.
- the first bodies are preferably not electrically connected to one another so that they can lead different phases.
- the first body, the second body and the plate are made of copper, for example. However, there are also other materials, such as. B. aluminum, suitable.
- FIG. 1 shows part of a circuit diagram of a circuit arrangement with first chips, second chips, capacitors, an output connection, a ground connection and a voltage connection.
- FIG. 2 shows a three-dimensional representation of the circuit arrangement, in which the first chips, the second chips, a first body, a second body, a plate, a carrier, a logic part, a heat sink and bond connections are shown.
- FIG. 3 shows a cross section through an inner region of the circuit arrangement, in which capacitors, first wire-shaped connections, second wire-shaped connections, openings, first openings, second openings, insulating layers, the second body, the plate, the carrier and the logic part are shown are.
- a circuit arrangement is provided which has a power section LE and a logic section LO.
- the power section LE consists of a parallel connection of half bridges and of capacitors K connected in parallel.
- the capacitors K form fewer heat-generating components of the circuit arrangement.
- the power unit LE has, as heat-generating components, first chips C1, which are fastened directly to a plurality of first metallic bodies Kl, which are designed as a rail and essentially consist of copper, without a housing (see FIG. 2).
- the first bodies K1 are arranged along outer edges of a cooling body KK which runs around an inner region IB of the circuit arrangement.
- the first chips C1 each have a transistor.
- the first chips Cl are arranged on the first bodies Kl such that first source / drain regions of the first chips Cl are electrically connected to the first bodies Kl.
- the first bodies Kl have a thickness of approx. 4 mm, a width of approx. 10 mm and a length of approx. 12 cm or 18 cm.
- the first bodies Kl are electrically separated from one another and carry out different phases.
- the power unit LE has, as heat-generating components, second chips C2, which are designed like the first chips C1 and are fastened directly to a second metallic body K2 without a housing such that first source / drain regions of the transistors of the second chips C2 with the second one Body K2 are electrically connected.
- the second body K2 is plate-shaped, consists essentially of copper and covers the inner region and inner edges of the heat sink KK (see FIG. 2).
- the capacitors K are arranged under the second body K2 in the inner region IB (see FIG. 3). Second source / drain regions of the second chips C2 are connected to the first bodies Kl via bond connections B.
- a metallic plate P which essentially consists of copper, is arranged on the second body K2 in an electrically insulated manner by means of a first insulating layer II (see FIGS. 2 and 3).
- the plate P has jagged projections V which are arranged between adjacent second chips C2. Second source / drain regions of the transistors of the first chips C1 are connected to the projections V of the plate P via bond connections B.
- the second body K2 has first openings 01 and second openings 02 above the inner region.
- the plate P has openings 0 above the first openings 01 and the second openings 02 of the second body K2.
- the capacitors K are electrically connected to the plate P via first wire-shaped connections B1, which are passed through the first openings 01 of the second body K2 and through the openings 0 of the plate P arranged above them.
- the capacitors K are electrically connected to the second body K2 via second wire-shaped connections B2, which are led through the second openings 02.
- the openings 0 of the plate P, which are arranged above the ' second openings of the second body K2, give space to the second wire-shaped connections B2.
- the first wire-shaped connections B1 and the second wire-shaped connections B2 form capacitor connections of the capacitors K.
- the surfaces of the openings 0, the first openings 01 and the second openings 02 are provided with second insulating layers 12.
- a carrier T made of aluminum is arranged above the plate P (see FIG. 2).
- the carrier T is approximately 5 mm thick.
- the surface of the carrier T facing the plate P has indentations E in the region of the first wire-shaped connections B1 in order to give space to the first wire-shaped connections B1.
- the surface of the carrier T facing away from the plate P is flat.
- the logic part LO is arranged in an electrically insulated manner on the surface of the carrier T facing away from the plate P by a third insulating layer 13 and is connected to the power part LE via bond connections B.
- the first bodies Kl are connected to output connections AA (see FIG. 1).
- the second body K2 is connected to a voltage connection SP which is supplied with approximately 36 volts.
- the plate P is connected to a ground connection GA, to which zero volts are applied.
- the capacitor K are connected in parallel to each other and between the ground connection GA and the voltage connection SP.
- the first chips C1 are connected in parallel and between the output connection AA and the ground connection GA.
- the second chips C2 are connected in parallel and between the output terminal AA and the voltage terminal SP.
- the first chips C1 form a lowside drive.
- the second chips C2 form an en highside drive.
- a first chip C1 and a second chip C2 each form a half bridge. The half bridges are connected in parallel and between the ground connection GA and the voltage connection SP.
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10109329 | 2001-02-27 | ||
DE10109329A DE10109329C1 (en) | 2001-02-27 | 2001-02-27 | Circuit has power stage with heat generating components mounted around component(s) that generates less heat mounted in inner region, conducting metal body mounted on cooling body |
PCT/DE2002/000601 WO2002069404A2 (en) | 2001-02-27 | 2002-02-20 | Circuit arrangement |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1364406A2 true EP1364406A2 (en) | 2003-11-26 |
Family
ID=7675601
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02712790A Withdrawn EP1364406A2 (en) | 2001-02-27 | 2002-02-20 | Circuit arrangement |
Country Status (4)
Country | Link |
---|---|
US (1) | US6930373B2 (en) |
EP (1) | EP1364406A2 (en) |
DE (1) | DE10109329C1 (en) |
WO (1) | WO2002069404A2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7393236B2 (en) | 2005-09-02 | 2008-07-01 | Gm Global Technology Operations, Inc. | Integrated thermal and electrical connection system for power devices |
CN101326853B (en) * | 2005-12-13 | 2011-11-23 | Nxp股份有限公司 | Device for and method of processing an audio data stream |
US9559590B2 (en) * | 2008-03-06 | 2017-01-31 | Infineon Technologies Austria Ag | Methods and apparatus for a power supply |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3420535C2 (en) * | 1984-06-01 | 1986-04-30 | Anton Piller GmbH & Co KG, 3360 Osterode | Semiconductor module for a fast switching arrangement |
JP2692765B2 (en) * | 1989-12-22 | 1997-12-17 | 株式会社日立製作所 | Parallel circuit with diode and IGBT, module thereof, and power converter using the same |
US6002183A (en) * | 1995-05-04 | 1999-12-14 | Iversen; Arthur H. | Power semiconductor packaging |
DE29510335U1 (en) * | 1995-06-26 | 1995-08-24 | Siemens Ag | Electronic combined logic power module |
JP3124513B2 (en) * | 1997-06-18 | 2001-01-15 | 三菱電機株式会社 | Power semiconductor switch device |
DE19727548A1 (en) * | 1997-06-28 | 1999-01-07 | Bosch Gmbh Robert | Electronic control unit |
US6201701B1 (en) * | 1998-03-11 | 2001-03-13 | Kimball International, Inc. | Integrated substrate with enhanced thermal characteristics |
JPH11346480A (en) * | 1998-06-02 | 1999-12-14 | Hitachi Ltd | Inverter device |
DE19924994A1 (en) * | 1999-05-31 | 2000-12-21 | Tyco Electronics Logistics Ag | Sandwich-structured intelligent power module for building into appliances includes a printed circuit board for a logical unit with a recess fitted with a power substrate on a cooling plate connected by a wire bonding technique. |
-
2001
- 2001-02-27 DE DE10109329A patent/DE10109329C1/en not_active Expired - Fee Related
-
2002
- 2002-02-20 EP EP02712790A patent/EP1364406A2/en not_active Withdrawn
- 2002-02-20 WO PCT/DE2002/000601 patent/WO2002069404A2/en active Application Filing
-
2003
- 2003-08-27 US US10/649,839 patent/US6930373B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
---|
See references of WO02069404A2 * |
Also Published As
Publication number | Publication date |
---|---|
WO2002069404A3 (en) | 2003-05-22 |
US6930373B2 (en) | 2005-08-16 |
WO2002069404A2 (en) | 2002-09-06 |
US20040169268A1 (en) | 2004-09-02 |
DE10109329C1 (en) | 2002-05-02 |
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