EP1362284A1 - Verfahren zum multiplizieren von zwei binärzahlen - Google Patents

Verfahren zum multiplizieren von zwei binärzahlen

Info

Publication number
EP1362284A1
EP1362284A1 EP02703685A EP02703685A EP1362284A1 EP 1362284 A1 EP1362284 A1 EP 1362284A1 EP 02703685 A EP02703685 A EP 02703685A EP 02703685 A EP02703685 A EP 02703685A EP 1362284 A1 EP1362284 A1 EP 1362284A1
Authority
EP
European Patent Office
Prior art keywords
operand
bits
variable
constant
left shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP02703685A
Other languages
English (en)
French (fr)
Inventor
David Naccache
Christophe Tymen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus Card International SA
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card International SA, Gemplus SA filed Critical Gemplus Card International SA
Publication of EP1362284A1 publication Critical patent/EP1362284A1/de
Ceased legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/533Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5332Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm

Definitions

  • the present invention relates to a method for multiplying two binary numbers.
  • Multiplication is an arithmetic operation performed by digital processors by means of elementary operations such as shifting or adding.
  • the complexity of a multiplication can be assessed by estimating the quantity of elementary operations to perform to reach the result. It depends directly on the size of the two numbers to be multiplied.
  • the present invention thus relates to a multiplication method having reduced complexity.
  • a method for calculating the product of a first and a second binary number, the first number resulting from the concatenation of a first constant A and a first variable X of u bits, all the bits of the first constant A being equal to 1, the second number comprising s bits, method according to which this product results from a sequence of operations of which the most complex is a multiplication of u bits by s bits.
  • the method comprises the following operations: - a first left shift operation of (u + l) bits of the second number to obtain a first operand,
  • the third operand is obtained by means of the following operations: - a fourth left shift operation of (v + m) bits of the first variable X to obtain a fourth operand,
  • the method comprises the following operations:
  • the method comprises the following operations :
  • the second operand results from the following operations: - a fourth left shift operation of (u + l) bits of the second variable Y to obtain a fourth operand,
  • the second constant B being equal to the first constant A
  • the number v of bits of the second variable Y being equal to the number u of bits of the first variable X
  • the second operand results from the following operations: - a fourth operation of adding the first variable X and second Y to obtain a fourth operand
  • the method comprises the following operations: - a first operation for defining a first operand whose value is 2exp (2 (u + D) - 2exp (2u + l + 1) + 2exp (2u) .a second left shift operation of (u + l + 1) bits of the first variable X to obtain a second operand,
  • the invention also relates to a device comprising means for implementing the above method. It advantageously applies to cryptography, in particular to the encryption of a signature.
  • FIG. 1 a representation of the two binary numbers
  • the first number F can be analyzed as the concatenation of a first constant A and a first variable X.
  • the constant A has I bits all equal to 1 and the variable X has a length of u bits.
  • the invention has an advantage when the value of I is greater than 1, although it also applies otherwise.
  • the product P is therefore analyzed as the sum of three operands.
  • the first operand which is worth 2exp (u + l) .S is obtained by practicing a left shift on the second number S of (u + l) bits and, naturally, by forcing at 0 the (u + l) bits of weight low of the shifted number.
  • the second operand which is worth 2expu.S is obtained by practicing a left shift of u bits and a sign inversion.
  • the third operand is obtained by multiplying the first variable X by the second number S, using any known method.
  • the invention thus makes it possible to replace a multiplication of (u + l) bits by s bits with a set of operations comprising two shifts, a sign inversion, two additions and a multiplication of u bits by s bits.
  • the advantage provided by the invention is all the more significant the larger I is.
  • the second number S can also be analyzed as the concatenation of a constant B and a variable Y.
  • the third operand XS is analyzed also as the sum of three operands, the fourth operand which is worth 2exp (v + m) .X which is obtained by practicing a left shift on the first variable X of (v + m) bits, the fifth operand which is worth - 2expv .X which is obtained by practicing a left shift of v bits and a sign inversion and the sixth operand which is obtained by multiplying the first X and second Y variables.
  • the most complex operation is a multiplication of u bits by v bits.
  • the invention takes advantage of the fact that the second constant B is equal to the first constant A and that the size v of the second variable Y is identical to the size u of the first variable X.
  • the product P s' then writes:
  • the product P is here obtained by means of the following four operations.
  • a first operand is obtained by adding the first variable X and the second number S.
  • a second operand is obtained by left shift of (u + l) bits of the first operand.
  • a third operand is obtained by left shift of u bits and inversion of sign of the first operand.
  • a fourth operand is obtained by multiplying the first X and second Y variables. Finally, product F is obtained by adding these four operands.
  • the invention also considers that the first F, respectively the second number S, result from the concatenation of a first constant A and a first variable X, respectively of a second constant B and a second variable Y.
  • the product P is also presented here as the sum of three operands.
  • the first operand which is worth A.B.2exp (u + v) is easily defined as any binary number expressed by a series of coefficients each corresponding to a power of 2.
  • the second operand is worth (A.2exp_u.Y + B.2expv.X) and the third operand is obtained by multiplying the first X and second Y variables.
  • the second operand is calculated directly from the expression 2e ⁇ p_ (u + l) .Y - 2e ⁇ pu.Y + 2e ⁇ p_ (v + m) .X - 2expv.X
  • the two numbers F and S are equal, which amounts to saying that the multiplication becomes an elevation squared of the first number F.
  • the product P also appears here as the sum of four operands.
  • the first operand that appears in square brackets in equation [3] above is a simple binary number.
  • the second operand is obtained by a left shift of (u + l + 1) bits of the variable X.
  • the third operand is obtained by a left shift of (u + 1) bits of this variable X.
  • the fourth operand is therefore obtained by squaring the variable X.
  • the invention presented above thus makes it possible to reduce the size of the numbers which must be multiplied when calculating a product. It can be used on any numbers, in which case it is first necessary to identify the first constant A by searching for a series of bits at 1 at the head of the first number. It can also be used when this constant A is known a priori.
  • PKCS # 1 notably defines the signature G of a message m within the framework of the encryption algorithm known under the name of RSA (from the name of its authors Ron RIVEST, Adi SHAMIR and
  • F A
  • h (m) G Fexpd modn This is an operation known as modular exponentiation.
  • A is a constant of which all the bits, often several hundred, are worth 1.
  • P is a parameter with a size of approximately 10 bytes.
  • h (m) represents a hash function of the message m, of a fixed length, typically 20 bytes.
  • the number F is the concatenation of a constant A and a variable X of value P
  • h (m) comprising k bits.
  • the term d is an exponent.
  • the term n is the module according to which the signature G is calculated, it is equal to the product of two large numbers first.
  • the terms d and n define what is known as the public key used for encryption.
  • the signature G and the index i are respectively initialized at 1 and 0.
  • the bit dj is equal to 1
  • a step of multiplication of the signature G by the F number is performed.
  • the signature G now taking the value of the result of this operation.
  • this number F now taking the value of the result of this last operation.
  • the index i is then incremented by one and a second test is performed on the value of this index. If this is equal to k, the process is ended, while otherwise, the process is continued by resuming the first test.
  • the invention further relates to a device for implementing the multiplication method.
  • This device a processor comprising known elements such as, accumulator, shift register, adder, multiplier will therefore not be more detailed.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
EP02703685A 2001-02-12 2002-02-08 Verfahren zum multiplizieren von zwei binärzahlen Ceased EP1362284A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0101835 2001-02-12
FR0101835A FR2820851B1 (fr) 2001-02-12 2001-02-12 Methode pour multiplier deux nombres entiers
PCT/FR2002/000495 WO2002065271A1 (fr) 2001-02-12 2002-02-08 Méthode pour multiplier deux nombres binaires

Publications (1)

Publication Number Publication Date
EP1362284A1 true EP1362284A1 (de) 2003-11-19

Family

ID=8859871

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02703685A Ceased EP1362284A1 (de) 2001-02-12 2002-02-08 Verfahren zum multiplizieren von zwei binärzahlen

Country Status (4)

Country Link
US (1) US20040143618A1 (de)
EP (1) EP1362284A1 (de)
FR (1) FR2820851B1 (de)
WO (1) WO2002065271A1 (de)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3116411A (en) * 1959-06-15 1963-12-31 Control Data Corp Binary multiplication system utilizing a zero mode and a one mode
US3159739A (en) * 1961-01-24 1964-12-01 Honeywell Inc Fast multiply apparatus
US6430589B1 (en) * 1997-06-20 2002-08-06 Hynix Semiconductor, Inc. Single precision array processor
US6275841B1 (en) * 1997-12-11 2001-08-14 Intrinsity, Inc. 1-of-4 multiplier

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO02065271A1 *

Also Published As

Publication number Publication date
US20040143618A1 (en) 2004-07-22
FR2820851B1 (fr) 2003-05-30
FR2820851A1 (fr) 2002-08-16
WO2002065271A1 (fr) 2002-08-22

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