EP1301996A1 - Device for transmitting/receiving digital data capable of variable-rate processing, in particular on a vdsl environment - Google Patents

Device for transmitting/receiving digital data capable of variable-rate processing, in particular on a vdsl environment

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Publication number
EP1301996A1
EP1301996A1 EP01955402A EP01955402A EP1301996A1 EP 1301996 A1 EP1301996 A1 EP 1301996A1 EP 01955402 A EP01955402 A EP 01955402A EP 01955402 A EP01955402 A EP 01955402A EP 1301996 A1 EP1301996 A1 EP 1301996A1
Authority
EP
European Patent Office
Prior art keywords
memory
bytes
interleaving
counter
size
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01955402A
Other languages
German (de)
French (fr)
Inventor
Simone Mazzoni
Hélène CAME
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of EP1301996A1 publication Critical patent/EP1301996A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2732—Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2782—Interleaver implementations, which reduce the amount of required interleaving memory

Definitions

  • Digital data transmission / reception device capable of processing different bit rates, in particular in an environment
  • the invention relates generally to the transmission and reception of digital data which may have different bit rates, and more particularly to the dimensioning of the memory means used in the interleaving and deinterlacing processes carried out within these devices. transmit / receive capable of handling these different rates.
  • the invention applies advantageously and without limitation to an environment of very high speed digital subscriber lines also known to those skilled in the art, "environment or NDSL communication system” (Very High Rate Digital Subscriber Line in English). ), which is a digital communication system between an operator and users via very high speed transmission lines.
  • environment or NDSL communication system Very High Rate Digital Subscriber Line in English
  • the invention thus applies more particularly to transmission / reception devices, still commonly called
  • Modem arranged on the operator side and the user side at the ends of the transmission line.
  • an NDSL communication system is capable of delivering so-called “symmetrical” services and so-called “asymmetric” services.
  • a service is said to be “symmetrical” when the information rates exchanged between the operator and the user are identical in one direction of transmission and in the other (that is to say from the operator to the user and from user to operator).
  • a service is said to be "asymmetric" when the rate of information in a direction of transmission is different from the rate of information in the other direction of transmission.
  • Interleaving and deinterleaving processing of data sent and received by a modem requires the use of memories which must be sized, for a modem intended to operate at a predetermined rate, according to said rate.
  • the invention aims to propose an architecture of transmission / reception device (modem) which can be adapted on the operator side or on the user side (in other words, such a modem is then perfectly interchangeable between transmission and reception) , and which is capable, in particular in terms of the memory of the interleaving and deinterlacing means, of adapting to a certain number of different bit rates taken from a predetermined group of bit rates, while offering a reduction in the memory size .
  • modem transmission / reception device
  • the invention thus proposes in particular to use memory means the size of which is optimized from an overall throughput
  • the invention therefore proposes a device for transmitting / receiving digital data, capable of processing different bit rates taken from a group of predetermined bit rates (for example all the symmetrical or asymmetrical services offered by the VDSL communication system).
  • the device according to the invention comprises a coding / decoding stage (generally called by a person skilled in the art "channel coding / decoding stage") comprising interleaving means and deinterleaving means.
  • interleaving and deinterleaving means include a memory the minimum size of which is fixed as a function of the maximum bit rate of said group (for example the greatest asymmetric bit rate in the case of a VDSL system). Furthermore, this memory has a first memory space allocated to the interleaving means and a second memory space allocated to the deinterleaving means. The size of each of the two memory spaces can be configured as a function of the bit rate actually processed by the device. Within the meaning of the present invention, the term "bit rate" associated with a dimensioning of memory or memory space is understood to be a global bit rate, that is to say the sum of the bit rates in reception and in transmission.
  • the data transmission stream is protected from the noise of the transmission channel by a coding algorithm of the Reed-Solomon type, well known to those skilled in the art.
  • this is coupled to the interleaving means in order to distribute over time the errors introduced by the transmission channel, which often occur in bursts affecting several successive bytes, thus being able to reduce the correction capacity of the Reed-Solomon coding alone (in general eight bytes per packet).
  • the interleaving means then carry out a temporal interleaving of the bytes by modifying their transmission order, which makes it possible to obtain said temporal distribution of the errors.
  • the channel coding / decoding stage comprises means for coding and decoding Reed-S olomon of length N (N being for example equal to 240 bytes).
  • the interleaving means are then able to implement a convolutive triangular interleaving with I branches of i-1 blocks of M bytes.
  • the deinterlacing means are for their part capable of implementing a triangular convolutional deinterlacing with I 'branches of i'-1 blocks of M' bytes.
  • I and l are sub-multiples of N and i and i 'denote the current relative indices of the branches.
  • the size in bytes of the first memory space is equal to Ix (II) xM / 2, while the size in bytes of the second memory space is equal to I'x (I'-l) xM72.
  • the size of these two memory spaces is configurable by I, I ', M and M'.
  • the use of a convolutional triangular interlacing (and by consequence of a convolutive triangular deinterlacing) instead of another conventional type of interlacing, is particularly interesting because it makes it possible to reduce the latency generated by the memory. Indeed, a convolutional triangular interlacing requires less memory space, which allows a reduction in latency. And, this latency is an essential and decisive criterion for a VDSL communication system.
  • the memory is a random access memory, for example with dual access.
  • the interleaving and deinterleaving means respectively comprise first and second addressing means.
  • Each of these first and second addressing means includes:
  • a first counter defining the relative index i or i 1 of a branch
  • a second counter defining the number of bytes in a block, this second counter being incremented each time the first counter has reached its limit value of counting
  • a third counter defining the current index of a block in the branch of index i or i ', this third counter being incremented each time a block contains M or M' bytes
  • first addressing means (relating to the interleaving means) further comprise first address determining means, capable of determining the successive addresses for reading and writing in the memory of the data successively delivered by the means interleave. These first address determination means determine said addresses from the values supplied by the intermediate calculation means, the second and third counters, and from the parameter M.
  • the second addressing means (that is to say those relating to the deinterleaving means) further comprise second address determining means, capable of determining the successive addresses for reading and writing in said memory of data successively delivered to the deinterleaving means.
  • These second address determination means determine said addresses from the values supplied by the intermediate calculation means, the second and third counters, and from the parameter M ′, and from the size of the first memory space (which allows thus determining the first unoccupied address in the memory).
  • FIG. 2 illustrates in more detail but still schematically, the internal architecture of a transmission / reception device according to the invention
  • FIG. 3 illustrates schematically but in more detail the internal architecture of a coding / decoding stage of the device of Figure 2;
  • FIG. 6 illustrates in more detail, but still schematically, the internal architecture of the interleaving and deinterleaving means of a transmission / reception device, according to the invention
  • FIG. 7 schematically illustrates an embodiment of the first addressing means associated with the interleaving means
  • FIG. 8 schematically illustrates an embodiment of the second addressing means associated with the deinterleaving means.
  • the references TO and TU designate two transmission / reception devices according to the invention, also more simply designated terminals or modem.
  • One of these terminals for example the terminal TO, is located on the operator side, while the other terminal TU is located on the user side.
  • These two modems are linked by a very high speed LH communication line.
  • the VDSL 5 communication system allows the operator to offer symmetrical services, typically six symmetrical services S1-S6, that is to say services whose information rates in one direction or in the other (from operator to user or from user to operator) are the same.
  • the IS service with the lowest speed has a speed of
  • the operator can also provide so-called "asymmetrical" services A1-A6, that is to say with different information rates in the user-operator direction (direction
  • the first asymmetric service A1 offered has an upstream speed of 32x64 kbits / second and a downstream speed of 100x64 kbits / second.
  • uplink + downlink is the A6 service whose uplink rate is 32x64 kbits / second and whose downstream rate is 832x64 kbits / second.
  • the transmission / reception device will thus be able to be placed on the user side or on the operator side and will be able to
  • the terminal TO comprises (FIG. 2) a transmission chain and a reception chain, both connected to the transmission line LH.
  • One of the components of the terminal TO is an ETC channel coding / decoding stage comprising, at the transmission chain a CC channel coding block and at the reception chain level a DCC channel decoding block.
  • the CC channel coding block notably includes Reed-Solomon coding means, the structure and function of which are well known to those skilled in the art. These Reed-Solomon coding means are associated with interleaving means.
  • the Reed-Solomon coding allows, with the interleaving that follows, the correction of the burst errors introduced by the transmission channel.
  • Reed-Solomon coding is applied individually to each of the data packets delivered at the input of the CC coding block.
  • Reed-Solomon coding adds a certain number of parity bytes to the bytes of received packets and thus makes it possible to correct a certain number of erroneous bytes. It is assumed here, by way of example, that the Reed-Solomon coding performed is an RS coding (240, 224) with a correction power of 8.
  • Reed-Solomon coding means apply to 224 byte packets and add 16 bytes of parity to them, so as to form a Reed-Solomon code word whose length is 240 bytes. And, it is thus possible to correct up to 8 erroneous bytes.
  • the information delivered at the output of the ETC channel coding stage is delivered to a modulation block BM of conventional structure and known per se, which can for example carry out a quadrature modulation. Then, after various conventional processing operations carried out in a transmission unit EM comprising in particular an interface with the transmission line LH, the modulated signal is transmitted on this line LH transmission.
  • the reception chain of the terminal TO includes at the head a reception block ER comprising in particular a reception interface with the transmission line LH and carrying out conventional processing.
  • the modulated signal delivered at the output of the reception block ER is demodulated in a demodulation block BDM, then the demodulated signal is delivered to the channel decoding block DCC.
  • This thus comprises in particular deinterleaving means and Reed-Solomon decoding means.
  • the MET interleaving means follow on from Reed-Solomon CRS coding means, while the MDET deinterleaving means precede Reed-Solomon DCRS decoding means.
  • the interleaving and the deinterlacing carried out are a convolutive triangular interlacing and deinterlacing with I branches of i-1 blocks of M bytes with regard to the interleaving, and with I 'branches of i'-1 blocks of M' bytes, regarding deinterlacing.
  • the parameters I and M on the one hand, and I 'and M' on the other hand can be modified for example by software, and are delivered by MCD control means (FIG. 3) which can be software means.
  • These parameters define the sizes of the memory spaces which will be respectively allocated to the interleaving means and to the deinterleaving means as a function of the bit rate of the information transmitted by the terminal TO (parameters I and M) and of the bit rate of the information received by the terminal TO (parameters I 'and M').
  • I has been chosen by way of example equal to 7.
  • the interleaving means therefore comprise I parallel branches BRi (numbered for example from 0 to 1-1) which are produced with a delay increment of M per branch (M represents the maximum number of bytes of a block BKj of index j).
  • M represents the maximum number of bytes of a block BKj of index j.
  • Each branch can be considered as a delay line, the length of the branch of index i with i varying from 0 to I- 1, being equal to ixM bytes.
  • the first block (having for example the index 0) of M bytes is not interleaved and is delivered as is at the output of the interleaving means.
  • the next block (having index 1) of M bytes is delivered to the entry of the BRI branch and so on until the seventh block of M bytes (having index 6) is delivered to the branch BR6.
  • the cycle begins again with the byte blocks of indices 7 to 13, the preceding byte blocks being either delivered at the output of the interleaving means, or progressing by a block " BKj in the branch considered.
  • deinterleaving means associated with these interleaving means MET and which are consequently incorporated in the user terminal TU, have a structure similar to that which has just been described for the interleaving means, but the branch indices are inverted so that the largest interleaving delay corresponds to the smallest deinterlacing delay.
  • the MDET deinterleaving means incorporated in the operator terminal TO include the branches, the branch of index i 'having a length equal to i'xM' bytes.
  • I ⁇ I has been shown, but of course, if the service is an asymmetrical service, I and I 'are generally different, as are M and M'.
  • the interleaving means and the deinterleaving means comprise common memory means MM, formed for example from a dual access random access memory.
  • the memory space of this memory MM is then broken down into a first memory space ESM1 allocated to the interleaving means MET and into a second memory space ESM2 allocated to the deinterleaving means MDET.
  • the interleaving means furthermore comprise first addressing means MAD 1 receiving the parameters I and M, while the deinterleaving means comprise second addressing means MAD2 receiving the parameters I 'and M'.
  • the structure of these addressing means will be described in more detail below with reference to FIGS. 7 and 8.
  • the minimum size of the memory MM is fixed as a function of the maximum bit rate that can be processed by the transmission / reception device.
  • maximum flow rate is understood, of course, the sum of the upward flow and the downward flow. In this case, the maximum speed is provided here by the largest asymmetric service A6.
  • the maximum bit rate is equal to 832x64 kbits / second.
  • the number of noisy bits is therefore equal to the product of this bit rate by the duration of the impulsive noise, which gives a number of noisy bits equal to 13312 (1664 bytes).
  • the corrective power of Reed-Solomon coding here 8
  • the number nrs of Reed-Solomon words necessary to correct 1664 noisy bytes is equal to 1664/8, or 208.
  • the size of the memory space for storing such a maximum bit rate is then equal to N.nrs / 2 where N is the size of the Reed-Solomon coding (here 240).
  • the size of the second memory space ESM2 intended to support the rising bit rate is equal to I'x (I'-l) xM '/ 2.
  • I and I ' must be submultiples of the size N of the Reed-Solomon coding.
  • the final size of the MM memory is therefore equal to 26892 bytes.
  • the control means MCD will extract from this stored table the corresponding values of I, M, l 'and M', and the deliver to the addressing means MAD1 and MAD2, the structure of which will now be described in more detail with reference to FIGS. 7 and 8.
  • the first addressing means comprise a first counter CT1 delivering, to rhythm of a clock signal, the relative index i of a branch BRi.
  • This index i is delivered to intermediate calculation means MCI which determine the address adbs of the branch BRi in the first memory space. More precisely, this adbs address is equal to ix (i-l) / 2.
  • the structure of these MCI means can be easily formed of multiplier, divider and subtractor.
  • the first counter CT1 has a counting range equal to I and thus counts for example from 0 to 1-1.
  • the means MD 1 also comprise a second counter CT2 which delivers a current value m equal to the current number of bytes in each block BKj of a branch BRi.
  • the counting range of this counter CT2 is equal to M.
  • m can vary for example from 0 to M-1.
  • the means MDA1 also include a third counter CT3, which delivers the index j of the block BKj of the branch of index i.
  • the counting range of this counter CT3 is equal to i. In other words, j varies for example from 0 to i- 1.
  • This third counter CT3 is incremented each time a block contains M bytes, that is to say in this case each time for example that the counter CT2 reaches the value M.
  • the means MDA1 also comprise first means for determining the address MD1, which determine the read address ar in the memory and the write address aw in the memory. More precisely, the reading address ar is equal to (adbs + j) xM
  • the write address aw is then simply equal to the read address, but delayed by one cycle of the clock signal.
  • the means MD1 can be easily produced from adders and multipliers.
  • the structure of the second address means MDA2 which will deliver the addresses for reading ar 'and writing aw' in the second memory space of the memory MM, have a structure substantially similar to that which has just been described for the first address means MDA1. We will describe here only the difference between the means MDA1 and the means MDA2.
  • the first CTIO counter delivers the relative index i 'of a branch, i' varies this time from I'-l to 0.
  • the intermediate calculation means MCI deliver the address of each branch adbs' using a formula similar to that used for the address calculation, but replacing i by i '.
  • the second counter CT20 defines the number m 'of bytes in a block and is incremented each time the counter CT10 reaches its counting limit value, in this case when i 'reaches the value 0.
  • the second counter CT20 varies here from 0 to M'-1.
  • the third counter CT30 defines the current index j 'of a block in the branch of index i'. It varies from 0 to i'-1 and is incremented each time a block contains M 'bytes, that is to say when the second counter CT20 has reached the value M'.
  • the second addressing means MDA2 comprise second address determining means MD2 which determine the write addresses aw 'and ar'. However, this time, the means MD2 must take into account the size of the first memory space ESM1, this size OF is defined by the formula (1) below:
  • the addresses of the memory MM varied from 0 to OF-
  • the means MD2 then calculate the reading address ar 'according to the formula (2) below:
  • the write address aw ' is equal to the read address and is available at the next clock.

Abstract

The invention concerns a digital data transmitting/receiving device capable of processing different rates selected from a group of predetermined rates. It comprises a coding/decoding stage including interleaving means (MET) and deinterleaving means (MDET) comprising a storage (MM) whereof the minimum size is fixed in accordance with the maximum rate of said group, and having a first memory workspace (ESM1) allocated to the interleaving means and second memory workspace (ESM2) allocated to deinterleaving means. The size of each of said two memory workspaces are parameter-adaptive according to the rate being actually processed by the device.

Description

Dispositif d'émission/réception de données numériques capable de traiter des débits différents, en particulier dans un environnement Digital data transmission / reception device capable of processing different bit rates, in particular in an environment
VDSL.VDSL.
L'invention concerne d'une façon générale l'émission et la réception de données numériques pouvant présenter des débits différents, et plus particulièrement le dimensionnement des moyens de mémoire utilisés dans les traitements d'entrelacement et de désentrelacement effectués au sein de ces dispositifs d'émission/réception capables de traiter ces débits différents.The invention relates generally to the transmission and reception of digital data which may have different bit rates, and more particularly to the dimensioning of the memory means used in the interleaving and deinterlacing processes carried out within these devices. transmit / receive capable of handling these different rates.
L'invention s'applique avantageusement et non limitativement à un environnement de lignes d'abonnés numériques à très haut débit encore dénommé par l'homme du métier, "environnement ou système de communication NDSL" (Very High Rate Digital Subscriber Line en langue anglaise), qui est un système de communication numérique entre un opérateur et des utilisateurs par rintermédiaire de lignes de transmission à très haut débit.The invention applies advantageously and without limitation to an environment of very high speed digital subscriber lines also known to those skilled in the art, "environment or NDSL communication system" (Very High Rate Digital Subscriber Line in English). ), which is a digital communication system between an operator and users via very high speed transmission lines.
L'invention s'applique ainsi plus particulièrement aux dispositifs d'émission/réception, encore couramment dénomméThe invention thus applies more particularly to transmission / reception devices, still commonly called
"Modem", disposés du côté opérateur et du côté utilisateur aux extrémités de la ligne de transmission."Modem", arranged on the operator side and the user side at the ends of the transmission line.
L'homme du métier sait qu'un système de communication NDSL est capable de délivrer des services dits "symétriques" et des services dits "asymétriques". Un service est dit "symétrique" lorsque les débits d'information échangés entre l'opérateur et l'utilisateur sont identiques dans un sens de transmission et dans l'autre (c'est-à-dire de l'opérateur vers l'utilisateur et de l'utilisateur vers l'opérateur).Those skilled in the art know that an NDSL communication system is capable of delivering so-called "symmetrical" services and so-called "asymmetric" services. A service is said to be "symmetrical" when the information rates exchanged between the operator and the user are identical in one direction of transmission and in the other (that is to say from the operator to the user and from user to operator).
Un service est - dit "asymétrique" lorsque le débit des informations dans un sens de transmission est différent du débit des informations dans l'autre sens de transmission.A service is said to be "asymmetric" when the rate of information in a direction of transmission is different from the rate of information in the other direction of transmission.
Les traitements d'entrelacement et de désentrelacement des données émises et reçues par un modem nécessitent l'utilisation de mémoires qui doivent être dimensionnées, pour un modem destiné à fonctionner selon un débit prédéterminé, en fonction dudit débit. • Interleaving and deinterleaving processing of data sent and received by a modem requires the use of memories which must be sized, for a modem intended to operate at a predetermined rate, according to said rate. •
L'invention vise à proposer une architecture de dispositif d'émission/réception (modem) qui puisse s'adapter côté opérateur ou côté utilisateur ( en d'autres termes, un tel modem est alors parfaitement interchangeable entre l'émission et la réception), et qui soit capable, notamment au niveau de la mémoire des moyens d'entrelacement et de désentrelacement, de s'adapter à un certain nombre de débits différents pris parmi un groupe prédéterminé de débits, tout en offrant une réduction de la taille-mémoire.The invention aims to propose an architecture of transmission / reception device (modem) which can be adapted on the operator side or on the user side (in other words, such a modem is then perfectly interchangeable between transmission and reception) , and which is capable, in particular in terms of the memory of the interleaving and deinterlacing means, of adapting to a certain number of different bit rates taken from a predetermined group of bit rates, while offering a reduction in the memory size .
L'invention propose ainsi notamment d'utiliser des moyens de mémoire dont la taille est optimisée à partir d'un débit globalThe invention thus proposes in particular to use memory means the size of which is optimized from an overall throughput
(émission+réception), qui puissent être partagés entre les moyens d'entrelacement et les moyens de désentrelacement, et qui soient reconfigurables au niveau des allocations mémoire, en fonction du débit effectivement traité par le dispositif d'émission/réception (modem). L'invention propose donc un dispositif d'émission/réception de données numériques, capable de traiter des débits différents pris parmi un groupe de débits prédéterminés (par exemple tous les services symétriques ou asymétriques proposés par le système de communication VDSL). Le dispositif selon l'invention comprend un étage de codage/décodage (généralement dénommés par l'homme du métier "étage de codage/décodage de canal") comportant des moyen d'entrelacement et des moyens de désentrelacement. Ces moyens d'entrelacement et de désentrelacement incluent une mémoire dont la taille minimale est fixée en fonction du débit maximal dudit groupe (par exemple le plus grand débit asymétrique dans le cas d'un système VDSL). Par ailleurs, cette mémoire possède un premier espace-mémoire alloué aux moyens d'entrelacement et un deuxième espace-mémoire alloué aux moyens de désentrelacement. La taille de chacun des deux espaces-mémoire est paramétrable en fonction du débit effectivement traité par le dispositif. Au sens de la présente invention, le terme "débit" associé à un dimensionnement de mémoire ou d'espace-mémoire s'entend comme étant un débit global, c'est-à-dire la somme des débits en réception et en émission. II est ainsi possible de réduire considérablement la taille des moyens de mémoire requis pour les moyens d'entrelacement et de désentrelacement lorsque ces moyens sont réalisés au sein d'un modem capable d'être disposé au choix côté opérateur ou côté utilisateur, et capable de pouvoir traiter au choix plusieurs débits différents symétriques ou asymétriques.(transmission + reception), which can be shared between the interleaving means and the deinterleaving means, and which can be reconfigured in terms of memory allocations, as a function of the bit rate actually processed by the transmission / reception device (modem). The invention therefore proposes a device for transmitting / receiving digital data, capable of processing different bit rates taken from a group of predetermined bit rates (for example all the symmetrical or asymmetrical services offered by the VDSL communication system). The device according to the invention comprises a coding / decoding stage (generally called by a person skilled in the art "channel coding / decoding stage") comprising interleaving means and deinterleaving means. These interleaving and deinterleaving means include a memory the minimum size of which is fixed as a function of the maximum bit rate of said group (for example the greatest asymmetric bit rate in the case of a VDSL system). Furthermore, this memory has a first memory space allocated to the interleaving means and a second memory space allocated to the deinterleaving means. The size of each of the two memory spaces can be configured as a function of the bit rate actually processed by the device. Within the meaning of the present invention, the term "bit rate" associated with a dimensioning of memory or memory space is understood to be a global bit rate, that is to say the sum of the bit rates in reception and in transmission. It is thus possible to considerably reduce the size of the memory means required for the interleaving and deinterleaving means when these means are produced within a modem capable of being arranged either on the operator side or on the user side, and capable of be able to process a choice of several different symmetrical or asymmetrical bit rates.
Généralement, le flot de transmission de données est protégé vis-à-vis des bruits du canal de transmission par un algorithme de codage du type Reed-Solomon, bien connu de l'homme du métier. Afin d'augmenter l'efficacité du codage de Reed-Solomon, celui-ci est couplé aux moyens d'entrelacement afin de répartir dans le temps les erreurs introduites par le canal de transmission, qui se produisent souvent en rafale affectant plusieurs octets successifs, pouvant ainsi réduire la capacité de correction du codage Reed-Solomon seul (en général huit octets par paquet). Les moyens d'entrelacement procèdent alors à un entrelacement temporel des octets en modifiant leur ordre de transmission, ce qui permet d'obtenir ladite répartition temporelle des erreurs.Generally, the data transmission stream is protected from the noise of the transmission channel by a coding algorithm of the Reed-Solomon type, well known to those skilled in the art. In order to increase the efficiency of Reed-Solomon coding, this is coupled to the interleaving means in order to distribute over time the errors introduced by the transmission channel, which often occur in bursts affecting several successive bytes, thus being able to reduce the correction capacity of the Reed-Solomon coding alone (in general eight bytes per packet). The interleaving means then carry out a temporal interleaving of the bytes by modifying their transmission order, which makes it possible to obtain said temporal distribution of the errors.
Plus précisément, selon un mode de réalisation de l'invention, l'étage de codage/décodage de canal comporte des moyens de codage et de décodage de Reed-S olomon de longueur N (N étant par exemple égal à 240 octets). Les moyens d'entrelacement sont alors aptes à mettre en oeuvre un entrelacement triangulaire convolutif à I branches de i-1 blocs de M octets. Les moyens de désentrelacement sont quant à eux aptes à mettre en oeuvre un désentrelacement convolutif triangulaire à I' branches de i'-l blocs de M' octets. I et l' sont des sous-multiples de N et i et i' désignent les indices relatifs courants des branches. Par ailleurs, la taille en octets du premier espace-mémoire est égale à Ix(I-l)xM/2, tandis que la taille en octets du deuxième espace-mémoire est égale à I'x(I'-l)xM72. Et, la taille de ces deux espaces-mémoire est paramétrable par I, I', M et M'. L'utilisation d'un entrelacement triangulaire convolutif (et par conséquent d'un désentrelacement triangulaire convolutif) au lieu d'un autre type d'entrelacement classique, est particulièrement intéressant car il permet de diminuer la latence engendrée par la mémoire. En effet, un entrelacement triangulaire convolutif nécessite un espace-mémoire moins important, ce qui permet une diminution de la latence. Et, cette latence est un critère primordial et décisif pour un système de communication VDSL.More precisely, according to one embodiment of the invention, the channel coding / decoding stage comprises means for coding and decoding Reed-S olomon of length N (N being for example equal to 240 bytes). The interleaving means are then able to implement a convolutive triangular interleaving with I branches of i-1 blocks of M bytes. The deinterlacing means are for their part capable of implementing a triangular convolutional deinterlacing with I 'branches of i'-1 blocks of M' bytes. I and l are sub-multiples of N and i and i 'denote the current relative indices of the branches. Furthermore, the size in bytes of the first memory space is equal to Ix (II) xM / 2, while the size in bytes of the second memory space is equal to I'x (I'-l) xM72. And, the size of these two memory spaces is configurable by I, I ', M and M'. The use of a convolutional triangular interlacing (and by consequence of a convolutive triangular deinterlacing) instead of another conventional type of interlacing, is particularly interesting because it makes it possible to reduce the latency generated by the memory. Indeed, a convolutional triangular interlacing requires less memory space, which allows a reduction in latency. And, this latency is an essential and decisive criterion for a VDSL communication system.
Selon un mode de réalisation particulièrement simple, la mémoire est une mémoire vive, par exemple à double accès. Les moyens d'entrelacement et de désentrelacement comprennent respectivement des premier et deuxième moyens d'adressage. Chacun de ces premier et deuxième moyens d'adressage comprennent :According to a particularly simple embodiment, the memory is a random access memory, for example with dual access. The interleaving and deinterleaving means respectively comprise first and second addressing means. Each of these first and second addressing means includes:
- un premier compteur définissant l'indice relatif i ou i1 d'une branche, - un deuxième compteur définissant le nombre d'octets dans un bloc, ce deuxième compteur étant incrémenté à chaque fois que le premier compteur a atteint sa valeur limite de comptage,a first counter defining the relative index i or i 1 of a branch, a second counter defining the number of bytes in a block, this second counter being incremented each time the first counter has reached its limit value of counting,
- un troisième compteur définissant l'indice courant d'un bloc dans la branche d'indice i ou i', ce troisième compteur étant incrémenté à chaque fois qu'un bloc contient M ou M' octets, eta third counter defining the current index of a block in the branch of index i or i ', this third counter being incremented each time a block contains M or M' bytes, and
- des moyens de calcul intermédiaires, calculant l'adresse de chaque branche dans ladite mémoire à partir du contenu du premier compteur, c'est-à-dire à partir de l'indice relatif i ou i'.- Intermediate calculation means, calculating the address of each branch in said memory from the content of the first counter, that is to say from the relative index i or i '.
Par ailleurs, les premiers moyens d'adressage (relatifs aux moyens d'entrelacement) comportent en outre des premiers moyens de détermination d'adresse, aptes à déterminer les adresses successives de lecture et d'écriture dans la mémoire des données successivement délivrées au moyen d'entrelacement. Ces premiers moyens de détermination d'adresse déterminent lesdites adresses à partir des valeurs fournies par les moyens de calcul intermédiaires, les deuxième et troisième compteurs, et à partir du paramètre M.Furthermore, the first addressing means (relating to the interleaving means) further comprise first address determining means, capable of determining the successive addresses for reading and writing in the memory of the data successively delivered by the means interleave. These first address determination means determine said addresses from the values supplied by the intermediate calculation means, the second and third counters, and from the parameter M.
Par ailleurs, les deuxièmes moyens d'adressage (c'est-à-dire ceux relatifs aux moyens de désentrelacement) comportent en outre des deuxièmes moyens de détermination d'adresse, aptes à déterminer les adresses successives de lecture et d'écriture dans ladite mémoire des données successivement délivrées aux moyens de désentrelacement. Ces deuxièmes moyens dé détermination d'adresse déterminent lesdites adresses à partir des valeurs fournies par les moyens de calcul intermédiaires, les deuxième et troisièmes compteurs, et à partir du paramètre M', et de la taille du premier espace-mémoire (ce qui permet ainsi de déterminer la première adresse non occupée dans la mémoire). D'autres avantages et caractéristiques de l'invention apparaîtront à l'examen de la description détaillée de modes de réalisation, nullement limitatifs, et des dessins annexés, sur lesquels : - la figure 1 illustre très schematiquement Un système de communication entre deux dispositifs d'émission/réception, selon l'invention;Furthermore, the second addressing means (that is to say those relating to the deinterleaving means) further comprise second address determining means, capable of determining the successive addresses for reading and writing in said memory of data successively delivered to the deinterleaving means. These second address determination means determine said addresses from the values supplied by the intermediate calculation means, the second and third counters, and from the parameter M ′, and from the size of the first memory space (which allows thus determining the first unoccupied address in the memory). Other advantages and characteristics of the invention will become apparent on examining the detailed description of embodiments, in no way limiting, and the appended drawings, in which: - Figure 1 very schematically illustrates A communication system between two devices d 'transmission / reception, according to the invention;
- la figure 2 illustre plus en détail mais toujours schematiquement, l'architecture interne d'un dispositif d'émission/ réception, selon l'invention;- Figure 2 illustrates in more detail but still schematically, the internal architecture of a transmission / reception device according to the invention;
- la figure 3 illustre schematiquement mais plus en détail l'architecture interne d'un étage de codage/décodage du dispositif dé la figure 2;- Figure 3 illustrates schematically but in more detail the internal architecture of a coding / decoding stage of the device of Figure 2;
- les figures 4 et 5 illustrent schematiquement les principes de mise en oeuvre d'un entrelacement et d'un désentrelacement triangulaires convolutif s;- Figures 4 and 5 schematically illustrate the principles of implementation of a convolutive triangular interlacing and deinterlacing s;
- la figure 6 illustre plus en détail, mais toujours schematiquement, l'architecture interne des moyens d'entrelacement et de désentrelacement d'un dispositif d'émission/réception, selon l'invention; - la figure 7 illustre schematiquement un mode de réalisation des premiers moyens d'adressage associés aux moyens d'entrelacement; et- Figure 6 illustrates in more detail, but still schematically, the internal architecture of the interleaving and deinterleaving means of a transmission / reception device, according to the invention; - Figure 7 schematically illustrates an embodiment of the first addressing means associated with the interleaving means; and
- la figure 8 illustre schematiquement un exemple de réalisation des deuxièmes moyens d'adressage associés aux moyens de désentrelacement. On va maintenant décrire une application de l'invention à un système de communication VDSL, bien que l'invention n'y soit pas limitée.- Figure 8 schematically illustrates an embodiment of the second addressing means associated with the deinterleaving means. We will now describe an application of the invention to a VDSL communication system, although the invention is not limited thereto.
Ainsi, sur la figure 1, les références TO et TU désignent deux dispositifs d'émission/réception selon l'invention, encore désignés plus simplement terminaux ou modem. L'un de ces terminaux, par exemple le terminal TO, est situé côté opérateur, tandis que l'autre terminal TU est situé côté utilisateur. Ces deux modems sont reliés par une ligne de communication LH à très haut débit.Thus, in FIG. 1, the references TO and TU designate two transmission / reception devices according to the invention, also more simply designated terminals or modem. One of these terminals, for example the terminal TO, is located on the operator side, while the other terminal TU is located on the user side. These two modems are linked by a very high speed LH communication line.
Ainsi, à titre indicatif, le système de communication VDSL 5 permet à l'opérateur d'offrir des services symétriques, typiquement six services symétriques S1-S6, c'est-à-dire des services dont les débits d'informations dans un sens de transmission ou dans l'autre (de l'opérateur vers l'utilisateur ou de l'utilisateur vers l'opérateur) sont identiques. A titre d'exemple, le service SI qui présente le plusîaible débit a un débit deThus, as an indication, the VDSL 5 communication system allows the operator to offer symmetrical services, typically six symmetrical services S1-S6, that is to say services whose information rates in one direction or in the other (from operator to user or from user to operator) are the same. For example, the IS service with the lowest speed has a speed of
10 32x64 kbits/seconde, tandis que le service symétrique le plus rapide S6 a un débit de 362x64 kbits/seconde.10 32x64 kbits / second, while the fastest symmetrical service S6 has a speed of 362x64 kbits / second.
Avec le système VDSL, l'opérateur peut également fournir des services dits "asymétriques" A1-A6, c'est-à-dire présentant des débits d'informations différents dans le sens utilisateur-opérateur (sensWith the VDSL system, the operator can also provide so-called "asymmetrical" services A1-A6, that is to say with different information rates in the user-operator direction (direction
15 montant) et dans le sens opérateur-utilisateur (sens descendant).15 upward) and in the operator-user direction (downward direction).
Ainsi, à titre indicatif, le premier service asymétrique Al offert possède un débit dans le sens montant de 32x64 kbits/seconde et un débit dans le sens descendant de 100x64 kbits/seconde.Thus, as an indication, the first asymmetric service A1 offered has an upstream speed of 32x64 kbits / second and a downstream speed of 100x64 kbits / second.
Le service asymétrique possédant le plus grand débit globalThe asymmetric service with the highest overall speed
20 d'informations (débit montant + débit descendant) est le service A6 dont le débit dans le sens montant est égal à 32x64 kbits/seconde et dont le débit dans le sens descendant est égal à 832x64 kbits/seconde.20 information (uplink + downlink) is the A6 service whose uplink rate is 32x64 kbits / second and whose downstream rate is 832x64 kbits / second.
Le dispositif d'émission/réception selon l'invention, va ainsi pouvoir être disposé côté utilisateur ou côté opérateur et va être capable deThe transmission / reception device according to the invention will thus be able to be placed on the user side or on the operator side and will be able to
25. traiter tous ces services moyennant, comme on va le voir plus en détail ci- après, un dimensionnement de la mémoire affectée aux moyens d'entrelacement/désentrelacement en fonction du débit maximum parmi les services proposés, en l'espèce le débit du plus grand service asymétrique (service A6), et moyennant un paramétrage de l'espace-25. process all of these services by means of, as will be seen in more detail below, a dimensioning of the memory allocated to the interleaving / deinterleaving means as a function of the maximum bit rate among the services offered, in this case the bit rate of the larger asymmetric service (A6 service), and with space settings
30 mémoire de cette mémoire en fonction du service effectivement traité par le dispositif.30 memory of this memory as a function of the service actually processed by the device.
On va maintenant décrire plus en détail l'architecture interne de l'un des terminaux de la figure 1 (en l'espèce le terminal opérateur TO), étant bien entendu que tout ce qui va être décrit ci-après est valable pour leWe will now describe in more detail the internal architecture of one of the terminals of FIG. 1 (in this case the operator terminal TO), it being understood that all that will be described below is valid for the
35 terminal TU. Le terminal TO comporte (figure 2) une chaîne d'émission et une chaîne de réception, toutes les deux reliées à la ligne de transmission LH.35 TU terminal. The terminal TO comprises (FIG. 2) a transmission chain and a reception chain, both connected to the transmission line LH.
L'un des constituants du terminal TO est un étage ETC de codage/décodage de canal comportant, au niveau de la chaîne d'émission un bloc de codage de canal CC et au niveau de la chaîne de réception un bloc de décodage de canal DCC.One of the components of the terminal TO is an ETC channel coding / decoding stage comprising, at the transmission chain a CC channel coding block and at the reception chain level a DCC channel decoding block. .
Le bloc de codage de canal CC comporte notamment des moyens de codage de Reed-Solomon, dont la structure et la fonction sont bien connues de l'homme du métier. Ces moyens de codage de Reed-Solomon sont associés à des moyens d'entrelacement.The CC channel coding block notably includes Reed-Solomon coding means, the structure and function of which are well known to those skilled in the art. These Reed-Solomon coding means are associated with interleaving means.
Plus précisément, le codage de Reed-Solomon permet avec l'entrelacement qui le suit, la correction des erreurs en rafale introduites par le canal de transmission. Le codage de Reed-Solomon s'applique individuellement à chacun des paquets de données délivrés en entrée du bloc de codage CC. Le codage de Reed-Solomon ajoute un certain nombre d'octets de parité aux octets des paquets reçus et permet ainsi de corriger un certain nombre d'octets erronés. On suppose ici, à titre d'exemple, que le codage de Reed-Solomon réalisé est un codage RS (240, 224) avec un pouvoir correcteur de 8. Ceci signifie que les moyens de codage de Reed- Solomon s'appliquent sur des paquets de 224 octets et y rajoutent 16 octets de parité, de façon à former un mot codé de Reed-Solomon dont la longueur est de 240 octets. Et, il est possible ainsi de corriger jusqu'à 8 octets erronés.More precisely, the Reed-Solomon coding allows, with the interleaving that follows, the correction of the burst errors introduced by the transmission channel. Reed-Solomon coding is applied individually to each of the data packets delivered at the input of the CC coding block. Reed-Solomon coding adds a certain number of parity bytes to the bytes of received packets and thus makes it possible to correct a certain number of erroneous bytes. It is assumed here, by way of example, that the Reed-Solomon coding performed is an RS coding (240, 224) with a correction power of 8. This means that the Reed-Solomon coding means apply to 224 byte packets and add 16 bytes of parity to them, so as to form a Reed-Solomon code word whose length is 240 bytes. And, it is thus possible to correct up to 8 erroneous bytes.
Puis, afin de répartir dans le temps les erreurs introduites par le canal qui se produisent souvent en rafale affectant plusieurs octets successifs, pouvant ainsi excéder la capacité de correction du codage de Reed-Solomon seule, on procède, afin d'augmenter l'efficacité de ce codage de Reed-Solomon, à un entrelacement temporel des octets en modifiant leur ordre de transmission. Les informations délivrées à la sortie de l'étage de codage de canal ETC, sont délivrées à un bloc de modulation BM de structure classique et connue en soi, qui peut par exemple effectuer une modulation en quadrature. Puis, après différents traitements classiques effectués dans un bloc d'émission EM comportant notamment une interface avec la ligne de transmission LH, le signal modulé est transmis sur cette ligne de transmission LH.Then, in order to distribute in time the errors introduced by the channel which often occur in burst affecting several successive bytes, thus being able to exceed the capacity of correction of the coding of Reed-Solomon alone, one proceeds, in order to increase the efficiency of this Reed-Solomon coding, to a temporal interleaving of the bytes by modifying their transmission order. The information delivered at the output of the ETC channel coding stage is delivered to a modulation block BM of conventional structure and known per se, which can for example carry out a quadrature modulation. Then, after various conventional processing operations carried out in a transmission unit EM comprising in particular an interface with the transmission line LH, the modulated signal is transmitted on this line LH transmission.
D'une façon analogue, la chaîne de réception du terminal TO comporte en tête un bloc de réception ER comportant notamment une interface de réception avec la ligne de transmission LH et effectuant des traitements classiques. Le signal modulé délivré à la sortie du bloc de réception ER est démodulé dans un bloc de démodulation BDM, puis le signal démodulé est délivré au bloc de décodage de canal DCC. Celui-ci comporte ainsi notamment des moyens de désentrelacement et des moyens dé décodage de Reed-Solomon. On se réfère maintenant plus particulièrement aux figures 3 et suivantes, pour décrire plus en détail l'architecture interne et le fonctionnement des moyens d'entrelacement et de désentrelacement.In an analogous manner, the reception chain of the terminal TO includes at the head a reception block ER comprising in particular a reception interface with the transmission line LH and carrying out conventional processing. The modulated signal delivered at the output of the reception block ER is demodulated in a demodulation block BDM, then the demodulated signal is delivered to the channel decoding block DCC. This thus comprises in particular deinterleaving means and Reed-Solomon decoding means. Referring now more particularly to Figures 3 and following, to describe in more detail the internal architecture and the operation of the interleaving and deinterleaving means.
Comme illustré sur la figure 3 et déjà expliqué plus haut, les moyens d'entrelacement MET font suite à des moyens de codage de Reed- Solomon CRS, tandis que les moyens de désentrelacement MDET précèdent des moyens de décodage DCRS de Reed-Solomon.As illustrated in FIG. 3 and already explained above, the MET interleaving means follow on from Reed-Solomon CRS coding means, while the MDET deinterleaving means precede Reed-Solomon DCRS decoding means.
Comme illustré schematiquement sur les figures 4 et . 5, l'entrelacement et le désentrelacement réalisés sont un entrelacement et un désentrelacement triangulaires convolutifs à I branches de i-1 blocs de M octets en ce qui concerne l'entrelacement, et à I' branches de i'-l blocs de M' octets, en ce qui concerne le désentrelacement.As illustrated schematically in Figures 4 and. 5, the interleaving and the deinterlacing carried out are a convolutive triangular interlacing and deinterlacing with I branches of i-1 blocks of M bytes with regard to the interleaving, and with I 'branches of i'-1 blocks of M' bytes, regarding deinterlacing.
Comme on le verra plus en détail ci-après, les paramètres I et M d'une part, et I' et M' d'autre part, sont modifiables par exemple par logiciel, et sont délivrés par des moyens de commande MCD (figure 3) qui peuvent être des moyens logiciels. Ces paramètres définissent les tailles des espaces-mémoire qui vont être respectivement allouées aux moyens d'entrelacement et aux moyens de désentrelacement en fonction du débit des informations émises par le terminal TO (paramètres I et M) et du débit des informations reçues par le terminal TO (paramètres I' et M'). Sur la figure 4, I a été choisi à titre d'exemple égal à 7. Les moyens d'entrelacement comportent donc I branches parallèles BRi (numérotées par exemple de 0 à 1-1) qui sont réalisées avec un incrément de retard de M par branche (M représente le nombre maximal d'octets d'un bloc BKj d'indice j). Chaque branche peut être considérée comme une ligne à retard, la longueur de la branche d'indice i avec i variant de 0 à I- 1 , étant égale à ixM octets.As will be seen in more detail below, the parameters I and M on the one hand, and I 'and M' on the other hand, can be modified for example by software, and are delivered by MCD control means (FIG. 3) which can be software means. These parameters define the sizes of the memory spaces which will be respectively allocated to the interleaving means and to the deinterleaving means as a function of the bit rate of the information transmitted by the terminal TO (parameters I and M) and of the bit rate of the information received by the terminal TO (parameters I 'and M'). In FIG. 4, I has been chosen by way of example equal to 7. The interleaving means therefore comprise I parallel branches BRi (numbered for example from 0 to 1-1) which are produced with a delay increment of M per branch (M represents the maximum number of bytes of a block BKj of index j). Each branch can be considered as a delay line, the length of the branch of index i with i varying from 0 to I- 1, being equal to ixM bytes.
Ainsi, le premier bloc (ayant par exemple l'indice 0) de M octets n'est pas entrelacé et est délivré tel quel en sortie des moyens d'entrelacement. Le bloc suivant (ayant l'indice 1) de M octets est délivré à l'entrée de la branche BRI et ainsi de suite jusqu'à ce que le septième bloc de M octets (ayant l'indice 6) soit délivré à la branche BR6. Puis, le cycle recommence avec les blocs d'octets d'indices 7 à 13, les blocs d'octets précédents étant soit délivrés en sortie des moyens d'entrelacement, soit progressant d'un bloc "BKj dans la branche considérée.Thus, the first block (having for example the index 0) of M bytes is not interleaved and is delivered as is at the output of the interleaving means. The next block (having index 1) of M bytes is delivered to the entry of the BRI branch and so on until the seventh block of M bytes (having index 6) is delivered to the branch BR6. Then, the cycle begins again with the byte blocks of indices 7 to 13, the preceding byte blocks being either delivered at the output of the interleaving means, or progressing by a block " BKj in the branch considered.
Les moyens de désentrelacement associés à ces moyens d'entrelacement MET, et qui sont par conséquent incorporés dans le terminal utilisateur TU, ont une structure analogue à celle qui vient d'être décrite pour les moyens d'entrelacement, mais les indices de branches sont inversés de telle sorte que le plus grand retard d'entrelacement corresponde au plus petit retard de désentrelacement.The deinterleaving means associated with these interleaving means MET, and which are consequently incorporated in the user terminal TU, have a structure similar to that which has just been described for the interleaving means, but the branch indices are inverted so that the largest interleaving delay corresponds to the smallest deinterlacing delay.
En ce qui concerne les moyens de désentrelacement MDET incorporés dans le terminal de l'opérateur TO, ils comprennent I' branches, la branche d'indice i' ayant une longueur égale à i'xM' octets. Sur la figure 5, on a représenté à des fins de simplification I'≈I, mais bien entendu, si le service est un service asymétrique, I et I' sont généralement différents, de même que M et M'.As regards the MDET deinterleaving means incorporated in the operator terminal TO, they include the branches, the branch of index i 'having a length equal to i'xM' bytes. In FIG. 5, for the sake of simplification, I≈I has been shown, but of course, if the service is an asymmetrical service, I and I 'are generally different, as are M and M'.
Matériellement, comme illustré schematiquement sur la figure 6, les moyens d'entrelacement et les moyens de désentrelacement comprennent des moyens de mémoire communs MM, formés par exemple d'une mémoire vive à double accès. L'espace-mémoire de cette mémoire MM se décompose alors en un premier espace-mémoire ESMl alloué aux moyens d'entrelacement MET et en un deuxième espace-mémoire ESM2 alloué aux moyens de désentrelacement MDET. Les moyens d'entrelacement comportent par ailleurs des premiers moyens d'adressage MAD 1 recevant les paramètres I et M, tandis que les moyens de désentrelacement comportent des deuxièmes moyens d'adressage MAD2 recevant les paramètres I' et M'. La structure de ces moyens d'adressage sera décrite plus en détail ci-après en référence aux figures 7 et 8. La taille minimale de la mémoire MM est fixée en fonction du débit maximal pouvant être traité par le dispositif d'émission/réception. Par débit maximal, on entend bien entendu la somme du débit montant et du débit descendant. En l'espèce, le débit maximal est fourni ici par le plus grand service asymétrique A6.Materially, as illustrated diagrammatically in FIG. 6, the interleaving means and the deinterleaving means comprise common memory means MM, formed for example from a dual access random access memory. The memory space of this memory MM is then broken down into a first memory space ESM1 allocated to the interleaving means MET and into a second memory space ESM2 allocated to the deinterleaving means MDET. The interleaving means furthermore comprise first addressing means MAD 1 receiving the parameters I and M, while the deinterleaving means comprise second addressing means MAD2 receiving the parameters I 'and M'. The structure of these addressing means will be described in more detail below with reference to FIGS. 7 and 8. The minimum size of the memory MM is fixed as a function of the maximum bit rate that can be processed by the transmission / reception device. By maximum flow rate is understood, of course, the sum of the upward flow and the downward flow. In this case, the maximum speed is provided here by the largest asymmetric service A6.
On va maintenant donner, à titre d'exemple non limitatif, un exemple dé dimensionnement de la mémoire MM et du choix des paramètres I, M, I' et M' pour un service asymétrique A6 et un codage de Reed-Solomon RS (240, 224) avec un pouvoir de correction de 8 octets/mot et en faisant l'hypothèse que les lignes de transmission sont perturbées par un bruit impulsif de 0,250 ms.We will now give, by way of nonlimiting example, an example of dimensioning of the memory MM and of the choice of the parameters I, M, I 'and M' for an asymmetric service A6 and a coding of Reed-Solomon RS (240 , 224) with a correction power of 8 bytes / word and assuming that the transmission lines are disturbed by an impulsive noise of 0.250 ms.
Dans le sens descendant, le débit maximum est égal à 832x64 kbits/seconde. Le nombre de bits bruités est par conséquent égal au produit de ce débit par la durée du bruit impulsif, ce qui fournit un nombre de bits bruités égal à 13312 (1664 octets). Compte tenu du pouvoir correcteur du codage de Reed-Solomon (ici 8), le nombre nrs de mots de Reed-Solomon nécessaires pour corriger 1664 octets bruités est égal à 1664/8, soit 208. La taille de l'espace-mémoire pour stocker un tel débit maximum est alors égale à N.nrs/2 où N est la taille du codage de Reed-Solomon (ici 240).In the downward direction, the maximum bit rate is equal to 832x64 kbits / second. The number of noisy bits is therefore equal to the product of this bit rate by the duration of the impulsive noise, which gives a number of noisy bits equal to 13312 (1664 bytes). Given the corrective power of Reed-Solomon coding (here 8), the number nrs of Reed-Solomon words necessary to correct 1664 noisy bytes is equal to 1664/8, or 208. The size of the memory space for storing such a maximum bit rate is then equal to N.nrs / 2 where N is the size of the Reed-Solomon coding (here 240).
Il en résulte donc une taille de l'espace-mémoire correspondant égale à 24960 octets. Le débit dans le sens montant est égal à 32x64 kbits/seconde. Un calcul analogue montre que le nombre de bits bruités est égal à 512 et que nrs=8. Il en résulte alors une taille d'espace-mémoire à prévoir pour le sens montant égale à 1920 octets. La taille minimale de la mémoire MM est donc de 26880 octets. Compte tenu de ces tailles, il est possible de déterminer les paramètres I, I', M et M'. Plus précisément, la taille du premier espace- mémoire nécessaire pour mettre en oeuvre un entrelacement convolutif triangulaire à I branches de i-1 blocs de M octets est égale à Ix(I-l)xM/2. De même, la taille du deuxième espace-mémoire ESM2 destiné à supporter le débit montant est égale à I'x(I'-l)xM'/2. Par ailleurs, I et I' doivent être des sous-multiples de la taille N du codage de Reed-Solomon.This therefore results in a corresponding memory space size equal to 24960 bytes. The flow in the uplink direction is equal to 32x64 kbits / second. An analogous calculation shows that the number of noisy bits is equal to 512 and that nrs = 8. This then results in a memory space size to be provided for the uplink direction equal to 1920 bytes. The minimum size of the MM memory is therefore 26880 bytes. Given these sizes, it is possible to determine the parameters I, I ', M and M'. More precisely, the size of the first memory space necessary for implementing a triangular convolutional interleaving with I branches of i-1 blocks of M bytes is equal to Ix (II) xM / 2. Likewise, the size of the second memory space ESM2 intended to support the rising bit rate is equal to I'x (I'-l) xM '/ 2. Furthermore, I and I 'must be submultiples of the size N of the Reed-Solomon coding.
Puisque Ix(I-l)xM/2 doit être égale à 24960, il est possible de choisir 1=40 et M=32. De même, puisque I'x(I'-l)xM72 doit être au moins égale à 1920, il est possible de choisir (moyennant une légère augmentation de cette taille pour atteindre 1932 afin de faciliter l'implémentation) I'=24 et M'=7.Since Ix (I-l) xM / 2 must be equal to 24960, it is possible to choose 1 = 40 and M = 32. Similarly, since I'x (I'-l) xM72 must be at least equal to 1920, it is possible to choose (with a slight increase in this size to reach 1932 in order to facilitate implementation) I '= 24 and M '= 7.
La taille définitive de la mémoire MM est donc égale à 26892 octets. Le calcul de I, M, I' et M', qui vient d'être fait- our le service asymétrique A6, peut être. fait d'une façon analogue pour les autres services du système VDSL. On peut ainsi mémoriser dans l'étage de codage/décodage une table de valeurs pour les paramètres I, M, I' et M'. Lors de l'installation du modem en bout de ligne et en fonction du service effectivement fourni par l'opérateur, les moyens de contrôle MCD vont extraire de cette table mémorisée les valeurs correspondantes de I, M, l' et M', et les délivrer aux moyens d'adressage MAD1 et MAD2 dont la structure va maintenant être décrite plus en détail en se référant aux figures 7 et 8. Sur la figure 7, on voit que les premiers moyens d'adressage comprennent un premier compteur CT1 délivrant, au rythme d'un signal d'horloge, l'indice relatif i d'une branche BRi. Cet indice i est délivré à des moyens de calcul intermédiaires MCI qui déterminent l'adresse adbs de la branche BRi dans le premier espace-mémoire. Plus précisément, cette adresse adbs est égale à ix(i-l)/2. La structure de ces moyens MCI peut être aisément formée de nultiplieur, diviseur et soustracteur.The final size of the MM memory is therefore equal to 26892 bytes. The calculation of I, M, I 'and M', which has just been done for the asymmetric service A6, can be. does the same for the other services of the VDSL system. It is thus possible to store in the coding / decoding stage a table of values for the parameters I, M, I 'and M'. During the installation of the modem at the end of the line and according to the service actually provided by the operator, the control means MCD will extract from this stored table the corresponding values of I, M, l 'and M', and the deliver to the addressing means MAD1 and MAD2, the structure of which will now be described in more detail with reference to FIGS. 7 and 8. In FIG. 7, it can be seen that the first addressing means comprise a first counter CT1 delivering, to rhythm of a clock signal, the relative index i of a branch BRi. This index i is delivered to intermediate calculation means MCI which determine the address adbs of the branch BRi in the first memory space. More precisely, this adbs address is equal to ix (i-l) / 2. The structure of these MCI means can be easily formed of multiplier, divider and subtractor.
Le premier compteur CT1 a une plage de comptage égale à I et compte ainsi par exemple de 0 à 1-1.The first counter CT1 has a counting range equal to I and thus counts for example from 0 to 1-1.
Les moyens MD 1 comportent par ailleurs un deuxième compteur CT2 qui délivre une valeur courante m égale au nombre courant d'octets dans chaque bloque BKj d'une branche BRi. La plage de comptage de ce compteur CT2 est égale à M. En d'autres termes, m peut varier par exemple de 0 à M-l.The means MD 1 also comprise a second counter CT2 which delivers a current value m equal to the current number of bytes in each block BKj of a branch BRi. The counting range of this counter CT2 is equal to M. In other words, m can vary for example from 0 to M-1.
Le deuxième compteur CT2 est incrémenté d'une unité à chaque fois que i=I-l. Les moyens MDA1 comportent également un troisième compteur CT3, qui délivre l'indice j du bloc BKj de la branche d'indice i. La plage de comptage de ce compteur CT3 est égale à i. En d'autres termes, j varie par exemple de 0 à i- 1. Ce troisième compteur CT3 est incrémenté à chaque fois qu'un bloc contient M octets, c'est-à-dire en l'espèce à chaque fois par exemple que le compteur CT2 atteint la valeur M.The second counter CT2 is incremented by one each time i = Il. The means MDA1 also include a third counter CT3, which delivers the index j of the block BKj of the branch of index i. The counting range of this counter CT3 is equal to i. In other words, j varies for example from 0 to i- 1. This third counter CT3 is incremented each time a block contains M bytes, that is to say in this case each time for example that the counter CT2 reaches the value M.
Les moyens MDA1 comportent également des premiers moyens de détermination d'adresse MD1, qui déterminent l'adresse de lecture ar dans la mémoire et l'adresse d'écriture aw dans la mémoire. Plus précisément, l'adresse de lecture ar est égale à (adbs + j)xMThe means MDA1 also comprise first means for determining the address MD1, which determine the read address ar in the memory and the write address aw in the memory. More precisely, the reading address ar is equal to (adbs + j) xM
+ m.+ m.
L'adresse d'écriture aw est alors tout simplement égale à l'adresse de lecture, mais retardée d'un cycle du signal d'horloge.The write address aw is then simply equal to the read address, but delayed by one cycle of the clock signal.
Là encore, les moyens MD1 peuvent être aisément réalisables à partir d'additionneurs et de multiplieurs.Again, the means MD1 can be easily produced from adders and multipliers.
Par ailleurs, à titre d'exemple non limitatif, il est possible d'utiliser, pour stocker la valeur de l'indice j délivrée par le troisième compteur CT3, qui est incrémenté tous les M cycles d'horloge, une petite mémoire auxiliaire double accès dont la taille serait égale à (I-l)xM bits. Tous les M cycles d'horloge, la valeur du j correspond à la ième branche dans la mémoire auxiliaire, puis le compteur CT3 est incrémenté et la nouvelle valeur est réécrite à la même adresse.Furthermore, by way of nonlimiting example, it is possible to use, for storing the value of the index j delivered by the third counter CT3, which is incremented every M clock cycles, a small double auxiliary memory access whose size would be equal to (II) xM bits. Every M clock cycles, the value of j corresponds to the ith branch in the auxiliary memory, then the counter CT3 is incremented and the new value is rewritten at the same address.
La structure des deuxièmes moyens d'adresse MDA2 qui vont délivrer les adresses de lecture ar' et d'écriture aw' dans le deuxième espace-mémoire de la mémoire MM, ont une structure sensiblement analogue à celle qui vient d'être décrite pour les premiers moyens d'adresse MDA1. On va décrire ici que la différence entre les moyens MDA1 et les moyens MDA2.The structure of the second address means MDA2 which will deliver the addresses for reading ar 'and writing aw' in the second memory space of the memory MM, have a structure substantially similar to that which has just been described for the first address means MDA1. We will describe here only the difference between the means MDA1 and the means MDA2.
Le premier compteur CTIO délivre l'indice relatif i' d'une branche, i' varie cette fois-ci de I'-l à 0. Les moyens de calcul intermédiaires MCI délivrent l'adresse de chaque branche adbs' en utilisant une formule analogue à celle utilisée pour le calcul de l'adresse, mais en remplaçant i par i'.The first CTIO counter delivers the relative index i 'of a branch, i' varies this time from I'-l to 0. The intermediate calculation means MCI deliver the address of each branch adbs' using a formula similar to that used for the address calculation, but replacing i by i '.
Le deuxième compteur CT20 définit le nombre m' d'octets dans un bloc et est incrémenté à chaque fois que le compteur CT10 atteint sa valeur limite de comptage, en l'espèce lorsque i' atteint la valeur 0. Le deuxième compteur CT20 varie ici de 0 à M'-l.The second counter CT20 defines the number m 'of bytes in a block and is incremented each time the counter CT10 reaches its counting limit value, in this case when i 'reaches the value 0. The second counter CT20 varies here from 0 to M'-1.
Le troisième compteur CT30 définit l'indice courant j' d'un bloc dans la branche d'indice i'. Il varie de 0 à i'-l et est incrémenté à chaque fois qu'un bloc contient M' octets, c'est-à-dire lorsque le deuxième compteur CT20 a atteint la valeur M'.The third counter CT30 defines the current index j 'of a block in the branch of index i'. It varies from 0 to i'-1 and is incremented each time a block contains M 'bytes, that is to say when the second counter CT20 has reached the value M'.
Les deuxièmes moyens d'adressage MDA2 comportent des deuxièmes moyens de détermination d'adresse MD2 qui déterminent les adresses d'écriture aw' et ar'. Cependant, cette fόis-ci, les moyens MD2 doivent tenir compte de la taille du premier espace-mémoire ESMl , cette taille OF est définie par la formule (1) ci-dessous :The second addressing means MDA2 comprise second address determining means MD2 which determine the write addresses aw 'and ar'. However, this time, the means MD2 must take into account the size of the first memory space ESM1, this size OF is defined by the formula (1) below:
OF = Ix(I-l)xM/2 (1)OF = Ix (I-l) xM / 2 (1)
et est par exemple stockée dans un registre. En effet, pour l'entrelacement dans le sens montant, les adresses de la mémoire MM variaient de 0 à OF-and is for example stored in a register. Indeed, for interleaving in the uplink direction, the addresses of the memory MM varied from 0 to OF-
1.1.
La première adresse non occupée dans lamémoire MM vaut doncThe first unoccupied address in the MM memory is therefore worth
OF. Les moyens MD2 calculent alors l'adresse de lecture ar' selon la formule (2) ci-dessous :OF. The means MD2 then calculate the reading address ar 'according to the formula (2) below:
ar' = OF + M'x(adbs* + j') + m' (2)ar '= OF + M'x (adbs * + j') + m '(2)
L'adresse d'écriture aw' est égale à l'adresse de lecture et est disponible au coup d'horloge suivant.The write address aw 'is equal to the read address and is available at the next clock.
Bien entendu, tout ce qui vient d'être décrit ici pour le terminalOf course, everything just described here for the terminal
TO s'applique au terminal TU avec des moyens de désentrelacement à I branches et des moyens d'entrelacement à l' branches. Il convient alors de remplacer, en ce qui concerne le terminal utilisateur TU, I par I' et vice versa, et M par M' et vice versa, dans tout ce qui précède.TO applies to the terminal TU with deinterlacing means with I branches and interleaving means with the branches. It is then advisable to replace, with regard to the user terminal TU, I by I 'and vice versa, and M by M' and vice versa, in all of the above.
En outre, il serait également possible d'utiliser une mémoire simple accès à la place d'une mémoire double accès, en adoptant un signal d'horloge de fréquence double. . Furthermore, it would also be possible to use a single access memory in place of a dual access memory, by adopting a clock signal of double frequency. .

Claims

REVENDICATIONS
1. Dispositif d'émission/réception de données numériques, capable de traiter des débits différents pris parmi un groupe de débits prédéterminés, comprenant un étage de codage/décodage de canal comportant des moyens d'entrelacement (MET) et des moyens de désentrelacement (MDET) incluant une mémoire (MM) dont la taille minimale est fixée en fonction du débit maximal dudit groupe, et possédant un premier espace-mémoire (ESMl) alloué aux moyens d'entrelacement et un deuxième espace-mémoire (ESM2) alloué aux moyens de désentrelacement, la taille de chacun de ces deux espaces- mémoire étant paramétrable en fonction du débit effectivement traité par le dispositif.1. A device for transmitting / receiving digital data, capable of processing different bit rates taken from a group of predetermined bit rates, comprising a channel coding / decoding stage comprising interleaving means (MET) and deinterleaving means ( MDET) including a memory (MM) whose minimum size is fixed as a function of the maximum throughput of said group, and having a first memory space (ESMl) allocated to the interleaving means and a second memory space (ESM2) allocated to the means deinterlacing, the size of each of these two memory spaces being configurable as a function of the bit rate actually processed by the device.
2. Dispositif selon la revendication 1 , caractérisé par le fait que l'étage de codage/décodage de canal comportent des moyens de codage/ décodage de Reed-Solomon (CRS, DCRS) de longueur N, par le fait que les moyens d'entrelacement (MET) sont aptes à mettre en oeuvre un entrelacement convolutif à I branches de i-1 blocs de M octets, et les moyens de désentrelacement sont aptes à mettre en oeuvre un désentrelacement convolutif à l' branches de i'-l blocs de M' octets, I et I' étant des sous-multiples de N et i et i' les indices relatifs courants des branches, par le fait que la taille en octets du premier espace-mémoire est égal à Ix(I-l)xM/2 et la taille en octets du deuxième espace-mémoire est égal à I'x(I'-l)xM72, et par le fait que les tailles de ces deux espaces- mémoire sont paramétrables par I, I', M et M'.2. Device according to claim 1, characterized in that the channel coding / decoding stage comprises Reed-Solomon coding / decoding means (CRS, DCRS) of length N, by the fact that the means of interleaving (MET) are able to implement a convolutional interleaving with I branches of i-1 blocks of M bytes, and the deinterleaving means are capable of implementing a convolutive deinterlacing on the branches of i'l blocks of M 'bytes, I and I' being sub-multiples of N and i and i 'the current relative indices of the branches, by the fact that the size in bytes of the first memory space is equal to Ix (II) xM / 2 and the size in bytes of the second memory space is equal to I'x (I'-l) xM72, and by the fact that the sizes of these two memory spaces are configurable by I, I ', M and M'.
3. Dispositif selon la revendication 2, caractérisé par le fait que la mémoire (MM) est une mémoire vive en particulier à double accès, par le fait que les moyens d'entrelacement et de désentrelacement comprennent respectivement des premiers (MDA1) et des deuxièmes (MDA2) moyens d'adressage comportant chacun un premier compteur (CT1, CTIO) définissant l'indice relatif i ou i' d'une branche, un deuxième compteur (CT2, CT20) définissant le nombre d'octets dans un bloc et incrémenté à chaque fois que le premier compteur atteint sa valeur limite de comptage, un troisième compteur (CT3, CT30) définissant l'indice courant d'un bloc dans la branche d'indice i ou i', et incrémenté à chaque fois qu'un bloc contient M ou M' octets, des moyens de calcul intermédiaires (MCI) calculant l'adresse (adbs, adbs') de chaque branche dans ladite mémoire à partir du contenu du premier compteur, par le fait que les premiers moyens d'adressage (MDA1) comportent en outre des premiers moyens de détermination d'adresse (MDl) aptes à déterminer les adresses successives de lecture et d'écriture dans ladite mémoire, des données successivement délivrées aux moyens d'entrelacement, ces moyens (MDl) déterminant lesdites adresses à partir des valeurs fournies par les moyens de calcul intermédiaires (MCI), les deuxième et troisième compteurs (CT2, CT3), et à partir du paramètre M, et par le fait que les deuxièmes moyens d'adressage(MDA2) comportent en outre des deuxièmes moyens de détermination d'adresse3. Device according to claim 2, characterized in that the memory (MM) is a random access memory in particular with dual access, by the fact that the interleaving and deinterleaving means respectively comprise first (MDA1) and second (MDA2) addressing means each comprising a first counter (CT1, CTIO) defining the relative index i or i 'of a branch, a second counter (CT2, CT20) defining the number of bytes in a block and incremented each time the first counter reaches its counting limit value, a third counter (CT3, CT30) defining the current index of a block in the branch of index i or i ', and incremented each time a block contains M or M' bytes, intermediate calculation means ( MCI) calculating the address (adbs, adbs') of each branch in said memory from the content of the first counter, by the fact that the first addressing means (MDA1) further comprise first means of address determination (MDl) capable of determining the successive addresses for reading and writing in said memory, data successively delivered to the interleaving means, these means (MDl) determining said addresses from the values supplied by the intermediate calculation means (MCI ), the second and third counters (CT2, CT3), and from the parameter M, and by the fact that the second addressing means (MDA2) also comprise second address determination means
(MD2) aptes à déterminer les adresses successives de lecture et d'écriture dans ladite mémoire, des données successivement délivrées aux moyens de désentrelacement, ces moyens (MD2) déterminant lesdites adresses à partir des valeurs fournies par les moyens de calcul intermédiaires (MCI), les deuxième et troisième compteurs (CT20, CT30), à partir du paramètre(MD2) capable of determining the successive addresses for reading and writing in said memory, data successively delivered to the deinterleaving means, these means (MD2) determining said addresses from the values supplied by the intermediate calculation means (MCI) , the second and third counters (CT20, CT30), from the parameter
M' et de la taille (OF) du premier espace-mémoire. M 'and the size (OF) of the first memory space.
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US20030021338A1 (en) 2003-01-30

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