EP1301992A1 - Frequency synthesizer - Google Patents

Frequency synthesizer

Info

Publication number
EP1301992A1
EP1301992A1 EP01927073A EP01927073A EP1301992A1 EP 1301992 A1 EP1301992 A1 EP 1301992A1 EP 01927073 A EP01927073 A EP 01927073A EP 01927073 A EP01927073 A EP 01927073A EP 1301992 A1 EP1301992 A1 EP 1301992A1
Authority
EP
European Patent Office
Prior art keywords
circuit
phase
frequency
frequency synthesizer
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01927073A
Other languages
German (de)
French (fr)
Inventor
Ting-Kuang Chiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ciena Corp
Original Assignee
Ciena Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ciena Corp filed Critical Ciena Corp
Publication of EP1301992A1 publication Critical patent/EP1301992A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/025—Digital function generators for functions having two-valued amplitude, e.g. Walsh functions

Definitions

  • This invention relates generally to the field of frequency synthesizers, and more
  • Phase locked loops have been used to generate a clock pulse based on an input
  • the output clock pulse has a frequency which is a multiple of the input signal frequency.
  • the reference signal is divided by a conventional divider circuit and supplied to the PLL.
  • the divider circuit often divides the reference signal by an
  • M the output clock frequency has less granularity and cannot be finely
  • Phase accumulators have been used in alternative frequency synthesizer circuits.
  • synthesizer that includes, PA, discrete digital synthesizer, and a look-up table.
  • a simplified frequency synthesizer is needed that allows for a finely tuned frequency output with
  • the present invention provides a simplified frequency synthesizer circuit that uses the most significant bit output from a phase accumulator for input to a phase locked loop or bandwidth filter to generate a square wave having a precisely tuned frequency.
  • a frequency synthesizer consistent with the present invention includes a phase
  • Another frequency synthesizer consistent with the present invention includes a phase
  • phase locked loop for removing jitter from a signal processed by the phase
  • Another frequency synthesizer consistent with the present invention includes a phase
  • Fig. 1 is a block diagram of a frequency synthesizer according to the present invention
  • Fig. 2 is a circuit diagram of a frequency synthesizer as shown in Fig. 1 ;
  • Fig. 3 is a block diagram of a frequency synthesizer according to the present invention including a bandpass filter. IV. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • a synthesizer circuit generates a square wave for use as a clock signal, for example, based on the most significant bit (MSB) output from a
  • phase accumulator circuit phase accumulator circuit.
  • the MSB output however, often has jitter (a time varying phase fluctuation), which can be eliminated with a jitter adjustment circuit, such as a PLL or narrow
  • An MSB selector circuit is used to select and supply the MSB to the jitter
  • Fig. 1 is a block diagram of the present invention including a phase locked loop (PLL) 160 as the jitter adjusting circuit. As shown, a phase accumulator section (PAS) 100
  • PLL phase locked loop
  • PAS phase accumulator section
  • MSB selector 150 generates a signal that is output to a most significant bit (MSB) selector 150.
  • MSB 150 may be a bus or other connection coupling the MSB of PAS 100 with PLL
  • Fig. 2 is a more detailed circuit diagram of the system in Fig. 1 showing the frequency
  • synthesizer of the present invention including a phase accumulator section and a phase locked
  • reference clock f r 140 causes register 130 (including a DQ flip-flop, for example) to latch the value of adder circuit 120, which adds an N-byte (N being an
  • each reference clock period causes the phase value output from register 130 to increase linearly, creating a phase ramp.
  • accumulator value is determined by X. The output of register 130 will increase until a
  • phase value output will rollover to a minimum
  • An MSB selector circuit such as a bus or other connection, is coupled to an MSB selector circuit
  • PA 100 and resulting signal 135 typically cannot be used alone as a digital synthesizer
  • PLL 160 can be provided to reduce jitter and generate a stable output.
  • PLL 160 includes an
  • optional frequency divider circuit 162 a phase detector circuit 164, filter circuit 166, voltage
  • VCO control oscillator
  • signal divider circuit 162 and loop divider circuit 170 advantageously
  • MSB 155 is input to signal divider 162 which divides the frequency of signal 155 by
  • Phase detector 164 compares the output from divider 162 and a feed back
  • Filter 166 typically includes a low pass filter circuit that filters the signal output by the phase detector 164. In particular, filter 166 typically has a cutoff frequency lower than
  • VCO 168 is input to VCO 168, which then outputs a square wave signal 175 having frequency/,
  • PLL 160 outputs a stable square wave 175, which is also fed back to phase detector
  • granularity of output 175 is determined, at least in part, by phase increment X 110. Moreover, by appropriately choosing K, X and M, the frequency output from the PLL can
  • Fig. 3 illustrates an alternative embodiment of the present invention similar to Fig. 1.
  • bandpass filter circuit 300 advantageously has a relatively narrow bandwidth of about 1 kHz to thereby significantly reduce jitter.
  • the MSB is supplied via selector 150 to bandpass filter circuit 300 instead of PLL 160.
  • Bandpass filter circuit 300 advantageously has a relatively narrow bandwidth of about 1 kHz to thereby significantly reduce jitter.
  • the embodiment shown in Fig. 3 the
  • PA and PLL circuits may be used.

Abstract

Frequency synthesizer including a phase accumulator (200), a most significant bit selector (250) and a jitter adjusting circuit (260). The most significant bit selector passes the most significant bit of the output of the phase accumulator to a jitter adjusting circuit to remove jitter before outputting a square wave. The jitter adjusting circuit may be, for example, a phase locked loop or a bandpass filter.

Description

FREQUENCY SYNTHESIZER
I. BACKGROUND OF THE INVENTION
This invention relates generally to the field of frequency synthesizers, and more
specifically to the field of frequency synthesizers that generate square wave signals having a frequency greater than a reference frequency.
Phase locked loops (PLL) have been used to generate a clock pulse based on an input
or reference signal, whereby the output clock pulse has a frequency which is a multiple of the input signal frequency. In particular, the reference signal is divided by a conventional divider circuit and supplied to the PLL. The divider circuit often divides the reference signal by an
integer M. If M is small, the output clock frequency has less granularity and cannot be finely
tuned. If M is large, however, the signal supplied from the divider circuit has a relatively
long period and the PLL has a slow response time, during which the output of the PLL is susceptible to noise.
Phase accumulators (PA) have been used in alternative frequency synthesizer circuits.
For example, U.S. Patent No. 5,931,891 entitled "A Digital Frequency
Synthesizer", incorporated herein by reference, discloses a relatively complicated frequency
synthesizer that includes, PA, discrete digital synthesizer, and a look-up table. A simplified frequency synthesizer, however, is needed that allows for a finely tuned frequency output with
minimal noise.
II. SUMMARY OF THE INVENTION
The present invention provides a simplified frequency synthesizer circuit that uses the most significant bit output from a phase accumulator for input to a phase locked loop or bandwidth filter to generate a square wave having a precisely tuned frequency.
A frequency synthesizer consistent with the present invention includes a phase
accumulator, a most significant bit selector for selecting a most significant bit (MSB) from an
output of the phase accumulator, and a jitter adjusting circuit for processing the selected MSB.
Another frequency synthesizer consistent with the present invention includes a phase
accumulator, and a phase locked loop for removing jitter from a signal processed by the phase
accumulator.
Another frequency synthesizer consistent with the present invention includes a phase
accumulator, and a bandpass filter for removing jitter from a signal processed by the phase
accumulator.
III. BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the invention and, together with the description, serve to explain the
principles of the invention. In the drawings:
Fig. 1 is a block diagram of a frequency synthesizer according to the present invention
including a PLL;
Fig. 2 is a circuit diagram of a frequency synthesizer as shown in Fig. 1 ; and
Fig. 3 is a block diagram of a frequency synthesizer according to the present invention including a bandpass filter. IV. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Reference will now be made in detail to embodiments consistent with this invention
that are illustrated in the accompanying drawings. The same reference numbers in different
drawings generally refer to the same or like parts.
Consistent with the present invention, a synthesizer circuit generates a square wave for use as a clock signal, for example, based on the most significant bit (MSB) output from a
phase accumulator circuit. The MSB output, however, often has jitter (a time varying phase fluctuation), which can be eliminated with a jitter adjustment circuit, such as a PLL or narrow
bandpass filter. An MSB selector circuit is used to select and supply the MSB to the jitter
adjustment circuit.
Fig. 1 is a block diagram of the present invention including a phase locked loop (PLL) 160 as the jitter adjusting circuit. As shown, a phase accumulator section (PAS) 100
generates a signal that is output to a most significant bit (MSB) selector 150. MSB selector
150 selects the most significant bit from the output of the PAS 100. The MSB is input to PLL
160 which, using a series of received bits, generates a square wave 175 without significant jitter. MSB 150 may be a bus or other connection coupling the MSB of PAS 100 with PLL
160.
Fig. 2 is a more detailed circuit diagram of the system in Fig. 1 showing the frequency
synthesizer of the present invention including a phase accumulator section and a phase locked
loop. As seen in Fig. 2, reference clock fr 140 causes register 130 (including a DQ flip-flop, for example) to latch the value of adder circuit 120, which adds an N-byte (N being an
integer) integer phase increment value X 110 to the previous output value (the phase value) of register 30. In this manner, each reference clock period causes the phase value output from register 130 to increase linearly, creating a phase ramp. The rate of increase in the phase
accumulator value is determined by X. The output of register 130 will increase until a
maximum value is reached, at which point the phase value output will rollover to a minimum
value. With each rollover, the MSB toggles.
An MSB selector circuit, such as a bus or other connection, is coupled to an
appropriate output of register 130, and outputs the MSB. Since the MSB is changes between
a logic level "1" and "0", the resulting output from the MSB selector circuit constitutes a train
of square wave pulses shown as signal 135 in Fig. 2, and having a frequency/ defined as equation (1) follows:
PA 100 and resulting signal 135 typically cannot be used alone as a digital synthesizer
because signal 135 may contain jitter, a time-varying phase fluctuation. Accordingly, PLL 160 can be provided to reduce jitter and generate a stable output. PLL 160 includes an
optional frequency divider circuit 162, a phase detector circuit 164, filter circuit 166, voltage
control oscillator (VCO) circuit 168 and an optional loop frequency divider circuit 170.
Although not required, signal divider circuit 162 and loop divider circuit 170 advantageously
expand the range of frequencies that can be output from PLL 160 so that even frequencies greater than reference frequency fr can be output from PLL 160.
MSB 155 is input to signal divider 162 which divides the frequency of signal 155 by
an integer M. Phase detector 164 compares the output from divider 162 and a feed back
signal output from divider circuit 170, and outputs a signal that is a measure of the phase difference. Filter 166 typically includes a low pass filter circuit that filters the signal output by the phase detector 164. In particular, filter 166 typically has a cutoff frequency lower than
expected jitter components in the signal supplied from phase detector 164. The filtered signal
is input to VCO 168, which then outputs a square wave signal 175 having frequency/,
defined by equation (2) as:
KX
/ = /, (2)
M
PLL 160 outputs a stable square wave 175, which is also fed back to phase detector
164 via optional divide-by-K (K is an integer) circuit 170. As indicated in formula (2), the
granularity of output 175 is determined, at least in part, by phase increment X 110. Moreover, by appropriately choosing K, X and M, the frequency output from the PLL can
have a magnitude greater than frequency ...
Fig. 3 illustrates an alternative embodiment of the present invention similar to Fig. 1.
In Fig. 3, however, the MSB is supplied via selector 150 to bandpass filter circuit 300 instead of PLL 160. Bandpass filter circuit 300 advantageously has a relatively narrow bandwidth of about 1 kHz to thereby significantly reduce jitter. In the embodiment shown in Fig. 3, the
signal output from bandpass filter circuit 300 has a frequency defined by equation 3, below:
There are many variations that may be made consistent with the present invention. For example, different types of PA and PLL circuits may be used.
The foregoing description is presented for purposes of illustration and description. It
is not exhaustive and does not limit the invention to the precise form disclosed.
Modifications and variations are possible in light of the above teachings or may be acquired
from practicing the invention. The scope of the invention is defined by the claims and their
equivalents.

Claims

WHAT IS CLAIMED IS:
1. A frequency synthesizer circuit being configured to generate an output signal
having desired frequency comprising: a phase accumulator circuit being configured to receive a phase increment value, and
output a plurality of bits in response to said phase increment value;
a most significant bit selector circuit being configured to select a most significant bit
(MSB) from said plurality of bits; and a jitter adjusting circuit being configured to process said MSB, and supply said output
signal.
2. The frequency synthesizer of claim 1 wherein said jitter adjusting circuit is a
phase locked loop.
3. The frequency synthesizer of claim 2 wherein the phase locked loop includes:
a phase detector circuit being configured to receive the MSB and a feedback signal;
a filter circuit being configured to receive an output of the phase detector; and
a voltage controlled oscillator being configured to receive an output of said filter
circuit.
4. The frequency synthesizer of claim 3 wherein the filter has a cutoff frequency
lower than expected jitter components in a received signal.
5. The frequency synthesizer of claim 3 wherein said phase locked loop further includes:
a first divider circuit being coupled to said phase accumulator and being configured to
generate a first output signal having a first frequency equal to a frequency associated with
said MSB divided by M, said first divider circuit supplying said first output signal to said
phase detector circuit; and a second divider divider circuit being coupled to an output of said frequency
synthesizer and being configured to generate a second output signal having a second
frequency equal to said desired frequency divided by K, said second divider circuit supplying
said second output signal to said phase detector circuit.
6. The frequency synthesizer of claim 1 wherein said jitter adjusting circuit is a
bandpass filter.
7. The frequency synthesizer of claim 6 wherein the bandpass filter has a
bandwidth approximately equal to 1kHz.
8. The frequency synthesizer of claim 1 wherein the phase accumulator includes:
an adder circuit being configured to add said phase increment increment value with an
output of said phase accumulator circuit to thereby generate a sum signal; and
a register receiving a sum signal from said adder circuit and a reference clock.
9. The frequency synthesizer of claim 1 wherein the MSB selector is a bus.
EP01927073A 2000-07-10 2001-04-17 Frequency synthesizer Withdrawn EP1301992A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US61268900A 2000-07-10 2000-07-10
US612689 2000-07-10
PCT/US2001/012379 WO2002005431A1 (en) 2000-07-10 2001-04-17 Frequency synthesizer

Publications (1)

Publication Number Publication Date
EP1301992A1 true EP1301992A1 (en) 2003-04-16

Family

ID=24454236

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01927073A Withdrawn EP1301992A1 (en) 2000-07-10 2001-04-17 Frequency synthesizer

Country Status (3)

Country Link
EP (1) EP1301992A1 (en)
CA (1) CA2378338A1 (en)
WO (1) WO2002005431A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2399241B (en) * 2003-03-06 2006-04-12 Ifr Ltd Improved waveform generation
CN103873052A (en) * 2012-12-12 2014-06-18 普诚科技股份有限公司 Value control oscillator and digital phase locked loop

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0630129A2 (en) * 1993-06-09 1994-12-21 Alcatel SEL Aktiengesellschaft Method for generating a synchronised clock signal with a circuit for an adjustable oscillator
AU6339594A (en) * 1993-06-09 1994-12-15 Alcatel N.V. Synchronized clock
KR960016812B1 (en) * 1994-11-26 1996-12-21 재단법인 한국전자통신연구소 Hybrid frequency synthesizer
US5651035A (en) * 1995-04-28 1997-07-22 International Microcircuits, Inc. Apparatus for reducing jitter of a spectrum spread clock signal and method therefor
DE19653022C2 (en) * 1996-12-19 1999-08-19 Bosch Gmbh Robert Frequency synthesizer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0205431A1 *

Also Published As

Publication number Publication date
CA2378338A1 (en) 2002-01-17
WO2002005431A1 (en) 2002-01-17

Similar Documents

Publication Publication Date Title
US6704381B1 (en) Frequency acquisition rate control in phase lock loop circuits
US7881419B2 (en) Semiconductor device, spread spectrum clock generator and method thereof
EP1434352B1 (en) Delay-compensated fractional-N frequency synthesizer
KR20070009749A (en) Adaptive frequency calibration apparatus of frequency synthesizer
US4506233A (en) Bandwidth control circuit for a phase locked loop
US6657464B1 (en) Method and circuit to reduce jitter generation in a PLL using a reference quadrupler, equalizer, and phase detector with control for multiple frequencies
US7504893B2 (en) System and method for reducing transient responses in a phase lock loop with variable oscillator gain
US6833764B1 (en) Apparatus and method for synthesizing a frequency using vernier dividers
CN111416616B (en) PLL with wide frequency coverage
EP0929940B1 (en) Frequency synthesizer having phase error feedback for waveform selection
US20070176697A1 (en) Controllable oscillator with output oscillation adjustment and method for producing an output oscillation for use therewith
US7583773B2 (en) Frequency synthesizing device with automatic calibration
EP0755120A1 (en) Phase-locked loop circuit
US7202750B2 (en) Controllable phase locked loop via adjustable delay and method for producing an output oscillation for use therewith
EP1301992A1 (en) Frequency synthesizer
US6538520B1 (en) Methods and apparatus for producing a reference frequency signal with use of a reference frequency quadrupler having frequency selection controls
US20060208814A1 (en) Low phase noise crystal oscillator with supply noise filtering
EP0697151B1 (en) Numerically controlled oscillator and digital phase locked loop
US5604774A (en) Fully secondary DPLL and destuffing circuit employing same
US7088797B2 (en) Phase lock loop with cycle drop and add circuitry
EP0881775A1 (en) A clock generator
US7574185B2 (en) Method and apparatus for generating a phase-locked output signal
US5349613A (en) Digital phase locked loop, and digital oscillator arranged to be used in the digital phase locked loop
AU750763B2 (en) Frequency synthesiser
JP3230501B2 (en) Frequency synthesizer

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20030210

AK Designated contracting states

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

RIN1 Information on inventor provided before grant (corrected)

Inventor name: CHIANG, TING-KUANG

RBV Designated contracting states (corrected)

Designated state(s): AT BE CH CY DE FR GB IT LI

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20050713