EP1301350A1 - Print engine/controller to work in multiples and a printhead driven by multiple print engine/controllers - Google Patents
Print engine/controller to work in multiples and a printhead driven by multiple print engine/controllersInfo
- Publication number
- EP1301350A1 EP1301350A1 EP00938327A EP00938327A EP1301350A1 EP 1301350 A1 EP1301350 A1 EP 1301350A1 EP 00938327 A EP00938327 A EP 00938327A EP 00938327 A EP00938327 A EP 00938327A EP 1301350 A1 EP1301350 A1 EP 1301350A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- printhead
- print engine
- data
- controller
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/46—Colour picture communication systems
- H04N1/52—Circuits or arrangements for halftone screening
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/387—Composing, repositioning or otherwise geometrically modifying originals
- H04N1/3871—Composing, repositioning or otherwise geometrically modifying originals the composed originals being of different kinds, e.g. low- and high-resolution originals
Definitions
- the invention relates to a print engine/controller adapted to work together with a number of print engine/controllers in driving a printhead and to a printhead driven by multiple print engine/controllers.
- the Memjet printhead is developed from printhead segments that are capable of producing, for example, 1600 dpi bi-level dots of liquid ink across the full width of a page. Dots are easily produced in isolation, allowing dispersed-dot dithering to be exploited to its fullest. Color planes might be printed in perfect registration, allowing ideal dot-on-dot printing.
- the printhead enables high-speed printing using microelectromechanical ink drop technology.
- PCT/AU00/00516, PCT/AU00/00517, PCT/AUOO/00511, and PCT/AU00/00755, PCT/AU00/00756 and PCT/AU00/00757 describe a print engine/controller suited to driving the above referenced page wide printhead.
- a single print engine/controller (PEC) chip is capable of driving a printhead of the above referenced type, printing a dithered version of a 320ppi contone image over a 12 inch printhead. It is desirable to be able to print higher resolution images for higher quality output. It is desirable to be able to run the printhead faster.
- a print engine/controller configured to be coupled with others to drive an ink drop printhead comprising: an interface at which to receive compressed page data; image decoders to decode compressed image planes in the received compressed page data; a half-toner/compositer to composite respective strips of the decoded image planes; and a printhead interface to output the composite strip to a printhead the printhead interface including: a multi-segment printhead interface outputting printhead formatted data; and a synchronization signal generator outputting a synchronization signal to couple print engine/controllers to synchronize their respective strips at the printhead.
- a Memjet printhead is a multi-segment printhead, where each segment of the printhead has physical connections.
- Memjet printheads can be constructed from multiple chips, each of which contains a single printhead segment, or can be constructed from multiple chips each of which contains more than one segment.
- the wiring is the same in both cases, and the logical connectivity is the same in both cases - multiple segments combining to form a wider printhead.
- the present invention advantageously uses multiple copies of the same print engine controller chip to drive a multi-segment printhead, each responsible for a strip of the page, all synchronized from a master chip.
- a variety of configurations can be built depending on the required application.
- a single print engine/controller can be used to run the entire printhead at a contone resolution of 320 ppi and at a maximum line speed of 30,000 lines per second. If double speed is to be achieved, 2 PECs can control 6 segments each, still running at 320 ppi contone resolution. But the effective speed has been doubled.
- Synchronization can also be readily used for simultaneous duplex printing.
- One PEC prints 12 inches (15 segments) on one side of a page, while a second PEC simultaneously prints the second side of the page.
- a single Master PEC chip giving the synchronization signals combinations of PECs can be achieved.
- the same page can be given to multiple PECs.
- Different PECs then deal with strips of the page data, producing the total page in a faster time and/or higher resolution.
- a simple way of sending data to the printhead from multiple PECs is simply to have each PEC responsible for a given number of printhead segments.
- the programming of individual PECs for strips within the overall page is organized in a margin unit within a half-toner/compositer within each PEC.
- a tag encoder within each print engine/controller is able to deal with a strip of a page and is capable of producing a partial tag when tagged pages are desirable.
- PECs When several PECs are used in unison, such as in a duplexed configuration or in a printhead configuration that consists of more than 15 Memjet segments, they are synchronized via a shared line sync signal. Only one Printhead Controller Chip, selected via an external master/slave pin, generates the line sync signal onto the shared line.
- the internals of PEC allow for printing a single strip of a page in conjunction with other PECs. This includes generation of partial Netpage tags and page descriptions. However it is up to the external page provider to allocate the various strips to each PEC correctly.
- FIG. 1 is a diagram illustrating data flow and the functions performed by the print engine controller.
- FIG. 2 shows the print engine controller in the context of the overall printer system architecture.
- FIG. 3 illustrates the print engine controller architecture.
- FIG. 4 illustrates the external interfaces to the halftoner/compositor unit (HCU) of FIG. 3.
- FIG. 5 is a diagram showing internal circuitry to the HCU of FIG. 4.
- FIG. 6 shows a block diagram illustrating the process within the dot merger unit of FIG. 5.
- FIG. 7 shows a diagram illustrating the process within the dot reorganization unit of FIG. 5.
- FIG. 8 shows a diagram illustrating the process within the line loader/format unit (LLFU) of FIG. 5.
- LLFU line loader/format unit
- FIG. 9 is a diagram showing internal circuitry to generate color data in the LLFU of FIG. 8.
- FIGs. 10 and 11 illustrate components of the LLFU seen in FIG. 9.
- FIG. 12 is a diagram showing internal circuitry to a printhead interface.
- FIG. 13 is a diagram of a dot counter used in the printhead interface.
- a typically 12 inch printhead width is controlled by one or more print engine/controllers (PECs), as described below, to allow full-bleed printing of both A4 and Letter pages.
- PECs print engine/controllers
- Six channels of colored ink are the expected maximum in the present printing environment, these being: • CMY, for regular color printing.
- the printer is to be capable of fast printing, a fixative will be required to enable the ink to dry before the next page has completed printing at higher speeds. Otherwise the pages might bleed on each other. In lower speed printing environments the fixative will not be required.
- a PEC might be built in a single chip to interface with a printhead. It will contain four basic levels of functionality:
- the print engine functionality includes expanding the page image, dithering the contone layer, compositing the black layer over the contone layer, optionally adding infrared tags, and sending the resultant image to the printhead.
- FIG. 1 is seen the flow of data to send a document from computer system to printed page.
- a document is received at 11 and loaded to memory buffer 12 wherein page layouts may be effected and any required objects might be added.
- Pages from memory 12 are rasterized at 13 and compressed at 14 prior to transmission to the print engine controller 10. Pages are received as compressed page images within the print engine controller 10 into a memory buffer 15, from which they are fed to a page expander 16 wherein page images are retrieved. Any requisite dither might be applied to any contone layer at 17. Any black bi-level layer might be composited over the contone layer at 18 together with any infrared tags at 19. The composited page data is printed at 20 to produce page 21.
- the print engine/controller takes the compressed page image and starts the page expansion and printing in pipeline fashion.
- Page expansion and printing is preferably pipelined because it is impractical to store a sizable bi-level CMYK+IR page image in memory.
- the first stage of the pipeline expands a JPEG-compressed contone CMYK layer (see below), expands a Group 4 Fax-compressed bi-level dither matrix selection map (see below), and expands a Group 4 Fax- compressed bi-level black layer (see below), all in parallel.
- the tag encoder encodes bi- level IR tag data from the compressed page image.
- the second stage dithers the contone CMYK layer using a dither matrix selected by the dither matrix select map, composites the bi-level black layer over the resulting bi- level K layer and adds the IR layer to the page.
- a fixative layer is also generated at each dot position wherever there is a need in any of C, M, Y, K, or IR channels.
- the last stage prints the bi-level CMYK+IR data through the printhead via a printhead interface (see below).
- FIG. 2 is seen how the print engine/controller 10 fits within the overall printer system architecture.
- the various components of the printer system might include
- a PEC chip 10 is responsible for receiving the compressed page images for storage in a memory buffer 24, performing the page expansion, black layer compositing and sending the dot data to the printhead 23. It may also communicate with QA chips 25,26 and provides a means of retrieving printhead characteristics to ensure optimum printing.
- the PEC is the subject of this specification.
- the memory buffer 24 is for storing the compressed page image and for scratch use during the printing of a given page.
- the construction and working of memory buffers is known to those skilled in the art and a range of standard chips and techniques for their use might be utilized in use of the PEC of the invention.
- a master QA chip • a master QA chip.
- the master chip 25 is matched to replaceable ink cartridge QA chips 26.
- the construction and working of QA units is known to those skilled in the art and a range of known QA processes might be utilized in use of the PEC of the invention.
- a QA chip is described in co-pending United States Patent Applications:
- QA chip communication may be best included within the overall functionality of the PEC chip since it has a role in the expansion of the image as well as running the physical printhead. By locating QA chip communication there it can be ensured that there is enough ink to print the page.
- the QA embedded in the printhead assembly is implemented using ah authentication chip. Since it is a master QA chip, it only contains authentication keys, and does not contain user-data. However, it must match the ink cartridge's QA chip.
- the QA chip in the ink cartridge contains information required for maintaining the best possible print quality, and is implemented using an authentication chip.
- a 64 MBit (8 MByte) memory buffer is used to store the compressed page image. While one page is being written to the buffer another is being read (double buffering).
- the PEC uses the memory to buffer the calculated dot information during the printing of a page. During the printing of page N, the buffer is used for: • Reading compressed page N
- a PEC chip will incorporate a simple micro-controller CPU core 35 to perform the following functions:
- the CPU Since all of the image processing is performed by dedicated hardware, the CPU does not have to process pixels. As a result, the CPU can be extremely simple.
- a wide variety of CPU known cores are suitable: it can be any processor core with sufficient processing power to perform the required calculations and control functions fast enough.
- An example of a suitable core is a Philips 8051 micro-controller running at about 1 MHz.
- Associated with the CPU core 35 may be a program ROM and a small program scratch RAM.
- the CPU communicates with the other units within the PEC chip via memory-mapped I/O. Particular address ranges may map to particular units, and within each range, to particular registers within that particular unit. This includes the serial 36 and parallel 91 interfaces.
- a small program flash ROM may be incorporated into the PEC chip.
- RAM size depends on the CPU chosen, but should not be more than 8KB. Likewise, a small scratch RAM area can be incorporated into the PEC chip. Since the program code does not have to manipulate images, there is no need for a large scratch area.
- the RAM size depends on the CPU chosen (e.g. stack mechanisms, subroutine calling conventions, register sizes etc.), but should not be more than about 2 KB.
- a PEC chip using the above referenced segment based page wide printhead can reproduce black at a full dot resolution (typically 1600 dpi), but reproduces contone color at a somewhat lower resolution using halftoning.
- the page description is therefore divided into a black bi-level layer and a contone layer.
- the black bi-level layer is defined to composite over the contone layer.
- the black bi-level layer consists of a bitmap containing a 1-bit opacity for each pixel.
- This black layer matte has a resolution that is an integer factor of the printer's dot resolution.
- the highest supported resolution is 1600 dpi, i.e. the printer's full dot resolution.
- the contone layer consists of a bitmap containing a 32-bit CMYK color for each pixel, where K is optional.
- This contone image has a resolution that is an integer factor of the printer's dot resolution.
- the highest supported resolution is 320 ppi over 12 inches for a single PEC, i.e. one-fifth the printer's dot resolution.
- multiple PECs are required, with each PEC producing an strip of the output page.
- the contone resolution is also typically an integer factor of the black bi-level resolution, to simplify calculations in the RBPs. This is not a requirement, however.
- the black bi-level layer and the contone layer are both in compressed form for efficient storage in the printer's internal memory.
- the print engine's page expansion and printing pipeline consists of a high speed serial interface 27 (such as a standard IEEE 1394 interface), a standard JPEG decoder 28, a standard Group 4 Fax decoder, a custom halftoner/compositor unit 29, a custom tag encoder 30, a line loader/formatter unit 31, and a custom interface 32 to the printhead 33.
- the decoders 28,88 and encoder 30 are buffered to the halftoner/compositor 29.
- the tag encoder 30 establishes an infrared tag or tags to a page according to protocols dependent on what uses might be made of the page and the actual content of a tag is not the subject of the present invention.
- the print engine works in a double buffered way.
- One page is loaded into DRAM 34 via DRAM interface 89 and data bus 90 from the high speed serial interface 27 while the previously loaded page is read from DRAM 34 and passed through the print engine pipeline.
- the page just loaded becomes the page being printed, and a new page is loaded via the high-speed serial interface 27.
- the pipeline expands any JPEG-compressed contone (CMYK) layer, and expands any of two Group 4 Fax-compressed bi-level data streams.
- CMYK JPEG-compressed contone
- the two streams are the black layer (although the PEC is actually color agnostic and this bi-level layer can be directed to any of the output inks), and a matte for selecting between dither matrices for contone dithering (see below).
- the second stage in parallel with the first, is encoded any tags for later rendering in either IR or black ink.
- the third stage dithers the contone layer, and composites position tags and the bi-level spotl layer over the resulting bi-level dithered layer.
- the data stream is ideally adjusted to create smooth transitions across overlapping segments in the printhead and ideally it is adjusted to compensate for dead nozzles in the printhead. Up to 6 channels of bi-level data are produced from this stage.
- the printhead may be CMY only, with K pushed into the CMY channels and IR ignored.
- the position tags may be printed in K if IR ink is not available (or for testing purposes).
- the resultant bi-level CMYK-IR dot-data is buffered and formatted for printing on the printhead 33 via a set of line buffers (see below). The majority of these line buffers might be ideally stored on the off-chip DRAM 34.
- the final stage prints the 6 channels of bi- level dot data via the printhead interface 32.
- Compression is used in a printing system that employs the PEC. This is to reduce bandwidth requirements between a host and PEC, as well as to reduce memory requirements for page storage.
- a Letter page of contone CMYK data has a size of 25MB.
- lossy contone compression algorithms such as JPEG (see below)
- contone images compress with a ratio up to 10:1 without noticeable loss of quality, giving a compressed page size of 2.5MB.
- a Letter page of bi-level data has a size of 7MB.
- Coherent data such as text compresses very well.
- CMYK contone image data consists of 114MB of bi-level data.
- the two-layer compressed page image format described below exploits the relative strengths of lossy JPEG contone image compression and lossless bi-level text compression.
- the format is compact enough to be storage-efficient, and simple enough to allow straightforward real-time expansion during printing. Since text and images normally don't overlap, the normal worst-case page image size is 2.5MB (i.e. image only), while the normal best-case page image size is 0.8MB (i.e. text only).
- the absolute worst-case page image size is 3.3MB (i.e. text over image). Assuming a quarter of an average page contains images, the average page image size is 1.2MB.
- a Group 3 Facsimile compression algorithm (see ANSI EIA 538-1988, Facsimile Coding Schemes and Coding Control Functions for Group 4 Facsimile Equipment, August 1988) can be used to losslessly compresses bi-level data for transmission over slow and noisy telephone lines.
- the bi-level data represents scanned black text and graphics on a white background, and the algorithm is tuned for this class of images (it is explicitly not tuned, for example, for halftoned bi-level images).
- the ID Group 3 algorithm runlength-encodes each scanline and then Huffman-encodes the resulting runlengths. Runlengths in the range 0 to 63 are coded with terminating codes. Runlengths in the range 64 to 2623 are coded with make-up codes, each representing a multiple of 64, followed by a terminating code. Runlengths exceeding 2623 are coded with multiple make-up codes followed by a terminating code.
- the Huffman tables are fixed, but are separately tuned for black and white runs (except for make-up codes above 1728, which are common).
- the 2D Group 3 algorithm encodes a scanline as a set of short edge deltas (0, ⁇ 1 , ⁇ 2, ⁇ 3) with reference to the previous scanline.
- the delta symbols are entropy-encoded (so that the zero delta symbol is only one bit long etc.) Edges within a 2D-encoded line that can't be delta-encoded are ranlength-encoded, and are identified by a prefix. ID- and 2D- encoded lines are marked differently. ID-encoded lines are generated at regular intervals, whether actually required or not, to ensure that the decoder can recover from line noise with minimal image degradation. 2D
- Group 3 achieves compression ratios of up to 6:1 (see Urban, S.J., "Review of standards for electronic imaging for facsimile systems", Journal of Electronic Imaging, Vol.1(1), January 1992, pp.5-21).
- a Group 4 Facsimile algorithm (see ANSFEIA 538-1988, Facsimile Coding Schemes and Coding Control Functions for Group 4 Facsimile Equipment, August 1988) losslessly compresses bi-level data for transmission over error-free communications lines (i.e. the lines are truly error-free, or error-correction is done at a lower protocol level).
- the Group 4 algorithm is based on the 2D Group 3 algorithm, with the essential modification that since transmission is assumed to be error-free, ID-encoded lines are no longer generated at regular intervals as an aid to error-recovery.
- Group 4 achieves compression ratios ranging from 20:1 to 60:1 for the CCITT set of test images.
- the design goals and performance of the Group 4 compression algorithm qualify it as a compression algorithm for the bi-level layers. However, its Huffman tables are tuned to a lower scanning resolution (100-400 dpi), and it encodes runlengths exceeding 2623 awkwardly. At 800 dpi, our maximum runlength is currently 6400. Although a Group 4 decoder core would be available for use in PEC, it might not handle runlengths exceeding those normally encountered in 400 dpi facsimile applications, and so would require modification.
- the (typically 1600 dpi) black layer is losslessly compressed using G4Fax at a typical compression ratio exceeding 10:1.
- a (typically 320dpi) dither matrix select layer, which matches the contone color layer, is losslessly compressed using G4Fax at a typical compression ratio exceeding 50:1.
- the Group 4 Fax (G4 Fax) decoder is responsible for decompressing bi-level data.
- Bi-level data is limited to a single spot color (typically black for text and line graphics), and a dither matrix select bit-map for use in subsequent dithering of the contone data (decompressed by the JPEG decoder).
- the input to the G4 Fax decoder is 2 planes of bi-level data, read from the external DRAM.
- the output of the G4 Fax decoder is 2 planes of decompressed bi-level data.
- the decompressed bi-level data is sent to the Halftoner/Compositor Unit (HCU) for the next stage in the printing pipeline.
- HCU Halftoner/Compositor Unit
- Two bi-level buffers provides the means for transferring the bi-level data between the G4 Fax decoder and the HCU.
- Each decompressed bi-level layer is output to two line buffers.
- Each buffer is capable of holding a full 12 inch line of dots at the expected maximum resolution. Having two line buffers allows one line to be read by the HCU while the other line is being written to by the G4
- Fax decoder This is important because a single bi-level line is typically less than 1600 dpi, and must therefore be expanded in both the dot and line dimensions. If the buffering were less than a full line, the G4 Fax decoder would have to decode the same line multiple times - once for each output 600dpi dotline.
- Spot color 1 is designed to allow high resolution dot data for a single color plane of the output image.
- each of the two line buffers is therefore 480 bytes (3840 bits), capable of storing 12 inches at 320 dpi.
- the typical compression ratio exceeds 50: 1.
- the decompression bandwidth requirements are 9.05 MB/sec for 1 page per second performance (regardless of whether the page width is 12 inches or 8.5 inches), and 20 MB/sec and 14.2 MB/sec for 12 inch and 8.5 inch page widths respectively during maximum printer speed performance (30,000 lines per second).
- the G4 Fax decoder can readily decompress a line from each of the outputs one at a time.
- the G4 Fax decoder is fed directly from the main memory via the DRAM interface.
- the amount of compression determines the bandwidth requirements to the external DRAM. Since G4 Fax is lossless, the complexity of the image impacts on the amount of data and hence the bandwidth, typically an 800 dpi black text/graphics layer exceeds 10:1 compression, so the bandwidth required to print 1 page per second is 0.78 MB/sec.
- a typical 320 dpi dither select matrix compresses at more than 50:1, resulting in a 0.025 MB/sec bandwidth.
- the fastest printing speed configuration of 320 dpi for dither select matrix and 800 dpi for spot color 1 requires bandwidth of 1.72 MB/sec and 0.056 MB/sec respectively. A total bandwidth of 2 MB/sec should therefore be more than enough for the DRAM bandwidth.
- G4 Fax decoding functionality is implemented by means of a G4 Fax Decoder core.
- G4Fax Decoder cores can be any core with sufficient processing power to perform the required calculations and control functions fast enough. It must be capable of handling runlengths exceeding those normally encountered in 400 dpi facsimile applications, and so may require modification.
- JPEG compression algorithm (see ISO/IEC 19018-1:1994, Information technology - Digital compression and coding of continuous-tone still images: Requirements and guidelines, 1994) lossily compresses a contone image at a specified quality level. It introduces imperceptible image degradation at compression ratios below 5:1, and negligible image degradation at compression ratios below 10:1 (see Wallace, G.K., "The JPEG Still Picture Compression Standard", Communications of the ACM, Vol.34, No.4, April 1991, pp.30-44). JPEG typically first transforms the image into a color space that separates luminance and chrominance into separate color channels.
- each color channel is compressed separately.
- the image is divided into 8x8 pixel blocks.
- Each block is then transformed into the frequency domain via a discrete cosine transform (DCT).
- DCT discrete cosine transform
- CMYK (or CMY) contone layer is compressed to a planar color JPEG bytestream. If luminance/chrominance separation is deemed necessary, either for the purposes of table sharing or for chrominance sub-sampling, then CMYK is converted to YCrCb and Cr and Cb are duly sub-sampled.
- the JPEG bytestream is complete and self-contained. It contains all data required for decompression, including quantization and Huffman tables.
- the JPEG decoder is responsible for performing the on-the-fiy decompression of the contone data layer.
- the input to the JPEG decoder is up to 4 planes of contone data. This will typically be 3 planes, representing a CMY contone image, or 4 planes representing a CMYK contone image. Each color plane can be in a different resolution, although typically all color planes will be the same resolution.
- the contone layers are read from the external DRAM.
- the output of the JPEG decoder is the decompressed contone data, separated into planes.
- the decompressed contone image is sent to the halftoner/compositor unit (HCU) 29 for the next stage in the printing pipeline.
- the 4-plane contone buffer provides the means for transferring the contone data between the JPEG decoder and the HCU 29.
- Each color plane of the decompressed contone data is output to a set of two line buffers (see below).
- Each line buffer is 3840 bytes, and is therefore capable of holding 12 inches of a single color plane's pixels at 320 ppi.
- the line buffering allows one line buffer to be read by the HCU while the other line buffer is being written to by the JPEG decoder. This is important because a single contone line is typically less than 1600 ppi, and must therefore be expanded in both the dot and line dimensions. If the buffering were less than a full line, the JPEG decoder would have to decode the same line multiple times - once for each output 600dpi dotline. Although a variety of resolutions is supported, there is a tradeoff between the resolution and available bandwidth.
- each color plane can be stored at a different resolution (for example CMY may be a higher resolution than the K plane).
- the highest supported contone resolution is 1600ppi (matching the printer's full dot resolution).
- the decompression output bandwidth requirements are 40 MB/sec for 1 page per second performance (regardless of whether the page width is 12 inches or 8.5 inches), and 88 MB/sec and 64 MB/sec for 12 inch and 8.5 inch page widths respectively during maximum printer speed performance (30,000 lines per second).
- the JPEG decoder is fed directly from the main memory via the DRAM interface.
- the amount of compression determines the bandwidth requirements to the external DRAM. As the level of compression increases, the bandwidth decreases, but the quality of the final output image can also decrease.
- the DRAM bandwidth for a single color plane can be readily calculated by applying the compression factor to the output bandwidth. For example, a single color plane at 320 ppi with a compression factor of 10:1 requires IMB/sec access to DRAM to produce a single page per second.
- JPEG functionality is implemented by means of a JPEG core.
- JPEG cores can be any JPEG core with sufficient processing power to perform the required calculations and control functions fast enough.
- the BTG X-Match core has decompression speeds up to 140 MBytes/sec, which allows decompression of 4 color planes at contone resolutions up to 400ppi for the maximum printer speed (30,000 lines at 1600dpi per second), and 800ppi for 1 page/sec printer speed.
- the core needs to only support decompression, reducing the requirements that are imposed by more generalized JPEG compression/decompression cores.
- the size of the core is expected to be no more than 100,000 gates.
- the JPEG decoder can readily decompress an entire line for each of the color planes one at a time, thus saving on context switching during a line and simplifying the control of the JPEG decoder.
- 4 contexts must be kept (1 context for each color plane), and includes current address in the external DRAM as well as appropriate JPEG decoding parameters.
- the halftoner/compositor unit (HCU) 29 combines the functions of halftoning the contone (typically CMYK) layer to a bi-level version of the same, and compositing the spotl bi-level layer over the appropriate halftoned contone la er(s). If there is no K ink in the printer, the HCU 29 is able to map K to CMY dots as appropriate. It also selects between two dither matrices on a pixel by pixel basis, based on the corresponding value in the dither matrix select map.
- CMYK contone
- the HCU 29 is able to map K to CMY dots as appropriate. It also selects between two dither matrices on a pixel by pixel basis, based on the corresponding value in the dither matrix select map.
- the input to the HCU 29 is an expanded contone layer (from the JPEG decoder unit) through buffer 37, an expanded bi-level spotl layer through buffer 38, an expanded dither-matrix-select bitmap at typically the same resolution as the contone layer through buffer 39, and tag data at full dot resolution through buffer 40.
- the HCU 29 uses up to two dither matrices, read from the external DRAM 34.
- the output from the HCU 29 to the line loader/format unit (LLFU) at 41 is a set of printer resolution bi-level image lines in up to 6 color planes.
- the contone layer is CMYK or CMY
- the bi-level spotl layer is K.
- the HCU in greater detail. Once started, the HCU proceeds until it detects an end-of- page condition, or until it is explicitly stopped via its control register.
- the first task of the HCU is to scale, in the respective scale units such as the scale unit 43, all data, received in the buffer planes such as 42, to printer resolution both horizontally and vertically.
- the scale unit provides a means of scaling contone or bi-level data to printer resolution both horizontally and vertically. Scaling is achieved by replicating a data value an integer number of times in both dimensions. Processes by which to scale data will be familiar to those skilled in the art.
- the advance dot bit allows the state machine to generate multiple instances of the same dot data (useful for page margins and creating dot data for overlapping segments in the printhead).
- the advance line bit allows the state machine to control when a particular line of dots has been finished, thereby allowing truncation of data according to printer margins. It also saves the scale unit from requiring special end-of-line logic.
- the input to the scale unit is a full line buffer.
- the line is used scale factor times to effect vertical up-scaling via line replication, and within each line, each value is used scale factor times to effect horizontal up-scaling via pixel replication.
- the input buffer select bit of the address is toggled (double buffering).
- the logic for the scale unit is the same for the 8-bit and 1-bit case, since the scale unit only generates addresses.
- each of the contone layers can be a different resolution, they are scaled independently.
- the bi- level spotl layer at buffer 45 and the dither matrix select layer at buffer 46 also need to be scaled.
- the bi-level tag data at buffer 47 is established at the correct resolution and does not need to be scaled.
- the scaled-up dither matrix select bit is used by the dither matrix access unit 48 to select a single 8-bit value from the two dither matrices.
- the 8-bit value is output to the 4 comparators 44, and 49 to 51, which simply compare it to the specific 8-bit contone value.
- the generation of an actual dither matrix is dependent on the structure of the printhead and the general processes by which to generate one will be familiar to those skilled in the art.
- a 1 is output. If not, then a 0 is output.
- These bits are then all ANDed at 52 to 56 with an inPage bit from the margin unit 57 (whether or not the particular dot is inside the printable area of the page).
- the final stage in the HCU is the compositing stage.
- the single output bit from each dot merger unit is a combination of any or all of the input bits.
- the spot color can be placed in> any output color plane (including infrared for testing purposes), black to be merged into cyan, magenta and yellow (if no black ink is present in the printhead), and tag dot data to be placed in a visible plane.
- a fixative color plane can also be readily generated.
- the dot reorg unit (DRU) 59 is responsible for taking the generated dot stream for a given color plane and organizing it into 32-bit quantities so that the output is in segment order, and in dot order within segments. Minimal reordering is required due to the fact that dots for overlapping segments are not generated in segment order.
- Two control bits are provided to the scale units by the margin unit 57: advance dot and advance line.
- the advance dot bit allows the state machine to generate multiple instances of the same dot data (useful for page margins and creating dot data for overlapping segments in the printhead).
- the advance line bit allows the state machine to control when a particular line of dots has been finished, thereby allowing truncation of data according to printer margins. It also saves the scale unit from requiring special end-of-line logic.
- the comparator unit contains a simple 8-bit "greater-than" comparator. It is used to determine whether the 8-bit contone value is greater than the 8-bit dither matrix value. As such, the comparator unit takes two 8-bit inputs and produces a single 1-bit output.
- FIG. 6 is seen more detail of the dot merger unit. It provides a means of mapping the bi-level dithered data, the spotl color, and the tag data to output inks in the actual printhead.
- Each dot merger unit takes 6 1-bit inputs and produces a single bit output that represents the output dot for that color plane.
- the output bit at 60 is a combination of any or all of the input bits. This allows the spot color to be placed in any output color plane (including infrared for testing purposes), black to be merged into cyan, magenta and yellow (in the case of no black ink in the printhead), and tag dot data to be placed in a visible plane. An output for fixative can readily be generated by simply combining all of the input bits.
- the dot merger unit contains a 6-bit ColorMask register 61 that is used as a mask against the 6 input bits. Each of the input bits is ANDed with the corresponding ColorMask register bit, and the resultant 6 bits are then ORed together to form the final output bit.
- the dot reorg unit which is responsible for taking the generated dot stream for a given color plane and organizing it into 32-bit quantities so that the output is in segment order, and in dot order within segments. Minimal reordering is required due to the fact that dots for overlapping segments are not generated in segment order.
- the DRU contains a 32-bit shift register, a regular 32-bit register, and a regular 16- bit register. A 5-bit counter keeps track of the number of bits processed so far.
- the dot advance signal from the dither matrix access unit (DMAU) is used to instruct the DRU as to which bits should be output.
- register(A) 62 is clocked every cycle. It contains the 32 most recent dots produced by the dot merger unit (DMU). The full 32-bit value is copied to register(B) 63 every 32 cycles by means of a WriteEnable signal produced by the DRU state machine 64 via a simple 5-bit counter. The 16 odd bits (bits 1, 3, 5, 7 etc.) from register(B) 63 are copied to register(C) 65 with the same WriteEnable pulse.
- a 32-bit multiplexor 66 selects between the following 3 outputs based upon 2 bits from the state machine:
- a 32-bit value made up from the 16 even bits of register A (bits 0, 2, 4, 6 etc.) and the 16 even bits of register B.
- the 16 even bits from register A form bits 0 to 15, while the 16 even bits from register B form bits 16-31.
- a 32-bit value made up from the 16 odd bits of register B (bits 1, 3, 5, 7 etc.) and the 16 bits of register C.
- the bits of register C form bits 0 to 15, while the odd bits from register B form bits 16-13.
- the margin unit (MU) 57 in FIG. 5, is responsible for turning advance dot and advance line signals from the dither matrix access unit (DMAU) 48 into general control signals based on the page margins of the current page. It is also responsible for generating the end of page condition.
- the MU keeps a counter of dot and line across the page. Both are set to 0 at the beginning of the page.
- the dot counter is advanced by 1 each time the MU receives a dot advance signal from the DMAU.
- the line counter is incremented and the dot counter is reset to 0.
- Each cycle, the current line and dot values are compared to the margins of the page, and appropriate output dot advance, line advance and within margin signals are given based on these margins.
- the DMAU contains the only substantial memory requirements for the HCU.
- FIG. 8 the line loader / format unit (LLFU). It receives dot information from the HCU, loads the dots for a given print line into appropriate buffer storage (some on chip, and some in external DRAM 34) and formats them into the order required for the printhead.
- a high level block diagram of the LLFU in terms of its external interface is shown in FIG. 9.
- the input 67 to the LLFU is a set of 6 32-bit words and a DataValid bit, all generated by the HCU.
- the output 68 is a set of 90 bits representing a maximum of 15 printhead segments of 6 colors. Not all the output bits may be valid, depending on how many colors are actually used in the printhead.
- each buffer line depends on the width of the printhead. Since a single PEC generates dots for up to 15 printhead segments, a single odd or even buffer line is therefore 15 sets of 640 dots, for a total of
- the entire set of requisite buffers might be provided on the PEC chip when manufacturing techniques are capable. Otherwise, the buffers for colors 2 onward may be stored in external DRAM. This enables the PEC to be valid even though the distance between color planes may change in the future. It is trivial to keep the even dots for color 1 on PEC, since everything is printed relative to that particular dot line (no additional line buffers are needed). In addition, the 2 half-lines required for buffering color 1 odd dots saves substantial DRAM bandwidth.
- the various line buffers (on chip and in DRAM) need to be pre-loaded with all 0s before the page is printed so that it has clean edges. The end of the page is generated automatically by the HCU so it will have a clean edge.
- FIG 10 is seen a block diagram for Color N OESplit (see Oesplit 70 of FIG. 9), and the block diagram for each of the two buffers E and F, 71,72 in FIG. 9 can be found in FIGs. 10 and 11.
- Buffer EF is a double buffered mechanism for transferring data to the printhead interface (PHI) 32 in FIG. 3. Buffers E and F therefore have identical structures.
- PHI printhead interface
- Both buffers E and F are composed of 6 sub-buffers, 1 sub-buffer per color, as shown in FIG.
- each sub-buffer numbered 73.
- the size of each sub-buffer is 2400 bytes, enough to hold 15 segments at 1280 dots per segment.
- the memory is accessed 32-bits at a time, so there are 600 addresses for each sub- buffer (requiring 10 bits of address). All the even dots are placed before the odd dots in each color's sub-buffer. If there is any unused space (for printing to fewer than 15 segments) it is located at the end of each color's sub- buffer.
- the amount of memory actually used from each sub-buffer is directly related to the number of segments actually addressed by the PEC. For a 15 segment printhead there are 1200 bytes of even dots followed by 1200 bytes of odd dots, with no unused space.
- the number of sub-buffers gainfully used is directly related to the number of colors used in the printhead. The maximum number of colors supported is 6.
- the addressing decoding circuitry for each of buffers E and F is such that in a given cycle, a single 32- bit access can be made to all 6 sub-buffers - either a read from all 6 or a write to one of the 6. Only one bit of the 32-bits read from each color buffer is selected, for a total of 6 output bits. The process is shown in FIG. 11.
- 15 bits of address allow the reading of a particular bit by means of 10-bits of address being used to select 32 bits, and 5-bits of address choose 1-bit from those 32. Since all color sub-buffers share this logic, a single 15-bit address gives a total of 6 bits out, one bit per color.
- Each sub-buffer 73 to 78 has its own WriteEnable line, to allow a single 32-bit value to be written to a particular color buffer in a given cycle.
- the individual WriteEnables are generated by ANDing the single WriteEnable input with the decoded form of ColorSelect.
- CurrAdr DotlnSegmentO (high bits) (puts in range 0 to 639) Endlf
- While read process is transferring data from E or F to the PHI, a write process is preparing the next dot-line in the other buffer.
- the data being written to E or F is color 1 data generated by the HCU, and color 2-6 data from buffer D
- Color 1 data is written to EF whenever the HCU's OutputValid flag is set, and color 2- 6 data is written during other times from register C.
- Buffer OE ! 81 in FIG. 9 is a 32-bit register used to hold a single HCU-generated set of contiguous 32 dots for color 1. While the dots are contiguous on the page, the odd and even dots are printed at different times.
- Buffer AB 82 is a double buffered mechanism for delaying odd dot data for color 1 by 2 dotlines. Buffers A and
- B therefore have identical structures.
- one of the two buffers is read from and then written to.
- the two buffers are logically swapped after the entire dot line has been processed.
- a single bit flag ABSense determines which of the two buffers are read from and written to.
- the HCU provides 32-bits of color 1 data whenever the output valid control flag is set, which is every 32 cycles after the first flag has been sent for the line.
- the 32 bits define a contiguous set of 32 dots for a single dot line -
- the output valid control flag is used as a WriteEnable control for the OEj register 81.
- the 16 even bits of HCU color 1 data are combined with the 16 even bits of register OE ! to make 32-bits of even color 1 data.
- the 16 odd bits of HCU color 1 data are combined with the 16 odd bits of register OE ⁇ to make 32-bits of odd color 1 data.
- the HCU provides 32 bits of data per color plane whenever the OutputValid control flag is set. This occurs every 32 cycles except during certain startup times.
- the 32 bits define a contiguous set of 32 dots for a single dot line - 16 even dots (bits 0, 2, 4 etc.), and 16 odd dots (bits 1, 3, 5 etc.).
- buffer OE (83 in FIG. 10) is used to store a single 32-bit value for color 1
- buffers OE 2 to OE 6 are used to store a single 32-bit value for colors 2 to 6 respectively.
- the remaining color planes are also split into even and odd dots.
- the dot data is delayed by a number of lines, and is written out to DRAM via buffer CD (84 in FIG. 9). While the dots for a given line are written to DRAM, the dots for a previous line are read from DRAM and written to buffer EF (71,72). This process must be done interleaved with the process writing color 1 to buffer EF.
- the ColorNWriteEnable signal on line 87 is given every second OutputValid flag.
- the address starts at 0, and increments every second OutputValid flag until 39. Instead of advancing to 40, the address is reset to 0, thus providing the double-buffering scheme. This works so long as the reading does not occur during the OutputValid flag, and that the previous segment's data can be written to DRAM in the time it takes to generate a single segment's data.
- the process is shown in the following pseudocode:
- Address generation for buffers C, D, E, F, and colorN are all tied to the timing of DRAM access, and must not interfere with color 1 processing with regards to buffers E and F.
- the basic principle is that the data for a single segment of color N (either odd or even dots) is transferred from the DRAM to buffer EF via buffer CD. Once the data has been read from DRAM those dots are replaced based on the values in ColorBufferN. This is done for each of the colors in odd and even dots. After a complete segment's worth of dots has accumulated (20 sets of 64 cycles), then the process begins again. Once the data for all segments in a given
- the addresses of the various half-lines for each color in DRAM should be optimized for the memory type being used.
- the very first half-line buffer is aligned for each color to a 1KByte boundary to maximize page-hits on DRAM access.
- variable DRAMMaxVal is used to check for this case, and if it occurs, the address is rounded up for the next half-line buffer to be page-aligned. Consequently the only waste is 64 bytes per 13 segments, but have the advantage of the 640-bit access completely within a single page.
- the address generation process can be considered as NumSegments worth of 10 sets of: 20 x 32-bit reads followed by 20 x 32-bit writes, and it can be seen in the following pseudocode:
- ColorNAdr ColorNAdr + 1 Endlf EndWhile EndWhen - wait until write has finished
- ColorCurrAdr[currColor] DRAMStartAddress + 640 bits Endlf
- ColorStartRowfcurrColor] ColorCurrRowfcurrColor] + 1 Endlf Endlf EndFor EndDo Wait until next Advance signal from PHI
- MaxHalfColors register is one less than the number of colors in terms of odd and even colors treated separately, but not including color 1. For example, in terms of a standard 6 color printing system there are 10 (colors 2-6 in odd and even), and so MaxHalfColors should be set to 9.
- the LLFU requires INumSegments cycles to prepare the first 180 bits of data for the printhead interface (PHI) 32. Consequently the printhead should be started and the first LineSync pulse must occur this period of time after the LLFU has started. This allows the initial Transfer value to be valid and the next 90-bit value to be ready to be loaded into the Transfer register.
- the printhead interface (PHI) 32 is the means by which the processor loads the printhead with the dots to be printed, and controls the actual dot printing process. It takes input from the LLFU and outputs data to the printhead itself.
- the PHI is capable of dealing with a variety of printhead lengths and formats. In terms of broad operating customizations, the PHI is parameterized according to Table 33:
- the internal structure of the PHI allows for a maximum of 6 colors, 8 segments per transfer, and a maximum of 2 segment groups. This is sufficient for a 15 segment (8.5 inch) printer capable of printing A4/Letter at full bleed. Multiple PECs can be connected together to produce wider prints as necessary.
- the printhead interface contains:
- LSGU LineSyncGen unit
- MJI Memjet interface
- FIG. 12 is seen the internal structure of the printhead interface (PHI) 32.
- PHI printhead interface
- the first LSGU 90 produces LineSyncO (LS0), which is used to control the Memjet Interface (MJI) in all synchronized chips.
- the second LSGU 89 produces LineSyncl (LSI) which is used to pulse the paper drive stepper motor.
- LS0 LineSyncO
- MJI Memjet Interface
- LSI LineSyncl
- a Master/Slave pin on the chip at 91 allows multiple chips to be connected together for side-by-side printing, front/back printing etc. via a Master/Slave relationship.
- the chip When the Master/Slave pin is attached to V DD , the chip is considered to be the Master, and LineSync pulses generated by the LineSyncGen unit 90 is enabled onto the two tri-state LineSync common line LineSyncO, shared by all the chips via two tri-state enables 92.
- the Master/Slave pin is attached to GND, the chip is considered to be the Slave, and LineSync pulses generated by the two LineSyncGen units 89,90 are not enabled onto the common LineSync lines. In this way, the Master chip's LineSync pulses are used by all PHIs on all the connected chips.
- the LineSyncGen units (LSGU) 89,90 are responsible for generating the synchronization pulses required for printing a page. Each LSGU produces an external LineSync signal to enable line synchronization.
- a generator inside the LGSU generates a LineSync pulse when told to 'go', and then every so many cycles until told to stop.
- the LineSync pulse defines the start of the next line.
- the exact number of cycles between LineSync pulses is determined by the CyclesBetweenPulses register, one per generator. It must be at least long enough to allow one line to print and another line to load, but can be longer as desired (for example, to accommodate special requirements of paper transport circuitry). If the CyclesBetweenPulses register is set to a number less than a line print time, the page will not print properly since each LineSync pulse will arrive before the particular line has finished printing.
- the LineSync pulse is not used directly from the LGSU.
- the LineSyncO pulse is enabled onto a tri- state LineSyncO line 97 only if the Master/Slave pin at 91 is set to Master. Consequently the LineSync pulse is only used in the form as generated by the Master PEC (pulses generated by Slave PECs are ignored).
- the Memjet interface (MJI) 93 transfers data to the Memjet printhead at 94, and tells the Memjet interface when to start printing the next line of data. It is also used to enable feedback from a specified segment.
- the Memjet printhead 95 itself is responsible for controlling the firing sequence of its nozzles, with firing profiles programmed via the I 2 C serial interface 36 in FIG. 3.
- the MJI contains a state machine that follows the printhead loading order described in Section 18.1, and it may include functionality for a preheat cycle and a cleaning cycle. Dot counts for each color are also kept by the MJI (see below).
- the MJI loads data into the printhead from a choice of 2 data sources:
- the MJI knows how many lines it has to print for the page. When the MJI is told to 'go', it waits for a LineSync pulse before it starts the first line (via an NPSync pulse to the printhead). Once it has finished loading/printing a line, it waits until the next LineSync pulse before starting the next line. The MJI stops once the specified number of lines has been loaded/printed, and ignores any further LineSync pulses. The MJI is therefore directly connected to the LLFU 31 (see FIGs 3 and 4) at 96, LineSyncO at 97 (shared between all synchronized chips), and the external Memjet printhead 95. The MJI accepts 90 bits of data from the LLFU.
- the MJI's state machine does not care which bits are valid and which bits are not valid - it merely passes the bits out to the printhead.
- the data lines and control signals coming out of the MJI are wired to the pinouts of the chip as described below.
- the MJI has a number of connections to the printhead, including a maximum of 6 colors, clocked in to a maximum of 8 segments per transfer to a maximum of 2 segment groups.
- Table 35 lists the connections, with the sense of input and output with respect to the MJI. The names correspond to the pin connections on the printhead. Table 35. Memjet Interface Connections
- the MJI maintains a count of the number of dots of each color fired from the printhead.
- the dot count for each color is a 32-bit value, individually cleared under processor control. At 32-bits length, each dot count can hold a maximum coverage dot count of 17 8-inch x 12-inch pages, although in typical usage, the dot count will be read and cleared after each page or half-page.
- the dot counts are used by the processor to update a QA chip in order to predict when the ink cartridge runs out of ink.
- the processor knows the volume of ink in the cartridge for each of the colors from the QA chip. ' Counting the number of drops eliminates the need for ink sensors, and prevents the ink channels from running dry. An updated drop count is written to the QA chip after each page. A new page will not be printed unless there is enough ink left, and allows the user to change the ink without getting a dud half-printed page which must be reprinted.
- FIG. 13 is seen the layout of a dot counter for Color N. All 6 dot counters are preferably identical in structure.
- the dot counter takes the color N data at 98, from the HCU, into a 15 line to 4 line encoder 99.
- the four line output of the encoder 99 is to an adder 100 and Color N Dot Count 101 outputting a 32 bit count at 102.
- the counter 101 might be cleared by a bit on line 103. Loading of the counter 101 is clocked by a bit on 104.
- the processor communicates with the MJI via a register set.
- the registers allow the processor to parameterize a print as well as receive feedback about print progress.
- the following registers are contained in the MJI: Table 36. Memjet interface registers
- the MJI's Status register is a 16-bit register with bit interpretations as follows: Table 37. MJI Status register
- the following pseudocode illustrates the logic required to load a printhead for a single line. Note that loading commences only after the LineSync pulse arrives. This is to ensure the data for the line has been prepared by the LLFU and is valid for the first transfer to the printhead.
- the LSGU must also be programmed to send LineSync pulses at the correct frequency.
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PCT/AU2000/000754 WO2002002338A1 (en) | 2000-06-30 | 2000-06-30 | Print engine/controller to work in multiples and a printhead driven by multiple print engine/controllers |
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JP (1) | JP4546697B2 (en) |
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US6679584B2 (en) | 1997-07-15 | 2004-01-20 | Silverbrook Research Pty Ltd. | High volume pagewidth printing |
GB2387817A (en) * | 2002-04-27 | 2003-10-29 | Hewlett Packard Co | Page wide array inkjet printer having halftone controller and multiple printheads, each printing different image strips. |
GB0621375D0 (en) * | 2006-10-27 | 2006-12-06 | Domino Printing Sciences Plc | Improvements in or relating to marking and/or coding |
CN103763566B (en) * | 2014-01-07 | 2016-09-28 | 西安建筑科技大学 | Color Halftone method for compressing image based on three-dimensional matrice WDCT conversion |
JP2019101480A (en) * | 2017-11-28 | 2019-06-24 | オムロン株式会社 | Control device and control method |
CN112394887A (en) * | 2019-08-17 | 2021-02-23 | 森大(深圳)技术有限公司 | Oneepass printing data high-efficiency processing method, device, equipment and storage medium |
US11745501B1 (en) | 2022-02-11 | 2023-09-05 | Ricoh Company, Ltd. | Drop size monitoring mechanism |
US11755865B1 (en) | 2022-03-01 | 2023-09-12 | Ricoh Company, Ltd. | Drop size monitoring mechanism |
US11731420B1 (en) | 2022-03-14 | 2023-08-22 | Ricoh Company, Ltd. | Drop size monitoring mechanism |
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EP0570146A1 (en) * | 1992-05-06 | 1993-11-18 | Xerox Corporation | Full color image output terminal interface |
WO2000027640A1 (en) * | 1998-11-09 | 2000-05-18 | Silverbrook Research Pty Ltd | Printer and methods of operation |
EP1289766A1 (en) * | 2000-05-24 | 2003-03-12 | Silverbrook Research Pty. Limited | Print engine/controller and printhead interface chip incorporating the engine/controller |
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SU1762124A1 (en) * | 1986-04-08 | 1992-09-15 | Институт кибернетики им.В.М.Глушкова | Inc-jet recording device |
JPS63188055A (en) * | 1987-01-29 | 1988-08-03 | Canon Inc | Ink jet recorder |
JPH07132594A (en) * | 1993-11-09 | 1995-05-23 | Seiko Epson Corp | Ink jet recording apparatus |
JP3063526B2 (en) * | 1994-06-22 | 2000-07-12 | 株式会社日立製作所 | Ink jet recording device |
JP3388916B2 (en) * | 1994-11-07 | 2003-03-24 | キヤノンファインテック株式会社 | Recording device |
FR2755900B1 (en) * | 1996-11-15 | 1999-01-29 | Toxot Sciences & Applic | MULTI-COLOR INK-JET PRESS, METHOD FOR SYNCHRONIZING SUCH A PRESS, AND PRINTED PRODUCT OBTAINED BY USING SUCH PRESS |
DE69936606T2 (en) * | 1998-02-13 | 2007-11-22 | Toshiba Tec K.K. | Ink-jet head driving device |
DE69932755D1 (en) * | 1998-12-16 | 2006-09-21 | Silverbrook Res Pty Ltd | Method for controlling the pressure on both sides of a print medium |
-
2000
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- 2000-06-30 EP EP00938327A patent/EP1301350A4/en not_active Ceased
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Publication number | Priority date | Publication date | Assignee | Title |
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EP0570146A1 (en) * | 1992-05-06 | 1993-11-18 | Xerox Corporation | Full color image output terminal interface |
WO2000027640A1 (en) * | 1998-11-09 | 2000-05-18 | Silverbrook Research Pty Ltd | Printer and methods of operation |
EP1289766A1 (en) * | 2000-05-24 | 2003-03-12 | Silverbrook Research Pty. Limited | Print engine/controller and printhead interface chip incorporating the engine/controller |
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IL166422A0 (en) | 2006-01-15 |
IL166422A (en) | 2007-06-17 |
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