EP1292984A1 - Damascene architecture electronic storage and method for making same - Google Patents

Damascene architecture electronic storage and method for making same

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Publication number
EP1292984A1
EP1292984A1 EP01943589A EP01943589A EP1292984A1 EP 1292984 A1 EP1292984 A1 EP 1292984A1 EP 01943589 A EP01943589 A EP 01943589A EP 01943589 A EP01943589 A EP 01943589A EP 1292984 A1 EP1292984 A1 EP 1292984A1
Authority
EP
European Patent Office
Prior art keywords
grid
layer
inter
floating
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01943589A
Other languages
German (de)
French (fr)
Inventor
Simon Deleonibus
Bernard Guillaumot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, STMicroelectronics SA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1292984A1 publication Critical patent/EP1292984A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate

Definitions

  • the present invention relates to an electronic memory and to a method for producing such a memory. More specifically, the invention relates to a memory of the flash memory type, for example with damascene architecture. It is said of a semiconductor component that it responds to a Damascene architecture when it has a surface, surface or intermediate, substantially planar, to which are exposed buried conductive parts, in a manner evoking the armor of a Damascus decor.
  • the invention finds applications in the manufacture of memory circuits and in particular memory circuits with high integration density.
  • a memory point that is to say of an individual memory component, is comparable to that of a field effect transistor with a source, a channel and a drain.
  • the channel is capped, not with a single grid, but with a grid structure comprising a floating grid and a control grid, electrically isolated from the floating grid.
  • a memory must have a certain capacity ratio between a first capacity existing between the floating gate and the control gate, and a second capacity existing between the floating gate and the substrate. This ratio must in particular be greater than 1, and is determined as a function of the electrical parameters of the memory.
  • the object of the present invention is to provide a memory, as well as a method for producing a memory, which does not have the limitations and difficulties mentioned above. Another object is to provide a memory capable of strong integration and which has a floating gate-control gate capacity improved compared to that of known memory devices.
  • Another goal is to propose a memory manufacturing process which is both economical and compatible with the requirements of strong integration.
  • the invention more specifically relates to an electronic memory, with a source and a drain, comprising, on a substrate, a floating gate and a control gate.
  • the floating grid has a substantially U-shaped section defining a space in which the control grid is housed. Thanks to the U-shape of the floating grid, a facing surface between the floating grid and the control grid can be made larger than the opposite surface between the floating grid and the substrate. This makes it possible to have a capacity ratio suitable for rapid writing and reading and makes it possible to lower the writing voltages.
  • Ci nt and C ox respectively an inter-grille capacity
  • the dielectric is a layer of insulating inter-grille, and a capacitance formed between the floating gate and the substrate, the dielectric of which is a layer of gate insulator.
  • the terms e ox , e int , ⁇ ox , ⁇ int , S ox and S int denote the thickness, the dielectric constant and the surface respectively of the gate oxide (ox) and the inter-gate oxide (int ).
  • the memory of the invention can be such that: - the control grid has a first face turned towards the substrate and faces, called lateral, substantially perpendicular to the first face, facing respectively the source and the drain, - the floating grid has a first part located between the first face of the control grid and the substrate, opposite said first face of the control grid, - the floating grid also has second and third parts, called lateral, substantially perpendicular to the first part and arranged opposite the lateral faces of the control grid.
  • the facing surface between the floating grid and the control grid corresponds substantially to the sum of the surface of the first face and that of the lateral faces of the control grid.
  • the facing surface between the floating grid and the substrate is limited to the surface of the first part of the floating grid, that is to say approximately the surface of the first face of the control grid.
  • this may include a layer of inter-grid insulation, disposed between the floating grid and the control grid.
  • This layer also has a substantially U-shaped section adjusted on the floating grid and on the control grid.
  • the invention also relates to a method of manufacturing a memory, for example as indicated above.
  • the method comprises the following successive stages: a) the formation on a substrate of a dummy grid, b) the production in the substrate of a source and a drain, self-aligned on the dummy grid, c) the coating of the dummy grid by a coating layer, and leveling of this layer with stopping on the dummy grid, d) elimination of the dummy grid to release a grid well intended to receive the floating grid and the control grid, e) depositing at least a first grid layer, at least one layer of inter-grid insulation and at least a second grid layer, and forming the layers to define a floating grid and a control grid separated by an inter-grid insulation, the first grid layer and the inter-grid insulation layer having an overall thickness less than a height of the well.
  • the dummy grid has an important role in determining the location and dimensions of the final grids. It can also be used as an implantation mask when forming the regions of source and drain. Indeed, when these regions are formed by implantation of doping impurities, they are automatically aligned on the sides of the dummy grid, and therefore on those of the final grids which will replace the dummy grid.
  • a common dummy grid can be used for this set of memories.
  • the source and the drain of each memory can be formed, for example, in one or two implantation steps, each time using the dummy grid as an implantation mask. It is then also possible to equip the dummy grid with lateral spacers which line its sides. When these spacers are formed between the two implantation steps, gradual source and drain regions are obtained, in a manner known per se.
  • the role of the dummy grid should be noted during the siliciding of the source and drain regions.
  • the materials used for the dummy grid and those used for the lateral spacers are chosen so as not to react with a siliciding metal, it is possible to deposit this metal on the entire structure and then subject it to a treatment. thermal with a temperature sufficient to cause siliciding. Siliconization then takes place only in regions where the metal is in direct contact with silicon. Such siliciding is qualified as selective.
  • the method of the invention offers several possibilities for mutual electrical insulation of the layers of materials forming the floating gate and the control gate. Insulation must be provided between the layers and at the ends of these. The ends considered here correspond to the limits of extension of the layers in a direction normal to the drain-source direction, that is to say along the drain and along the source, perpendicular to the direction of circulation of a channel current. .
  • step e) of the method may include:
  • step e) of the process may include, in order:
  • the coating layer of the dummy grid has, within the framework of the process, essentially a role of "mold", to form the grid well, after the elimination of the dummy grid.
  • the coating material may however be given other functions.
  • the coating material can be chosen to be electrically conductive and form contact ports for the source and the drain.
  • the coating material can also be chosen electrically insulating to isolate, for example, different components formed on the same substrate.
  • contact-making passages are made in the coating layer directly above the source and the drain, to connect them electrically to lines. interconnection, for example.
  • the interconnection of components is one of the common and usual techniques of microelectronics and is not described further here.
  • FIGS. 1 and 2 are schematic sections of a semiconductor structure illustrating the production of a dummy grid during the implementation of a method according to the invention.
  • FIG. 3 illustrates a self-aligned siliciding, operated on a structure conforming to FIG. 2.
  • Figures 4 and 5 illustrate the formation of a coating layer on a structure in accordance with Figure 3.
  • Figure 6 illustrates the elimination of the dummy grid from a structure according to Figure 5.
  • Figures 7, 8 and 9 show, in section, the production of a final grid from a structure in accordance with Figure 6.
  • - Figure 10 is a top view of a structure comparable to that of Figure 9 and illustrates a first possibility of making the grids.
  • - Figure 11 is a schematic section on a plane XI-XI of the structure of Figure 10.
  • - Figure 12 is a schematic section on a plane XII-XII of the structure of Figure 10.
  • FIG. 13 is a top view of a structure comparable to that of Figure 9 and illustrates a second possibility of making the grids.
  • Figure 14 is a schematic section of the structure of Figure 13 along a plane XIV-XIV.
  • Figure 15 is a schematic section of the structure of Figure 13 along a plane XV-XV.
  • FIG. 1 shows a silicon substrate 100, the surface of which has been oxidized in order to form a layer 102 of silicon oxide, called the pedestal layer.
  • a layer of polycrystalline or amorphous silicon 104 On the layer 102 are successively deposited a layer of polycrystalline or amorphous silicon 104 then a layer of silicon nitride 106. All of these layers form a stack 110.
  • the total thickness of the layers 104 and 106 is, for example, of the order of 100 to 500 nm and corresponds substantially to the total thickness of the grids of a memory point which will ultimately be obtained at the end of the manufacturing process.
  • An etching mask 108 shown in broken lines, such as a photosensitive resin mask, is formed on the layer 106 of silicon nitride. This mask defines the location, the size and the shape of a dummy grid which it is desired to produce in the stack 110.
  • the layers 102, 104 and 106 of the stack 110 are eliminated by etching with the exception of a portion protected by the mask 108.
  • This portion of the stack forms the body of the dummy grid, identified with the reference 112 in FIG. 2.
  • the formation of the dummy grid is followed by a first implantation of ions at low dose.
  • ions for example, during the first implantation, boron, phosphorus or arsenic ions can be implanted with a dose of 10 13 to 10 14 cm -2 at an energy of 3 to 25 keV.
  • the first implantation is followed by the formation on the side (s) of the dummy grid of lateral spacers 114, 116 visible in FIG. 2.
  • the lateral spacers comprise a first layer of silicon oxide 114 in contact with the layers 104 and 106 of the dummy grid.
  • a second surface layer 116 of silicon nitride covers the oxide layer.
  • the role of the first spacer layer 114 is essentially to limit the contact stresses with the layers of material of the dummy grid, and in particular with polycrystalline silicon. It also limits the constraints of contact with a small portion of substrate which it touches at the base of the dummy grid.
  • the second layer of spacer 116 essentially has the role of protecting the dummy grid from the subsequent treatments of the process and in particular the siliciding treatments.
  • the formation of the lateral spacers can take place according to techniques known per se, which essentially provide for the full plate deposition of the selected materials then the anisotropic etching of these materials so as to leave only a small thickness on the flanks of the dummy grid.
  • a second implantation of impurities can be carried out at a higher dose, for example from 10 14 to 5.10 15 at / cm 2 .
  • the second layout then uses the dummy grid, widened by the lateral spacers, as a layout mask. It makes it possible to obtain in the substrate regions 118,120 of source and gradual drain with a doping which decreases while going towards the channel 121. The gradual character of the regions of source and drain is not intentionally shown in the figures for reasons of clarity.
  • FIG. 3 shows a next step which consists in carrying out selective siliciding of the substrate in the source and drain regions.
  • This operation involves the deposition of a layer 124 of metal such as, for example, titanium, cobalt, or nickel and then a heat treatment at a temperature sufficient to cause a siliciding reaction between the metal and the silicon of the substrate. Siliciding locally increases the conductivity of the source and the drain and thus reduces their access resistance.
  • metal such as, for example, titanium, cobalt, or nickel
  • the siliciding is qualified as selective insofar as it is limited to the zones in which the metal of the layer 124 is directly in contact with silicon. It can be observed in FIG. 3 that the metal layer 124 has disappeared above the source and drain regions to form surface layers 126, 128 of silicide there. On the other hand, the metal layer 124 persists on the top and on the sides of the dummy grid. Indeed, on these parts, the silicon nitride of the layers 106 and 116 of the dummy grid and of the spacers prevented siliciding.
  • FIG. 3 shows, in the form of primers in phantom, other dummy grids possibly produced on the same substrate.
  • Figures 4 and 5 show an operation of coating the dummy grid.
  • a thick layer of coating material 200 is deposited on the entire structure to conform to its shape. It can be observed that the coating layer has a thickness which is greater than the height of the dummy grid.
  • the coating material can be chosen to be conductive or insulating. In the example described, it is, for example, a layer of silicon oxide, that is to say an electrical insulating material.
  • FIG. 5 shows the result of a leveling operation during which the coating layer has been polished to give it a flat surface 236.
  • the polishing is continued with stop on the layer of silicon nitride 106 of the dummy grid for making it flush with the flat surface 236. It may be noted that when the coating material is electrically conductive, the leveling with stop on the silicon nitride layer leads to the electrical separation of the source and the drain.
  • a next step in the process comprises, as shown in FIG. 6, the elimination of the dummy grid to form a well 240 delimited by the lateral spacers 114, 116 and surrounded by the coating layer 200.
  • the elimination of the grid dummy comprises the successive etching of the layers 104, 106 making up the dummy grid, then the etching of the pedestal layer 102, which, in this example, is also eliminated.
  • FIG. 7 illustrates a first series of operations for producing a final grid.
  • a layer of gate insulator 248 is formed at the bottom of the well 240. This is, by example, of a layer of silicon oxide obtained by deposition of Si0 2 or by oxidation of the underlying substrate 100.
  • a first grid layer 260 is then deposited, followed by a layer of inter-grid insulation 262.
  • the first grid layer can be formed, for example, of a material chosen from: Si,, TaN, W / TiN, Ti , TaN or Cu / TaN, W / Nb; / Ru0 2 or in a stack of sublayers formed from these materials.
  • the inter-grid insulation layer can also be solid or formed by a stack of dielectric sublayers. It is, for example, an oxide / nitride / oxide stack which has the advantage of a high dielectric constant.
  • the intergrid insulator layer may also be an insulator with a high dielectric constant (HiK).
  • HiK high dielectric constant
  • the thickness of this layer is given, for example, by the ratio of the dielectric constants: ⁇ HiK m t-aiR ⁇ 0N0 " tONO
  • ⁇ H ⁇ ⁇ , ⁇ ON o, t H ⁇ and t ON o are the dielectric constants and the thicknesses respectively of a material with high dielectric constant and of an oxide / nitride / oxide stack.
  • a layer of intergrid insulator made of a material with a dielectric constant greater than that of the gate insulator is chosen.
  • these materials are respectively an oxide / nitride / oxide stack and silicon oxide, the thickness of the layers is, for example, 140A (O / N / O) and 90A (oxide) respectively.
  • the overall thickness of the first grid layer and of the grid insulator layer is less than the depth of the well 240, that is to say less than the height of the previously eliminated dummy grid. .
  • the thickness of the gate insulator layer 148 which, like the inter-gate insulator layer, is shown with exaggerated thicknesses for reasons of clarity of the figures is neglected.
  • etching and / or isolation operations of certain parts may take place. These operations do not appear in FIG. 7 but will be described later.
  • Figures 8 and 9 show the completion of the memory component.
  • a second grid layer 264 made of one or more conductive materials chosen from those mentioned above for the first grid layer, is deposited on the inter-grid insulating layer 262. As shown in FIG. 8, the thickness of the second grid layer is sufficient to completely fill the part of the well not yet occupied by the other layers of the final grid.
  • the deposition of the second grid layer is followed, as shown in FIG. 9, by a leveling which makes it possible to remove all the materials which protrude above the coating layer 200 to expose its superficial face 236.
  • This operation completes the process for manufacturing the memory proper. It can however be supplemented by the interconnection of the memory component with other components produced on the same substrate or not. Interconnection operations are outside the strict scope of the invention and are in themselves well known. They are therefore not described here. Simply, broken lines indicate the position of contact-making passages 270 that it is possible to make in the coating layer 200 to connect the source and the drain to interconnection lines not shown.
  • FIG. 9 which corresponds to a section plane of the component passing through the source and the drain, shows the U-shape of the floating gate finally obtained from the first layer of gate.
  • the floating grid is separated from the control grid by the inter-grid insulation, also in a U shape. It surrounds the control grid on three sides, in this case, the side facing channel 121, and the two lateral ribs. perpendicular to the substrate.
  • references 260 and 264 are used in the rest of the text both to designate the first and second grid layers and to designate the floating grid and the control grid, respectively formed by these layers.
  • Figure 10 is a top view of the memory component of Figure 9. It corresponds to a particular implementation of the method of the invention in which the first layer of grid 260 and the inter-grid insulation layer 262, then cut these layers before forming the second grid layer 264.
  • the cutting here corresponds to an etching of these layers, intended to fix their extension along the source and the drain 118 and 120.
  • the location of the source and drain regions 118, 120, hidden by the coating layer is indicated in broken lines.
  • the edges of the first grid layer and of the inter-grid insulation layer, as fixed by the cutout, are indicated by arrows 280.
  • the reference 282 indicates a layer of insulation called edge insulation, which covers the cutting edges of the first grid layer and the inter-grid insulation layer.
  • the edge insulating layer can be obtained by oxidation of the cutting edge of the first grid layer. It can also be formed by depositing a layer of dielectric material and then by anisotropic etching of this material, as for the formation of lateral spacers on the sides of the dummy grid.
  • the edge insulating layer 282 makes it possible to electrically insulate the first grid layer 260 and the second grid layer 264, formed subsequently, on the cutting edges 280.
  • FIGS. 9 and 10 show the so-called damascene structure which is characterized by the outcrop of the metal layers and in particular the second grid layer forming the control grid, at the free surface 236 of the coating layer.
  • the second grid layer 264 can extend parallel to the regions source and drain (perpendicular to the section plane of Figure 9) to form a line of words, for example.
  • FIG. 10 shows the sectional planes IX-IX, XI-XI and XII-XII which correspond to FIGS. 9, 11 and 12.
  • FIG. 11 is a section of the structure of FIGS. 9 and 10 according to a section plane which crosses, in its middle, the part of the first grid layer 262 rising up on the lateral spacers 114, 116. It makes it possible to better show the 'edge insulator 282 which laterally delimits the floating grid 260.
  • the inter-grid insulation layer 262 and the second grid layer 264, forming the control grid, are indicated in broken lines because hidden by the first grid layer ( floating grid).
  • the reference 290 designates a deep trench of silicon oxide formed in the substrate 100 to isolate the memory component from other components formed on the same substrate.
  • Figure 12 is a sectional view of the structure of Figures 9 and 10 which passes through, in the middle, the control gate in a direction perpendicular to the plane of Figure 9. This cutting 'reveals the first gate layer 260 and the grid insulator layer 262, which have been cut and protected by the edge insulator layer 282, before the second grid layer 264 is formed.
  • FIG. 13 is a top view of a component comparable to that of FIG. 9 and illustrates another possibility of producing the grid. floating and control grid.
  • the first grid layer 260 is first deposited, then this layer is cut before depositing the inter-grid insulation layer 262 and the second grid layer 264.
  • the cutting of the first layer of grid 260 operated by etching the latter according to an appropriate etching mask, is intended to fix its extension parallel to the source and drain regions.
  • the cutting is distinguished from that operated in the variant described above, only by the fact that it relates only to the first grid layer, without affecting the inter-grid insulation layer deposited later. It can be seen in FIG. 13 that no layer of edge insulation is provided.
  • FIG. 14 is a section of the structure of FIG. 13 according to a section plane XIV-XIV which crosses, in its middle, the part of the layer of inter-grid insulation which rises along the spacers 114, 116, and along the lateral flanks of the floating grid and the grid control. It can be observed that the cutting edges of the first grid layer 260, bearing the reference 280 by analogy with FIGS. 11 and 12, are completely covered and isolated from the second grid layer 264, by the layer of insulating grids 262. This somehow covers the floating grid 260. The same observation can be made in FIG.
  • the control grid 264 is of the Damascene type and is flush with the surface 236 of the coating layer hidden in FIG. 15.

Abstract

The invention concerns an electronic storage, with a source (118) and a drain (120), comprising, on a substrate (100), a floating gate (260) and a control gate (264). The invention is characterised in that the floating gate (260) has a substantially U-shaped cross-section defining a space wherein is housed the control gate (264).

Description

MEMOIRE ELECTRONIQUE A ARCHITECTURE DAMASCENE ET PROCEDE DE REALISATION D'UNE TELLE MEMOIRE. ELECTRONIC MEMORY WITH DAMASCENE ARCHITECTURE AND METHOD FOR PRODUCING SUCH A MEMORY.
Domaine technique La présente invention concerne une mémoire électronique et un procédé de réalisation d'une telle mémoire. De façon plus précise, l'invention concerne une mémoire du type mémoire flash, par exemple à architecture damascène. On dit d'un composant à semi- conducteur qu'il répond à une architecture damascène lorsqu'il présente une surface, superficielle ou intermédiaire, sensiblement plane, à laquelle affleurent des parties conductrices enterrées, d'une manière évoquant les armures d'un décor de Damas. L'invention trouve des applications dans la fabrication de circuits de mémoire et en particulier de circuits de mémoire à forte densité d'intégration.Technical Field The present invention relates to an electronic memory and to a method for producing such a memory. More specifically, the invention relates to a memory of the flash memory type, for example with damascene architecture. It is said of a semiconductor component that it responds to a Damascene architecture when it has a surface, surface or intermediate, substantially planar, to which are exposed buried conductive parts, in a manner evoking the armor of a Damascus decor. The invention finds applications in the manufacture of memory circuits and in particular memory circuits with high integration density.
Etat de la technique antérieure Un exemple de mémoire flash de type connu est donné par le document (1), dont les références sont indiquées à la fin de la présente description. Ce document illustre aussi les impératifs de conception et de fabrication liés au performances et caractéristiques attendues pour un tel composant.STATE OF THE PRIOR ART An example of a flash memory of known type is given by document (1), the references of which are given at the end of this description. This document also illustrates the design and manufacturing requirements linked to the performance and characteristics expected for such a component.
De façon générale, on cherche à réaliser des mémoires ou des circuits de mémoire avec une capacité de stockage d'informations toujours accrue, et avec des vitesses d'écriture et de lecture toujours plus élevées. Ces impératifs conduisent à la miniaturisation des composants et à leur intégration avec des densités croissantes .In general, it is sought to produce memories or memory circuits with an ever increasing information storage capacity, and with ever higher write and read speeds. These imperatives lead to miniaturization components and their integration with increasing densities.
La structure classique d'un point de mémoire, c'est-à-dire d'un composant de mémoire individuel, est comparable à celle d'un transistor à effet de champ avec une source, un canal et un drain. Toutefois, le canal est coiffé, non pas d'une grille unique, mais d'une structure de grille comprenant une grille flottante et une grille de commande, électriquement isolée de la grille flottante. Pour autoriser une programmation et une lecture rapide, une mémoire doit présenter un certain rapport de capacités entre une première capacité existant entre la grille flottante et la grille de commande, et une deuxième capacité existant entre la grille flottante et le substrat. Ce rapport doit en particulier être supérieur à 1, et est déterminé en fonction des paramètres électriques de la mémoire .The classical structure of a memory point, that is to say of an individual memory component, is comparable to that of a field effect transistor with a source, a channel and a drain. However, the channel is capped, not with a single grid, but with a grid structure comprising a floating grid and a control grid, electrically isolated from the floating grid. To allow programming and rapid reading, a memory must have a certain capacity ratio between a first capacity existing between the floating gate and the control gate, and a second capacity existing between the floating gate and the substrate. This ratio must in particular be greater than 1, and is determined as a function of the electrical parameters of the memory.
Pour atteindre des densités d'intégration très fortes il est connu de réduire la taille des points de mémoire. Ceci implique une réduction de la taille de leurs grilles et donc de l'épaisseur de l'isolant de grille qui sépare la grille flottante du canal sous- jacent. La réduction de l'épaisseur de l'isolant de grille conduit à une augmentation de la capacité électrique existant entre la grille flottante et le canal ou le substrat. Pour conserver le rapport entre les capacités indiqué ci-dessus, il convient donc d'augmenter également la valeur de la capacité entre la grille flottante et la grille de commande. Cette capacité, peut être légèrement augmentée en choisissant un isolant inter-grilles avec une constante diélectrique la plus élevée possible, mais reste limitée par la réduction de la taille des grilles imposée par la miniaturisation du composant, et celle de l'épaisseur de l'isolant de grille. En effet, pour une épaisseur d'isolant de grille inférieure à 9 nm, des problèmes de perte d'information apparaissent, liés à une perte de charge à travers l'oxyde.To achieve very high integration densities, it is known to reduce the size of the memory points. This implies a reduction in the size of their grids and therefore in the thickness of the gate insulator which separates the floating gate from the underlying channel. The reduction in the thickness of the gate insulator leads to an increase in the electrical capacity existing between the floating gate and the channel or the substrate. To maintain the ratio between the capacities indicated above, it is therefore also necessary to increase the value of the capacity between the floating grid and the control grid. This capacity can be slightly increased by choosing an inter-gate insulator with the highest possible dielectric constant, but remains limited by the reduction in the size of the gates imposed by the miniaturization of the component, and that of the thickness of the gate insulator. Indeed, for a gate insulator thickness of less than 9 nm, problems of information loss appear, linked to a pressure drop across the oxide.
Une difficulté importante existe donc pour concilier les impératifs de l'intégration et du maintien des caractéristiques de fonctionnement des mémoires .A major difficulty therefore exists in reconciling the imperatives of integrating and maintaining the operating characteristics of the memories.
A titre d'illustration de l'état de la technique, et plus particulièrement des techniques de fabrication de composants de type mémoire ou transistor, on peut se reporter encore aux documents (2) et (3) dont les références complètes sont également données à la fin de la description.By way of illustration of the state of the art, and more particularly of the techniques for manufacturing memory or transistor type components, reference may also be made to documents (2) and (3), the full references of which are also given at the end of the description.
Exposé de l'invention.Statement of the invention.
La présente invention a pour but de proposer une mémoire, de même qu'un procédé de réalisation d'une mémoire, qui ne présentent pas les limitations et difficultés mentionnées ci-dessus. Un autre but est de proposer une mémoire susceptible d'une forte intégration et qui présente une capacité grille flottante- grille de commande améliorée par rapport à celle des dispositifs de mémoire connus.The object of the present invention is to provide a memory, as well as a method for producing a memory, which does not have the limitations and difficulties mentioned above. Another object is to provide a memory capable of strong integration and which has a floating gate-control gate capacity improved compared to that of known memory devices.
Un but est encore de proposer un procédé de fabrication de la mémoire qui soit à la fois économique et compatible avec les exigences d'une intégration forte .Another goal is to propose a memory manufacturing process which is both economical and compatible with the requirements of strong integration.
Pour atteindre ces buts, l'invention a plus précisément pour objet une mémoire électronique, avec une source et un drain, comportant, sur un substrat, une grille flottante et une grille de commande. Conformément à l'invention, la grille flottante présente une section sensiblement en U définissant un espace dans lequel est logée la grille de commande. Grâce à la forme en U de la grille flottante une surface en regard entre la grille flottante et la grille de commande peut être rendue plus importante que la surface en regard entre la grille flottante et le substrat. Ceci permet de disposer d'un rapport de capacités adapté à une écriture et à une lecture rapides et permet d'abaisser les tensions d'écriture.To achieve these goals, the invention more specifically relates to an electronic memory, with a source and a drain, comprising, on a substrate, a floating gate and a control gate. According to the invention, the floating grid has a substantially U-shaped section defining a space in which the control grid is housed. Thanks to the U-shape of the floating grid, a facing surface between the floating grid and the control grid can be made larger than the opposite surface between the floating grid and the substrate. This makes it possible to have a capacity ratio suitable for rapid writing and reading and makes it possible to lower the writing voltages.
On a : ^^ __ o . x fint χ _S X O na: ^^ __ o. x fint χ _S X
^ox eint εox Sj_nt Dans ces expressions Cint et Cox désignent respectivement une capacité inter-grilles , dont le diélectrique est une couche d'isolant inter-grilles, et une capacité formée entre la grille flottante et le substrat, dont le diélectrique est une couche d'isolant de grille. Les termes eox, eint, εox, εint, Sox et Sint désignent l'épaisseur, la constante diélectrique et la surface respectivement de l'oxyde de grille (ox) et de l'oxyde inter-grilles (int).^ ox e int ε ox Sj_ n t In these expressions Ci nt and C ox respectively an inter-grille capacity, the dielectric is a layer of insulating inter-grille, and a capacitance formed between the floating gate and the substrate, the dielectric of which is a layer of gate insulator. The terms e ox , e int , ε ox , ε int , S ox and S int denote the thickness, the dielectric constant and the surface respectively of the gate oxide (ox) and the inter-gate oxide (int ).
Or, si on baisse les tensions d'écriture (de programmation) il convient d'augmenter le rapport -Ln^ ; ce qui est possible avec la mémoire conforme àHowever, if the writing (programming) voltages are lowered, the ratio should be increased - Ln ^; which is possible with memory conforming to
1 ' invention.1 invention.
De façon plus précise, la mémoire de l'invention peut être telle que : - la grille de commande présente une première face tournée vers le substrat et des faces, dites latérales, sensiblement perpendiculaires à la première face, tournées respectivement vers la source et le drain, - la grille flottante présente une première partie située entre la première face de la grille de commande et le substrat, en regard de ladite première face de la grille de commande, - la grille flottante présente en outre des deuxième et troisième parties, dites latérales, sensiblement perpendiculaires à la première partie et disposées en regard des faces latérales de la grille de commande. On constate que la surface en regard entre la grille flottante et la grille de commande correspond sensiblement à la somme de la surface de la première face et de celle des faces latérales de la grille de commande. En revanche la surface en regard entre la grille flottante et le substrat se limite à la surface de la première partie de la grille flottante, c'est-à- dire environ la surface de la première face de la grille de commande.More precisely, the memory of the invention can be such that: - the control grid has a first face turned towards the substrate and faces, called lateral, substantially perpendicular to the first face, facing respectively the source and the drain, - the floating grid has a first part located between the first face of the control grid and the substrate, opposite said first face of the control grid, - the floating grid also has second and third parts, called lateral, substantially perpendicular to the first part and arranged opposite the lateral faces of the control grid. It can be seen that the facing surface between the floating grid and the control grid corresponds substantially to the sum of the surface of the first face and that of the lateral faces of the control grid. On the other hand, the facing surface between the floating grid and the substrate is limited to the surface of the first part of the floating grid, that is to say approximately the surface of the first face of the control grid.
Dans une réalisation particulière du composant de mémoire de l'invention, celui-ci peut comporter une couche d'isolant inter-grilles, disposée entre la grille flottante et la grille de commande. Cette couche présente également une section sensiblement en U ajustée sur la grille flottante et sur la grille de commande .In a particular embodiment of the memory component of the invention, this may include a layer of inter-grid insulation, disposed between the floating grid and the control grid. This layer also has a substantially U-shaped section adjusted on the floating grid and on the control grid.
Différentes possibilités de mise en forme de la couche d'isolant de grille seront exposées dans la suite du texte.Different possibilities for shaping the grid insulating layer will be explained in the following text.
L'invention concerne également un procédé de fabrication d'une mémoire, par exemple telle qu'indiquée ci-dessus. Le procédé comporte les étapes successives suivantes : a) la formation sur un substrat d'une grille factice, b) la réalisation dans le substrat d'une source et d'un drain, auto alignées sur la grille factice, c) l'enrobage de la grille factice par une couche d'enrobage, et planage de cette couche avec arrêt sur la grille factice, d) l'élimination de la grille factice pour libérer un puits de grille destiné à recevoir la grille flottante et la grille de commande, e) le dépôt d'au moins une première couche de grille, d'au mois une couche d'isolant inter-grilles et d'au moins une deuxième couche de grille, et mise en forme des couches pour définir une grille flottante et une grille de commande séparées par un isolant inter-grilles, la première couche de grille et la couche d'isolant inter-grilles présentant une épaisseur globale inférieure à une hauteur du puits.The invention also relates to a method of manufacturing a memory, for example as indicated above. The method comprises the following successive stages: a) the formation on a substrate of a dummy grid, b) the production in the substrate of a source and a drain, self-aligned on the dummy grid, c) the coating of the dummy grid by a coating layer, and leveling of this layer with stopping on the dummy grid, d) elimination of the dummy grid to release a grid well intended to receive the floating grid and the control grid, e) depositing at least a first grid layer, at least one layer of inter-grid insulation and at least a second grid layer, and forming the layers to define a floating grid and a control grid separated by an inter-grid insulation, the first grid layer and the inter-grid insulation layer having an overall thickness less than a height of the well.
La grille factice a un rôle important pour fixer l'emplacement et les dimensions des grilles définitives. Elle peut aussi être utilisée comme masque d'implantation lors de la formation des régions de source et de drain. En effet, lorsque ces régions sont formées par implantation d'impuretés dopantes, elles sont automatiquement alignées sur les flancs de la grille factice, et donc sur ceux des grilles définitives qui remplaceront la grille factice.The dummy grid has an important role in determining the location and dimensions of the final grids. It can also be used as an implantation mask when forming the regions of source and drain. Indeed, when these regions are formed by implantation of doping impurities, they are automatically aligned on the sides of the dummy grid, and therefore on those of the final grids which will replace the dummy grid.
Dans le cas d'une réalisation d'un ensemble de mémoires, en particulier d'un ensemble de mémoires alignées, une grille factice commune peut être utilisée pour cet ensemble de mémoires. La source et le drain de chaque mémoire peuvent être formés, par exemple, en une ou deux étapes d'implantation en utilisant à chaque fois la grille factice comme masque d'implantation. Il est alors de plus possible d'équiper la grille factice d'espaceurs latéraux qui garnissent ses flancs. Lorsque ces espaceurs sont formés entre les deux étapes d'implantation, on obtient, de façon connue en soi, des régions de source et de drain graduelles.In the case of an embodiment of a set of memories, in particular of a set of aligned memories, a common dummy grid can be used for this set of memories. The source and the drain of each memory can be formed, for example, in one or two implantation steps, each time using the dummy grid as an implantation mask. It is then also possible to equip the dummy grid with lateral spacers which line its sides. When these spacers are formed between the two implantation steps, gradual source and drain regions are obtained, in a manner known per se.
Enfin, il convient de relever le rôle de la grille factice lors de la siliciuration des régions de source et de drain. Lorsque les matériaux utilisés pour la grille factice et ceux utilisés pour les espaceurs latéraux sont choisis pour ne pas réagir avec un métal de siliciuration, il est possible de déposer ce métal sur l'ensemble de la structure puis de soumettre celle- ci à un traitement thermique avec une température suffisante pour provoquer la siliciuration. La siliciuration n'a alors lieu que dans des régions où le métal est en contact direct avec du silicium. Une telle siliciuration est qualifiée de sélective. Le procédé de l'invention offre plusieurs possibilités pour l'isolation électrique mutuelle des couches de matériaux formant la grille flottante et la grille de commande. L'isolation doit être prévue entre les couches et aux extrémités de celles-ci. Les extrémités considérées ici correspondent aux limites d'extension des couches dans une direction normale à la direction drain-source, c'est à dire le long du drain et le long de la source, perpendiculairement au sens de circulation d'un courant de canal.Finally, the role of the dummy grid should be noted during the siliciding of the source and drain regions. When the materials used for the dummy grid and those used for the lateral spacers are chosen so as not to react with a siliciding metal, it is possible to deposit this metal on the entire structure and then subject it to a treatment. thermal with a temperature sufficient to cause siliciding. Siliconization then takes place only in regions where the metal is in direct contact with silicon. Such siliciding is qualified as selective. The method of the invention offers several possibilities for mutual electrical insulation of the layers of materials forming the floating gate and the control gate. Insulation must be provided between the layers and at the ends of these. The ends considered here correspond to the limits of extension of the layers in a direction normal to the drain-source direction, that is to say along the drain and along the source, perpendicular to the direction of circulation of a channel current. .
A cet effet, et selon une première possibilité, l'étape e) du procédé peut comporter :To this end, and according to a first possibility, step e) of the method may include:
- le dépôt de la première couche de grille et de la couche d'isolant inter-grilles, - la gravure de ces couches pour définir leur extension le long des source et drain,- the deposition of the first grid layer and the inter-grid insulating layer, - the etching of these layers to define their extension along the source and drain,
- l'isolation électrique de flancs de découpage des couches, obtenus par la gravure,- the electrical insulation of the cutting edges of the layers, obtained by etching,
- le dépôt de la deuxième couche de grille avec une épaisseur suffisante pour combler le puits de grille,- depositing the second grid layer with a thickness sufficient to fill the grid well,
- le polissage de la deuxième couche de grille, de la couche d'isolant inter-grilles et de la première couche de grille, avec arrêt sur la couche d' enrobage. L'isolation électrique des flancs de découpage peut avoir lieu par exemple par oxydation de ces flancs, ou par recouvrement de ces flancs au moyen d'une couche de diélectrique, comparable à des espaceurs latéraux de grille. II est également possible de profiter de la couche d'isolant inter-grilles pour isoler électriquement les flancs de découpage. Dans ce cas, l'étape e) du procédé peut comporter dans l'ordre :- the polishing of the second grid layer, of the inter-grid insulation layer and of the first grid layer, with stopping on the coating layer. The electrical isolation of the cutting flanks can take place for example by oxidation of these flanks, or by covering these flanks by means of a dielectric layer, comparable to lateral grid spacers. It is also possible to take advantage of the inter-grid insulation layer to insulate electrically the cutting edges. In this case, step e) of the process may include, in order:
- le dépôt de la première couche de grille,- the deposition of the first grid layer,
- la gravure de la première couche de grille pour définir son extension le long de la source et du drain,- the etching of the first grid layer to define its extension along the source and the drain,
- le dépôt de la couche d'isolant inter-grilles et de la deuxième couche de grille, la couche d'isolant inter-grilles présentant avec la première couche de grille un épaisseur totale inférieure à la hauteur du puits de grille, et la deuxième couche de grille présentant une épaisseur suffisante pour combler le puits de grille, le polissage de la deuxième couche de grille, de la couche d'isolant inter-grilles et de la première couche de grille, avec arrêt sur la couche d'enrobage.- The deposition of the inter-grid insulation layer and the second grid layer, the inter-grid insulation layer having with the first grid layer a total thickness less than the height of the grid well, and the second grid layer having a sufficient thickness to fill the grid well, polishing the second grid layer, the inter-grid insulation layer and the first grid layer, with stopping on the coating layer.
La couche d'enrobage de la grille factice a, dans la cadre du procédé, essentiellement un rôle de "moule", pour former le puits de grille, après l'élimination de la grille factice. Le matériau d'enrobage peut cependant se voir conférer d'autres fonctions. Par exemple, le matériau d'enrobage peut être choisi électriquement conducteur et former des accès de contact pour la source et le drain.The coating layer of the dummy grid has, within the framework of the process, essentially a role of "mold", to form the grid well, after the elimination of the dummy grid. The coating material may however be given other functions. For example, the coating material can be chosen to be electrically conductive and form contact ports for the source and the drain.
Le matériau d'enrobage peut aussi être choisi électriquement isolant pour isoler, par exemple, différents composants formés sur un même substrat. Dans ce cas, des passages de prise de contact sont pratiqués dans la couche d'enrobage à l'aplomb de la source et du drain, pour les relier électriquement à des lignes d'interconnexion, par exemple. L'interconnexion des composants fait partie des techniques courantes et usuelles de la microélectronique et n'est pas davantage décrite ici. D'autres caractéristiques et avantages de l'invention ressortiront de la description qui va suivre en référence aux figures des dessins annexés. Cette description est donnée à titre purement illustratif et non limitatif.The coating material can also be chosen electrically insulating to isolate, for example, different components formed on the same substrate. In this case, contact-making passages are made in the coating layer directly above the source and the drain, to connect them electrically to lines. interconnection, for example. The interconnection of components is one of the common and usual techniques of microelectronics and is not described further here. Other characteristics and advantages of the invention will emerge from the description which follows with reference to the figures of the appended drawings. This description is given purely by way of non-limiting illustration.
Brève description des figuresBrief description of the figures
- Les figures 1 et 2 sont des coupes schématiques d'une structure à semi-conducteurs illustrant la réalisation d'une grille factice lors de la mise en œuvre d'un procédé conforme à l'invention.- Figures 1 and 2 are schematic sections of a semiconductor structure illustrating the production of a dummy grid during the implementation of a method according to the invention.
- La figure 3 illustre une siliciuration auto- alignée, opérée sur une structure conforme à la figure 2.FIG. 3 illustrates a self-aligned siliciding, operated on a structure conforming to FIG. 2.
- Les figures 4 et 5 illustrent la formation d'une couche d'enrobage sur une structure conforme à la figure 3.- Figures 4 and 5 illustrate the formation of a coating layer on a structure in accordance with Figure 3.
- La figure 6 illustre l'élimination de la grille factice d'une structure conforme à la figure 5.- Figure 6 illustrates the elimination of the dummy grid from a structure according to Figure 5.
- Les figures 7, 8 et 9 montrent, en coupe, la réalisation d'une grille définitive à partir d'une structure conforme à la figure 6.- Figures 7, 8 and 9 show, in section, the production of a final grid from a structure in accordance with Figure 6.
- La figure 10 est une vue de dessus d'une structure comparable à celle de la figure 9 et illustre une première possibilité de réalisation des grilles. - La figure 11 est une coupe schématique selon un plan XI-XI de la structure de la figure 10. - La figure 12 est une coupe schématique selon un plan XII-XII de la structure de la figure 10.- Figure 10 is a top view of a structure comparable to that of Figure 9 and illustrates a first possibility of making the grids. - Figure 11 is a schematic section on a plane XI-XI of the structure of Figure 10. - Figure 12 is a schematic section on a plane XII-XII of the structure of Figure 10.
- La figure 13 est une vue de dessus d'une structure comparable à celle de la figure 9 et illustre une deuxième possibilité de réalisation des grilles.- Figure 13 is a top view of a structure comparable to that of Figure 9 and illustrates a second possibility of making the grids.
- La figure 14 est une coupe schématique de la structure de la figure 13 selon un plan XIV-XIV.- Figure 14 is a schematic section of the structure of Figure 13 along a plane XIV-XIV.
- La figure 15 est une coupe schématique de la structure de la figure 13 selon un plan XV-XV.- Figure 15 is a schematic section of the structure of Figure 13 along a plane XV-XV.
Description détaillée de modes de mise en œuyre deDetailed description of modes of implementation of
1 ' invention.1 invention.
Des parties identiques similaires ou équivalentes des différentes figures décrites ci-après portent les mêmes références numériques de façon à faciliter le report d'une figure à l'autre. Par ailleurs, bien que la description concerne la fabrication de composants sur un substrat massif, en l'occurrence de silicium, il convient de souligner que les procédés restent identiques pour la formation des composants sur un substrat à couche mince isolée tel que les substrats de type SOI (silicium sur isolant/silicon on insulator).Identical similar or equivalent parts of the different figures described below have the same reference numerals so as to facilitate the transfer from one figure to another. Furthermore, although the description relates to the manufacture of components on a solid substrate, in this case of silicon, it should be emphasized that the processes remain identical for the formation of the components on an insulated thin film substrate such as the substrates of SOI type (silicon on insulator / silicon on insulator).
Enfin, les différentes parties de composant représentées sur les figures ne le sont pas nécessairement selon une échelle uniforme, pour rendre les figures plus lisibles.Finally, the different component parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
La figure 1 montre un substrat de silicium 100 dont la surface a été oxydée afin de former une couche 102 d'oxyde de silicium dite couche piédestal. Sur la couche 102 sont successivement déposées une couche de silicium polycristallin ou amorphe 104 puis une couche de nitrure de silicium 106. L'ensemble de ces couches forme un empilement 110. L'épaisseur totale des couches 104 et 106 est, par exemple, de l'ordre de 100 à 500 nm et correspond sensiblement à l'épaisseur totale des grilles d'un point de mémoire qui sera finalement obtenu au terme du procédé de fabrication. Un masque de gravure 108, représenté en trait discontinu, tel qu'un masque de résine photosensible, est formé sur la couche 106 de nitrure de silicium. Ce masque définit l'emplacement, la taille et la forme d'une grille factice que l'on souhaite réaliser dans l'empilement 110.FIG. 1 shows a silicon substrate 100, the surface of which has been oxidized in order to form a layer 102 of silicon oxide, called the pedestal layer. On the layer 102 are successively deposited a layer of polycrystalline or amorphous silicon 104 then a layer of silicon nitride 106. All of these layers form a stack 110. The total thickness of the layers 104 and 106 is, for example, of the order of 100 to 500 nm and corresponds substantially to the total thickness of the grids of a memory point which will ultimately be obtained at the end of the manufacturing process. An etching mask 108, shown in broken lines, such as a photosensitive resin mask, is formed on the layer 106 of silicon nitride. This mask defines the location, the size and the shape of a dummy grid which it is desired to produce in the stack 110.
Les couches 102, 104 et 106 de l'empilement 110 sont éliminées par gravure a l'exception d'une portion protégée par le masque 108.The layers 102, 104 and 106 of the stack 110 are eliminated by etching with the exception of a portion protected by the mask 108.
Cette portion de 1 ' empilement forme le corps de la grille factice, repérée avec la référence 112 sur la figure 2.This portion of the stack forms the body of the dummy grid, identified with the reference 112 in FIG. 2.
La formation de la grille factice est suivie d'une première implantation d'ions à faible dose. A titre d'exemple, lors de la première implantation, on peut implanter des ions de bore, de phosphore ou d'arsenic avec une dose de 1013 à 1014 cm-2 à une énergie de 3 à 25 keV.The formation of the dummy grid is followed by a first implantation of ions at low dose. For example, during the first implantation, boron, phosphorus or arsenic ions can be implanted with a dose of 10 13 to 10 14 cm -2 at an energy of 3 to 25 keV.
La première implantation est suivie par la formation sur le ou les flancs de la grille factice d' espaceurs latéraux 114, 116 visibles à la figure 2. Les espaceurs latéraux comportent une première couche d'oxyde de silicium 114 en contact avec les couches 104 et 106 de la grille factice. Une deuxième couche 116, superficielle, de nitrure de silicium recouvre la couche d'oxyde. La première couche d'espaceur 114 a essentiellement pour rôle de limiter les contraintes de contact avec les couches de matériau de la grille factice, et notamment avec le silicium polycristallin. Elle limite aussi les contraintes de contact avec une petite portion de substrat qu'elle touche à la base de la grille factice.The first implantation is followed by the formation on the side (s) of the dummy grid of lateral spacers 114, 116 visible in FIG. 2. The lateral spacers comprise a first layer of silicon oxide 114 in contact with the layers 104 and 106 of the dummy grid. A second surface layer 116 of silicon nitride covers the oxide layer. The role of the first spacer layer 114 is essentially to limit the contact stresses with the layers of material of the dummy grid, and in particular with polycrystalline silicon. It also limits the constraints of contact with a small portion of substrate which it touches at the base of the dummy grid.
La deuxième couche d'espaceur 116 a essentiellement pour rôle de protéger la grille factice des traitements ultérieurs du procédé et en particulier les traitements de siliciuration.The second layer of spacer 116 essentially has the role of protecting the dummy grid from the subsequent treatments of the process and in particular the siliciding treatments.
La formation des espaceurs latéraux peut avoir lieu selon des techniques connues en soi, qui prévoient pour l'essentiel le dépôt en pleine plaque des matériaux sélectionnés puis la gravure anisotrope de ces matériaux pour n'en laisser subsister qu'une faible épaisseur sur les flancs de la grille factice.The formation of the lateral spacers can take place according to techniques known per se, which essentially provide for the full plate deposition of the selected materials then the anisotropic etching of these materials so as to leave only a small thickness on the flanks of the dummy grid.
Eventuellement, après la formation des espaceurs latéraux, une deuxième implantation d'impuretés peut être conduite à plus forte dose, par exemple de 1014 à 5.1015 at/cm2. La deuxième implantation utilise alors la grille factice, élargie par les espaceurs latéraux, comme masque d'implantation. Elle permet d'obtenir dans le substrat des régions 118,120 de source et de drain graduelles avec un dopage qui diminue en allant vers le canal 121. Le caractère graduel des régions de source et de drain n'est volontairement pas représenté sur les figures pour des raisons de clarté.Optionally, after the formation of the lateral spacers, a second implantation of impurities can be carried out at a higher dose, for example from 10 14 to 5.10 15 at / cm 2 . The second layout then uses the dummy grid, widened by the lateral spacers, as a layout mask. It makes it possible to obtain in the substrate regions 118,120 of source and gradual drain with a doping which decreases while going towards the channel 121. The gradual character of the regions of source and drain is not intentionally shown in the figures for reasons of clarity.
La figure 3 montre une étape suivante qui consiste à effectuer une siliciuration sélective du substrat dans les régions de source et de drain. Cette opération comporte le dépôt d'une couche 124 de métal tel que, par exemple, du titane, du cobalt, ou du nickel puis un traitement thermique à une température suffisante pour provoquer une réaction de siliciuration entre le métal et le silicium du substrat. La siliciuration permet d'augmenter localement la conductivité de la source et du drain et réduire ainsi leur résistance d'accès.FIG. 3 shows a next step which consists in carrying out selective siliciding of the substrate in the source and drain regions. This operation involves the deposition of a layer 124 of metal such as, for example, titanium, cobalt, or nickel and then a heat treatment at a temperature sufficient to cause a siliciding reaction between the metal and the silicon of the substrate. Siliciding locally increases the conductivity of the source and the drain and thus reduces their access resistance.
La siliciuration est qualifiée de sélective dans la mesure où elle est limitée aux zones dans lesquelles le métal de la couche 124 est directement en contact avec du silicium. On peut observer sur la figure 3 que la couche de métal 124 a disparu au dessus des régions de source et de drain pour y former des couches superficielles 126,128 de siliciure. En revanche la couche de métal 124 persiste sur le dessus et sur les flancs de la grille factice. En effet, sur ces parties, le nitrure de silicium des couches 106 et 116 de la grille factice et des espaceurs ont empêché la siliciuration.The siliciding is qualified as selective insofar as it is limited to the zones in which the metal of the layer 124 is directly in contact with silicon. It can be observed in FIG. 3 that the metal layer 124 has disappeared above the source and drain regions to form surface layers 126, 128 of silicide there. On the other hand, the metal layer 124 persists on the top and on the sides of the dummy grid. Indeed, on these parts, the silicon nitride of the layers 106 and 116 of the dummy grid and of the spacers prevented siliciding.
Une vue légèrement élargie donnée à la figure 3 montre, sous la forme d'amorces en trait mixte, d'autres grilles factices éventuellement réalisées sur le même substrat. Les figures 4 et 5 montrent une opération d'enrobage de la grille factice. Une épaisse couche de matériau d'enrobage 200 est déposée sur l'ensemble de la structure pour en épouser la forme. On peut observer que la couche d'enrobage présente une épaisseur qui est supérieure à la hauteur de la grille factice. Le matériau d'enrobage peut être choisi conducteur ou isolant. Dans l'exemple décrit, il s'agit, par exemple d'une couche d'oxyde de silicium, c'est à dire d'un matériau isolant électrique.A slightly enlarged view given in FIG. 3 shows, in the form of primers in phantom, other dummy grids possibly produced on the same substrate. Figures 4 and 5 show an operation of coating the dummy grid. A thick layer of coating material 200 is deposited on the entire structure to conform to its shape. It can be observed that the coating layer has a thickness which is greater than the height of the dummy grid. The coating material can be chosen to be conductive or insulating. In the example described, it is, for example, a layer of silicon oxide, that is to say an electrical insulating material.
La figure 5 montre le résultat d'une opération de planage lors de laquelle la couche d'enrobage a été polie pour lui conférer une surface plane 236. Le polissage est poursuivi avec arrêt sur la couche de nitrure de silicium 106 de la grille factice pour la rendre affleurante à la surface plane 236. On peut noter que lorsque le matériau d'enrobage est conducteur électrique, le planage avec arrêt sur la couche de nitrure de silicium conduit à la séparation électrique de la source et du drain.FIG. 5 shows the result of a leveling operation during which the coating layer has been polished to give it a flat surface 236. The polishing is continued with stop on the layer of silicon nitride 106 of the dummy grid for making it flush with the flat surface 236. It may be noted that when the coating material is electrically conductive, the leveling with stop on the silicon nitride layer leads to the electrical separation of the source and the drain.
Une étape suivante du procédé comprend, comme le montre la figure 6, l'élimination de la grille factice pour former un puits 240 délimité par les espaceurs latéraux 114, 116 et entouré par la couche d'enrobage 200. L'élimination de la grille factice comprend la gravure successive des couches 104, 106 composant la grille factice, puis la gravure de la couche de piédestal 102, qui, dans cet exemple, est également éliminée.A next step in the process comprises, as shown in FIG. 6, the elimination of the dummy grid to form a well 240 delimited by the lateral spacers 114, 116 and surrounded by the coating layer 200. The elimination of the grid dummy comprises the successive etching of the layers 104, 106 making up the dummy grid, then the etching of the pedestal layer 102, which, in this example, is also eliminated.
La figure 7 illustre une première série d'opérations pour la réalisation d'une grille définitive. Tout d'abord une couche d'isolant de grille 248 est formée au fond du puits 240. Il s'agit, par exemple, d'une couche d'oxyde de silicium obtenue par dépôt de Si02 ou par oxydation du substrat 100 sous- jacent. On dépose ensuite une première couche de grille 260 suivie d'une couche d'isolant inter-grilles 262. La première couche de grille peut être formée, par exemple, en un matériau choisi parmi : Si, , TaN, W/TiN, Ti, TaN ou Cu/TaN, W/Nb ; /Ru02 ou en un empilement de sous-couches formées de ces matériaux. La couche d'isolant inter-grilles peut également être massive ou formée d'un empilement de sous-couches diélectriques. Il s'agit, par exemple, d'un empilement oxyde/nitrure/όxyde qui présente l'avantage d'une forte constante diélectrique.FIG. 7 illustrates a first series of operations for producing a final grid. First of all, a layer of gate insulator 248 is formed at the bottom of the well 240. This is, by example, of a layer of silicon oxide obtained by deposition of Si0 2 or by oxidation of the underlying substrate 100. A first grid layer 260 is then deposited, followed by a layer of inter-grid insulation 262. The first grid layer can be formed, for example, of a material chosen from: Si,, TaN, W / TiN, Ti , TaN or Cu / TaN, W / Nb; / Ru0 2 or in a stack of sublayers formed from these materials. The inter-grid insulation layer can also be solid or formed by a stack of dielectric sublayers. It is, for example, an oxide / nitride / oxide stack which has the advantage of a high dielectric constant.
La couche d'isolant intergrilles peut être aussi un isolant à forte constante diélectrique (HiK) . L'épaisseur de cette couche est donnée, par exemple, par le rapport des constantes diélectriques : εHiK m t-aiR ε0N0 "tONOThe intergrid insulator layer may also be an insulator with a high dielectric constant (HiK). The thickness of this layer is given, for example, by the ratio of the dielectric constants: ε HiK m t-aiR ε 0N0 " tONO
Dans cette expression εHικ, εONo, tHικ et tONo sont les constantes diélectriques et les épaisseurs respectivement d'un matériau à forte constante diélectrique et d'un empilement oxyde/nitrure/oxyde.In this expression ε H ι κ , ε ON o, t H ικ and t ON o are the dielectric constants and the thicknesses respectively of a material with high dielectric constant and of an oxide / nitride / oxide stack.
Ce matériau HiK est par exemple Al203 (ε=12), Ti02 (ε=40), Hf02 (ε=25) et BST (ε>200 en couche mince). De préférence, on choisit une couche d'isolant intergrilles en un matériau avec une constante diélectrique supérieure à celle de l'isolant de grille. Lorsque ces matériaux sont respectivement un empilement oxyde/nitrure/oxyde et de l'oxyde de silicium, l'épaisseur des couches est, par exemple, de 140A (O/N/O) et 90Â (oxyde) respectivement.This HiK material is for example Al 2 0 3 (ε = 12), Ti0 2 (ε = 40), Hf0 2 (ε = 25) and BST (ε> 200 in a thin layer). Preferably, a layer of intergrid insulator made of a material with a dielectric constant greater than that of the gate insulator is chosen. When these materials are respectively an oxide / nitride / oxide stack and silicon oxide, the thickness of the layers is, for example, 140A (O / N / O) and 90A (oxide) respectively.
On peut observer sur la figure 7 que l'épaisseur globale de la première couche de grille et de la couche d'isolant de grille est inférieure à la profondeur du puits 240 c'est à dire inférieure à la hauteur de la grille factice précédemment éliminée. On néglige dans cette évaluation de l'épaisseur de la couche d'isolant de grille 148 qui, tout comme la couche d'isolant inter-grilles sont représentées avec des épaisseurs exagérées pour des raisons de clarté des figures .It can be observed in FIG. 7 that the overall thickness of the first grid layer and of the grid insulator layer is less than the depth of the well 240, that is to say less than the height of the previously eliminated dummy grid. . In this evaluation, the thickness of the gate insulator layer 148 which, like the inter-gate insulator layer, is shown with exaggerated thicknesses for reasons of clarity of the figures is neglected.
A ce stade du procédé, de même qu'avant le dépôt de la couche d'isolant inter-grilles, peuvent intervenir des opérations de gravure et/ou d'isolation de certaines parties. Ces opérations n'apparaissent pas sur la figure 7 mais seront décrites ultérieurement.At this stage of the process, as well as before the deposition of the inter-grid insulating layer, etching and / or isolation operations of certain parts may take place. These operations do not appear in FIG. 7 but will be described later.
Les figures 8 et 9 montrent l'achèvement du composant de mémoire. Une deuxième couche de grille 264, en un ou plusieurs matériaux conducteurs choisis parmi ceux mentionnés précédemment pour la première couche de grille, est déposée sur la couche d'isolant inter-grilles 262. Comme le montre la figure 8, l'épaisseur de la deuxième couche de grille est suffisante pour entièrement combler la partie du puits non encore occupée par les autres couches de la grille définitive.Figures 8 and 9 show the completion of the memory component. A second grid layer 264, made of one or more conductive materials chosen from those mentioned above for the first grid layer, is deposited on the inter-grid insulating layer 262. As shown in FIG. 8, the thickness of the second grid layer is sufficient to completely fill the part of the well not yet occupied by the other layers of the final grid.
Le dépôt de la deuxième couche de grille est suivi, comme le montre la figure 9, d'un planage qui permet d'éliminer tous les matériaux qui dépassent au dessus de la couche d'enrobage 200 pour remettre à nu sa face superficielle 236. Cette opération termine le procédé de fabrication de la mémoire proprement dite. Il peut toutefois être complété par l'interconnexion du composant de mémoire avec d'autres composants réalisés sur le même substrat ou non. Les opérations d'interconnexion sortent du cadre strict de l'invention et sont en soi bien connues. Elles ne sont donc pas décrites ici. Simplement, des lignes en trait discontinu indiquent la position de passages de prise de contact 270 qu'il est possible de pratiquer dans la couche d'enrobage 200 pour relier la source et le drain à des lignes d'interconnexion non représentées.The deposition of the second grid layer is followed, as shown in FIG. 9, by a leveling which makes it possible to remove all the materials which protrude above the coating layer 200 to expose its superficial face 236. This operation completes the process for manufacturing the memory proper. It can however be supplemented by the interconnection of the memory component with other components produced on the same substrate or not. Interconnection operations are outside the strict scope of the invention and are in themselves well known. They are therefore not described here. Simply, broken lines indicate the position of contact-making passages 270 that it is possible to make in the coating layer 200 to connect the source and the drain to interconnection lines not shown.
La figure 9 qui correspond à un plan de coupe du composant passant par la source et le drain, montre la forme en U de la grille flottante finalement obtenue à partir de la première couche de grille. La grille flottante est séparée de la grille de commande par l'isolant inter-grilles, également en U. Elle entoure la grille de commande sur trois cotés, en l'occurrence, le côté tourné vers le canal 121, et les deux côtes latéraux perpendiculaires au substrat.FIG. 9 which corresponds to a section plane of the component passing through the source and the drain, shows the U-shape of the floating gate finally obtained from the first layer of gate. The floating grid is separated from the control grid by the inter-grid insulation, also in a U shape. It surrounds the control grid on three sides, in this case, the side facing channel 121, and the two lateral ribs. perpendicular to the substrate.
Pour des raisons de commodité, les références 260 et 264 sont utilisées dans la suite du texte aussi bien pour désigner les première et deuxième couches de grille que pour désigner la grille flottante et la grille de commande, respectivement formées par ces couches .For reasons of convenience, the references 260 and 264 are used in the rest of the text both to designate the first and second grid layers and to designate the floating grid and the control grid, respectively formed by these layers.
La figure 10 est une vue de dessus du composant de mémoire de la figure 9. Elle correspond à une mise en œuvre particulière du procédé de l'invention dans laquelle on a d'abord formé la première couche de grille 260 et la couche d'isolant inter-grilles 262, puis découpé ces couches avant de former la deuxième couche de grille 264. Le découpage correspond ici à une gravure de ces couches, destinée à fixer leur extension le long de la source et du drain 118 et 120. Sur la figure l'emplacement des régions de source et de drain 118, 120, cachées par la couche d'enrobage, est indiqué en trait discontinu. Les bords de la première couche de grille et de la couche d'isolant inter-grilles, tels que fixés par le découpage, sont indiqués par des flèches 280. La référence 282 indique une couche d'isolant appelée isolant de bords, qui recouvre les bords de découpage de la première couche de grille et de la couche d'isolant inter-grilles. La couche d'isolant de bords peut être obtenue par oxydation du bord de découpage de la première couche de grille. Elle peut aussi être formée par dépôt d'une couche de matériau diélectrique puis par gravure anisotrope de ce matériau, comme pour la formation des espaceurs latéraux sur les flancs de la grille factice. La couche d'isolant de bords 282 permet d'isoler électriquement la première couche de grille 260 et la deuxième couche de grille 264, formée ultérieurement, sur les bords de découpage 280. Les figures 9 et 10 montrent la structure dite damascène qui se caractérise par l'affleurement des couches métalliques et en particulier la deuxième couche de grille formant la grille de commande, à la surface libre 236 de la couche d'enrobage. Sur la figure 10 on observe aussi que la deuxième couche de grille 264 peut se prolonger parallèlement aux régions de source et de drain (perpendiculairement au plan de coupe de la figure 9) pour former une ligne de mots, par exemple .Figure 10 is a top view of the memory component of Figure 9. It corresponds to a particular implementation of the method of the invention in which the first layer of grid 260 and the inter-grid insulation layer 262, then cut these layers before forming the second grid layer 264. The cutting here corresponds to an etching of these layers, intended to fix their extension along the source and the drain 118 and 120. In the figure, the location of the source and drain regions 118, 120, hidden by the coating layer, is indicated in broken lines. The edges of the first grid layer and of the inter-grid insulation layer, as fixed by the cutout, are indicated by arrows 280. The reference 282 indicates a layer of insulation called edge insulation, which covers the cutting edges of the first grid layer and the inter-grid insulation layer. The edge insulating layer can be obtained by oxidation of the cutting edge of the first grid layer. It can also be formed by depositing a layer of dielectric material and then by anisotropic etching of this material, as for the formation of lateral spacers on the sides of the dummy grid. The edge insulating layer 282 makes it possible to electrically insulate the first grid layer 260 and the second grid layer 264, formed subsequently, on the cutting edges 280. FIGS. 9 and 10 show the so-called damascene structure which is characterized by the outcrop of the metal layers and in particular the second grid layer forming the control grid, at the free surface 236 of the coating layer. In FIG. 10 it is also observed that the second grid layer 264 can extend parallel to the regions source and drain (perpendicular to the section plane of Figure 9) to form a line of words, for example.
Enfin, on a indiqué sur la figure 10 des plans de coupe IX-IX, XI-XI et XII-XII qui correspondent aux figures 9, 11 et 12.Finally, FIG. 10 shows the sectional planes IX-IX, XI-XI and XII-XII which correspond to FIGS. 9, 11 and 12.
La figure 11 est une coupe de la structure des figures 9 et 10 selon un plan de coupe qui traverse, en son milieu, la partie de la première couche de grille 262 remontant sur les espaceurs latéraux 114, 116. Elle permet de mieux montrer l'isolant de bords 282 qui délimite latéralement la grille flottante 260. La couche d'isolant inter-grilles 262 et la deuxième couche de grille 264, formant la grille de commande, sont indiquées en trait discontinu car cachées par la première couche de grille (grille flottante). La référence 290 désigne une tranchée profonde d'oxyde de silicium pratiquée dans le substrat 100 pour isoler le composant de mémoire d'autres composants formés sur le même substrat.FIG. 11 is a section of the structure of FIGS. 9 and 10 according to a section plane which crosses, in its middle, the part of the first grid layer 262 rising up on the lateral spacers 114, 116. It makes it possible to better show the 'edge insulator 282 which laterally delimits the floating grid 260. The inter-grid insulation layer 262 and the second grid layer 264, forming the control grid, are indicated in broken lines because hidden by the first grid layer ( floating grid). The reference 290 designates a deep trench of silicon oxide formed in the substrate 100 to isolate the memory component from other components formed on the same substrate.
La figure 12, est une coupe de la structure des figures 9 et 10 qui traverse, en son milieu, la grille de commande selon une direction perpendiculaire au plan de la figure 9. Cette coupe' laisse apparaître la première couche de grille 260 et la couche d'isolant de grille 262, qui ont été découpées et protégées par la couche d'isolant de bords 282, avant la formation de la deuxième couche de grille 264.Figure 12 is a sectional view of the structure of Figures 9 and 10 which passes through, in the middle, the control gate in a direction perpendicular to the plane of Figure 9. This cutting 'reveals the first gate layer 260 and the grid insulator layer 262, which have been cut and protected by the edge insulator layer 282, before the second grid layer 264 is formed.
La figure 13, est une vue de dessus, d'un composant comparable à celui de la figure 9 et illustre une autre possibilité de réalisation de la grille flottante et de la grille de commande. Selon cette variante du procédé, on dépose d'abord la première couche de grille 260, puis on découpe cette couche avant de déposer la couche d'isolant inter-grilles 262 et la deuxième couche de grille 264. Le découpage de la première couche de grille 260, opéré par gravure de celle-ci selon un masque de gravure approprié, est destiné à fixer son extension parallèlement aux régions de source et de drain. En somme, le découpage ne se distingue de celui opéré dans la variante précédemment décrite, que par le fait qu'il ne concerne que la première couche de grille, sans affecter la couche d'isolant inter-grilles déposée ultérieurement. On peut observer sur la figure 13 qu'aucune couche d'isolant de bords n'est prévue.FIG. 13 is a top view of a component comparable to that of FIG. 9 and illustrates another possibility of producing the grid. floating and control grid. According to this variant of the method, the first grid layer 260 is first deposited, then this layer is cut before depositing the inter-grid insulation layer 262 and the second grid layer 264. The cutting of the first layer of grid 260, operated by etching the latter according to an appropriate etching mask, is intended to fix its extension parallel to the source and drain regions. In sum, the cutting is distinguished from that operated in the variant described above, only by the fact that it relates only to the first grid layer, without affecting the inter-grid insulation layer deposited later. It can be seen in FIG. 13 that no layer of edge insulation is provided.
Le fait qu'une isolation spécifique des bords de découpe de la première couche de grille soit inutile pour un composant conforme à la figure 13, ressort encore plus clairement de la figure 14. La figure 14 est une coupe de la structure de la figure 13 selon un plan de coupe XIV-XIV qui traverse, en son milieu, la partie de la couche d'isolant inter-grilles qui remonte le long des espaceurs 114, 116, et le long des flancs latéraux de la grille flottante et de la grille de commande. On peut observer que les bords de découpage de la première couche de grille 260, portant la référence 280 par analogie avec les figure 11 et 12, sont entièrement recouvertes et isolées de la deuxième couche de grille 264, par la couche d'isolant inter- grilles 262. Celle-ci encapuchonné en quelque sorte la grille flottante 260. On peut faire la même observation sur la figure 15 qui est une coupe selon un plan de coupe XV-XV parallèle à celui de la figure 14 passant par le milieu de la grille de commande. L'indication des plans de coupe est également donnée sur la figure 13. La grille de commande 264 est de type damascène et affleure à la surface 236 de la couche d'enrobage cachée sur la figure 15.The fact that a specific insulation of the cutting edges of the first grid layer is unnecessary for a component conforming to FIG. 13 is more clearly shown in FIG. 14. FIG. 14 is a section of the structure of FIG. 13 according to a section plane XIV-XIV which crosses, in its middle, the part of the layer of inter-grid insulation which rises along the spacers 114, 116, and along the lateral flanks of the floating grid and the grid control. It can be observed that the cutting edges of the first grid layer 260, bearing the reference 280 by analogy with FIGS. 11 and 12, are completely covered and isolated from the second grid layer 264, by the layer of insulating grids 262. This somehow covers the floating grid 260. The same observation can be made in FIG. 15 which is a section along a section plane XV-XV parallel to that of FIG. 14 passing through the middle of the control grid. The indication of the cutting planes is also given in FIG. 13. The control grid 264 is of the Damascene type and is flush with the surface 236 of the coating layer hidden in FIG. 15.
L'ensemble des réalisations décrites en référence aux figures concerne chaque fois un point de mémoire isolé.All of the embodiments described with reference to the figures each time relate to an isolated memory point.
Toutefois, les procédés de l'invention s'appliquent de façon identique pour la réalisation collective d'une pluralité de points de mémoire.However, the methods of the invention apply identically to the collective production of a plurality of memory points.
DOCUMENTS CITESCITED DOCUMENTS
(1)(1)
"Novel 0.44μm2 Ti-Salicide STI Cell Technology for High-Density NOR Flash Memories and High Performance Embedded Application" de H. WATANABE et coll. 1998 IEEE, pages 975-978"Novel 0.44μm 2 Ti-Salicide STI Cell Technology for High-Density NOR Flash Memories and High Performance Embedded Application" by H. WATANABE et al. 1998 IEEE, pages 975-978
(2)(2)
FR-A-2 757 312FR-A-2 757 312
(3) FR-A-2 750 534 (3) FR-A-2 750 534

Claims

REVENDICATIONS
1. Procédé de fabrication d'une mémoire avec une source (118), un drain (120), une grille flottante (260) et une grille de commande (264), le procédé comportant les étapes successives suivantes : a) formation sur un substrat d'une grille factice (112), b) réalisation dans le substrat de régions de source et de drain (118, 120), auto-alignées sur la grille factice, c) enrobage de la grille factice par une couche d'enrobage (200) et planage de cette couche avec arrêt sur la grille factice, d) élimination de la grille factice pour libérer au moins un puits de grille (240) destiné à recevoir la grille flottante et la grille de commande, e) dépôt d'au moins une première couche de grille (260), d'au mois une couche d'isolant inter-grilles (262) et d'au moins une deuxième couche de grille (264), et mise en forme des couches pour définir une grille flottante et une grille de commande séparées par un isolant inter-grilles, la première couche de grille et la couche d'isolant inter-grilles présentant une épaisseur globale inférieure à une hauteur du puits de grille.1. A method of manufacturing a memory with a source (118), a drain (120), a floating grid (260) and a control grid (264), the method comprising the following successive steps: a) training on a substrate of a dummy grid (112), b) production in the substrate of source and drain regions (118, 120), self-aligned on the dummy grid, c) coating of the dummy grid with a coating layer (200) and planing of this layer with stop on the dummy grid, d) elimination of the dummy grid to release at least one grid well (240) intended to receive the floating grid and the control grid, e) deposit of at least a first grid layer (260), at least one layer of inter-grid insulation (262) and at least a second grid layer (264), and shaping of the layers to define a grid floating and a control grid separated by an inter-grid insulation, the first grid layer and the isolan layer t inter-grids having an overall thickness less than a height of the grate well.
2. Procédé selon la revendication 1, dans lequel l'étape e) comporte dans l'ordre :2. Method according to claim 1, in which step e) comprises in order:
- le dépôt de la première couche de grille (260) et de la couche d'isolant inter-grilles (262), - gravure de ces couches pour définir leur extension le long des source et drain, - isolation électrique de flancs de découpe des couches, obtenus par la gravure,- depositing the first grid layer (260) and the inter-grid insulating layer (262), - etching these layers to define their extension along the source and drain, - electrical insulation of the sides for cutting the layers, obtained by etching,
- dépôt de la deuxième couche de grille (264) avec une épaisseur suffisante pour combler le puits de grille, - polissage de la deuxième couche de grille (264), de la couche d'isolant inter-grilles (262) et de la première couche de grille (260) avec arrêt sur la couche d'enrobage.- depositing the second grid layer (264) with sufficient thickness to fill the grid well, - polishing the second grid layer (264), the inter-grid insulation layer (262) and the first grid layer (260) with stop on the coating layer.
3. Procédé selon la revendication 2, dans lequel l'étape e) comporte dans l'ordre :3. Method according to claim 2, in which step e) comprises in order:
- le dépôt de la première couche de grille (260),- depositing the first grid layer (260),
- la gravure de la première couche de grille (260) pour définir son extension le long de la source et du drain, - le dépôt de la couche d'isolant inter-grilles (262) et de la deuxième couche de grille (264), la couche d'isolant inter-grilles présentant avec la première couche de grille un épaisseur totale inférieure à la hauteur du puits de grille (240), et la deuxième couche de gille présentant une épaisseur suffisante pour combler le puits de grille,- the etching of the first grid layer (260) to define its extension along the source and the drain, - the deposition of the inter-grid insulation layer (262) and of the second grid layer (264) , the inter-grid insulation layer having with the first grid layer a total thickness less than the height of the grid well (240), and the second gille layer having a thickness sufficient to fill the grid well,
- le polissage de la deuxième couche de grille, de la couche d'isolant inter-grilles et de la première couche de grille, avec arrêt sur la couche d'enrobage (200).- Polishing the second grid layer, the inter-grid insulation layer and the first grid layer, with stopping on the coating layer (200).
4. Procédé selon la revendication 2, dans lequel, avant l'étape c), on forme sur la grille factice des espaceurs de grille (114, 116) en au moins un matériau isolant électrique. 4. Method according to claim 2, in which, before step c), grid spacers (114, 116) are formed on the dummy grid in at least one electrically insulating material.
5. Procédé selon la revendication 2, dans lequel la couche d'enrobage (200) est en un matériau conducteur électrique pour former des accès de contact de la source et du drain.5. Method according to claim 2, wherein the coating layer (200) is made of a material electrical conductor to form source and drain contact ports.
6. Procédé selon la revendication 2, dans lequel le matériau de la couche d'enrobage (200) est un matériau isolant électrique.6. The method of claim 2, wherein the material of the coating layer (200) is an electrical insulating material.
7. Procédé selon la revendication 2, comprenant, avant l'enrobage de la grille factice, une siliciuration auto-alignée des régions de source et de drain. 7. Method according to claim 2, comprising, before the coating of the dummy gate, a self-aligned siliciding of the source and drain regions.
8. Procédé selon la revendication 1, de fabrication collective d'un ensemble de mémoires, dans lequel, lors de l'étape a), on forme une grille factice commune à l'ensemble des mémoires.8. Method according to claim 1, of collective manufacture of a set of memories, in which, during step a), a dummy grid is formed common to all of the memories.
9. Mémoire électronique, avec une source (118) et un drain (120), comportant, sur un substrat (100), une grille flottante (260) et une grille de commande (264), dans laquelle la grille flottante (260) présente une section sensiblement en U définissant un espace dans lequel est logée la grille de commande (264), la mémoire étant réalisée conformément au procédé de l'une quelconque des revendications 1 à 8.9. Electronic memory, with a source (118) and a drain (120), comprising, on a substrate (100), a floating grid (260) and a control grid (264), in which the floating grid (260) has a substantially U-shaped section defining a space in which the control grid (264) is housed, the memory being produced in accordance with the method of any one of claims 1 to 8.
10. Mémoire selon la revendication 9, dans laquelle :10. Memory according to claim 9, in which:
- la grille de commande (264) présente une première face tournée vers le substrat (100) et des faces, dites latérales, sensiblement perpendiculaires à la première face, tournées respectivement vers la source et le drain,the control grid (264) has a first face facing the substrate (100) and faces, said to be lateral, substantially perpendicular to the first face, facing respectively the source and the drain,
- la grille flottante (260) présente une première partie située entre la première face de la grille de commande (264) et le substrat (100), en regard de ladite première face de la grille de commande, et caractérisée en ce que :- the floating grid (260) has a first part located between the first face of the grid control (264) and the substrate (100), facing said first face of the control grid, and characterized in that:
- la grille flottante présente en outre des deuxième et troisième parties, dites latérales, sensiblement perpendiculaires à la première partie et disposées en regard des faces latérales de la grille de commande.- The floating grid also has second and third parts, called lateral, substantially perpendicular to the first part and arranged opposite the lateral faces of the control grid.
11. Mémoire selon l'une des revendications 1 ou 10, comprenant une couche d'isolant inter-grilles (262), disposée entre la grille flottante (260) et la grille de commande (264), et présentant également une section sensiblement en U ajustée sur la grille flottante et sur la grille de commande.11. Memory according to one of claims 1 or 10, comprising a layer of inter-grid insulation (262), disposed between the floating grid (260) and the control grid (264), and also having a section substantially in U adjusted on the floating grid and on the control grid.
12. Mémoire selon la revendication 11, dans laquelle la couche (262) d'isolant inter-grilles comporte un empilement de sous-couches diélectriques.12. The memory as claimed in claim 11, in which the layer (262) of inter-grid insulation comprises a stack of dielectric sublayers.
13. Mémoire selon la revendication 11, dans laquelle la couche d'isolant inter-grilles est en un matériau avec une constante diélectrique supérieure à celle d'un isolant de grille séparant la grille flottante du substrat.13. The memory of claim 11, wherein the inter-grid insulator layer is made of a material with a dielectric constant greater than that of a gate insulator separating the floating gate from the substrate.
14. Mémoire selon la revendication 11, dans laquelle la couche d'isolant inter-grilles (262) et la grille flottante (260) présentent au moins un bord commun sensiblement en forme de U.14. The memory of claim 11, wherein the inter-grid insulating layer (262) and the floating grid (260) have at least one common edge substantially U-shaped.
15. Mémoire selon la revendication 14, dans laquelle le bord commun est recouvert d'un matériau isolant électrique (282) séparant la grille flottante de la grille de commande. 15. The memory of claim 14, wherein the common edge is covered with an electrical insulating material (282) separating the floating gate from the control gate.
EP01943589A 2000-06-09 2001-06-08 Damascene architecture electronic storage and method for making same Withdrawn EP1292984A1 (en)

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FR0007416A FR2810161B1 (en) 2000-06-09 2000-06-09 ELECTRONIC MEMORY WITH DAMASCENE ARCHITECTURE AND METHOD OF MAKING SAID MEMORY
PCT/FR2001/001775 WO2001095392A1 (en) 2000-06-09 2001-06-08 Damascene architecture electronic storage and method for making same

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