EP1285366A1 - Modelisation semi-physique de modeles de circuit equivalents au bruit haute frequence d'un transistor hemt - Google Patents

Modelisation semi-physique de modeles de circuit equivalents au bruit haute frequence d'un transistor hemt

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Publication number
EP1285366A1
EP1285366A1 EP01930749A EP01930749A EP1285366A1 EP 1285366 A1 EP1285366 A1 EP 1285366A1 EP 01930749 A EP01930749 A EP 01930749A EP 01930749 A EP01930749 A EP 01930749A EP 1285366 A1 EP1285366 A1 EP 1285366A1
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Prior art keywords
model
region
noise
physical
semi
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EP01930749A
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German (de)
English (en)
Inventor
Roger S. Tsai
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Northrop Grumman Corp
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TRW Inc
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Priority claimed from US09/840,529 external-priority patent/US20020116691A1/en
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Publication of EP1285366A1 publication Critical patent/EP1285366A1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits

Definitions

  • PARAMETERMICROSCOPYFORSEMICONDUCTQRDEVICES by Roger Tsai, Serial No. 60/200,307, (Attorney Docket No. 12-1114); EMBEDDING PARASITIC MODEL FOR PI-FET LAYOUTS, by Roger Tsai, Serial No. 60/200,810, (Attorney Docket No. 12-1116); SEMI-PHYSICAL MODELING OF HEMT DC-TO-HIGH FREQUENCY ELECTROTHERMAL CHARACTERISTICS, by Roger Tsai, Serial
  • the present invention relates to a method for modeling semiconductor devices and more particularly to a method for modeling semiconductor devices, such as field effect transistors (FET) and high electron mobility transistors (HEMT) for relatively accurately determining the physical device characteristics and noise characteristics to enable the high frequency performance of the device to be forecasted.
  • FET field effect transistors
  • HEMT high electron mobility transistors
  • HEMT technology provides unparalleled, high-performance characteristics at high frequencies (microwave to millimeter wave). As such, HEMTs are used in various
  • Equivalent circuit modeling utilizes networks of linear electrical elements to model the small signal performance of the device. Such models are known to include linear noise sources for modeling noise generating mechanisms within the device.
  • a typical small signal and noise equivalent circuit topology is shown with FIG. 1.
  • This equivalent circuit model is known to accurately model measured S-parameters (small signal characteristics) of HEMT devices up to 120 GHz and noise performance in circuit applications up to 190 GHz.
  • the noisy correlation of each equivalent circuit element to a location and function within a typical HEMT structure is shown in FIG. 2.
  • the noise generating mechanisms of Ign and Idn represent noise generation in the gate and drain respectively.
  • the noise characteristics can also be simulated directly from physical device simulators.
  • Such physical device simulators utilize the comprehensive knowledge about material characteristics andbasic device physics to simulate the actual physical operation and structure of HEMT devices.
  • Such simulation for noise characteristics are known to be based upon Monte Carlo approaches. Since this method uses the physical structure to simulate performance, the correspondence between simulated noise performance and the devices physical characteristics are relatively strong. However, the ability of the device simulator to accurately model real, measured noise characteristics is relatively inaccurate.
  • an alternate method is known for modeling real, measured characteristics known as analytical physical device modeling. This method involves the use of analytical expressions that model the basic device physics within a device. This approach uses expressions that are strictly based on the device physics alone.
  • a current/voltage perturbation analysis is applied to the analytically modeled intrinsic charge and current control expressions to derive fundamental noise generating mechanisms.
  • purely analytically- based physics expressions are unable to model known critical physical phenomena that occur within a HEMT device such as, quantized energy states within an active channel and non-stationary carrier transport.
  • Other methods are known for modeling the small signal and noise characteristics of a HEMT device. Examples of these methods are disclosed in: The Noise Properties of High Electron Mobility Transistors," by T. Brookes, IEEE Trans. Electron Devices, Vol. ED-33, No. 1, January 1986 and "A Noise Model for High Electron Mobility Transistors," by Anwar, et al., IEEE Trans Electron Devices, Vol. 41, No. 11,
  • the first mentioned reference utilizes the noise equivalent circuit model illustrated in FIG. 1 along with analytical physical model for MESFET small signal and noise characteristics.
  • the Statz et al reference builds on the Van der Ziel reference and utilizes an example of current/voltage perturbation analysis used to generate equivalent circuit noise parameters.
  • the Statz et al reference involves describing the physical origin FET noise as originating from three mechanisms: enhanced Johnson noise; diffusion noise; and electronic response of gate charge to drain charge fluctuations known as "gate breathing".
  • Region 1 is in the region where Ohm's law still applies, i.e. the electric field is low enough where linear channel mobility still governs carrier transport.
  • the physical location of Region 1 in a HEMT is shown schematically in FIG. 3.
  • the Statz, et al. reference quantifies how current fluctuations in Region 1 appear as amplified voltage fluctuations after traversing through the saturated region of the FET, shown as Region 2 in FIG.4. This total noise generating mechanism is known as enhanced Johnson noise.
  • Diffusion noise manifests itself as the spontaneous generation of dipole layers within Region 2. These dipoles layers are generated at a fixed rate and drift from their original point of generation to the boundary of Region 2 closest to the drain contact as generally shown in FIG. 4. To preserve DC continuity, the fluctuating fields and potentials within Region 2 must be nullified by the voltage fluctuations on the drain. As such, electrical noise is generated from the diffusion of these dipoles through Region 2. "Gate breathing" originates from the fact that the gate is capacitively coupled to the channel for all FET-like devices. Charge fluctuations that occur within the channel consequently induce noise charges on the gate. Because these charges are time dependent, noise displacement currents flow into the gate. The physical origin for gate noise is illustrated in FIG. 3.
  • the present invention relates to a semi-physical device model that can represent known physical device characteristics as well as measured noise characteristics accurately.
  • the semi-physical device model utilizes analytical expressions to model the fundamental charge of the electric field structure of a HEMT's internal structure. The expressions are based on device physics but are empirical in form. As such, the model is able to maintain physical dependencies with good fidelity while retaining relatively accurate measured-to-modeled noise characteristics.
  • the semi-physical model also provides model elements for a FET noise equivalent circuit model.
  • the noise generator model elements are derived from a current/voltage perturbation analysis of the intrinsic charge and electric fields as modeled within the device by the semi-physical HEMT model.
  • the simulated noise model elements represent a relatively accurate physical equivalent description of noise generating mechanisms within the physical FET. Since the model elements are derived from an intrinsic charge model, the RF performance can be predicted at an arbitrary bias point. DESCRIPTION OF THE DRAWINGS
  • FIG. 1 an exemplary small signal and noise equivalent circuit model for a HEMT device.
  • FIG. 2 is a cross sectional view illustrating a rough translation of a physical location of each of the equivalent circuit elements in the small signal and noise equivalent circuit model illustrated in FIG. 1.
  • FIG. 3 is a diagram illustrating the enhanced Johnson noise and gate breathing noise generating mechanisms in a HEMT.
  • FIG. 4 is a diagram of the diffusion noise generating mechanism in a HEMT.
  • FIG. 5 is a HEMT device embedded in a microstrip environment to facilitate on wafer testing.
  • FIG. 6 is a Smith chart which compares the measured vs. modeled S-parameters Sll, S12 and S22 up to 50 GHz.
  • FIG. 7 is a magnitude-angle plot comparing the measured vs. modeled values for the S-parameters S21 up to 50 GHz.
  • FIG. 8 is a Smith chart comparing the semiphysical and noise equivalent circuit modeled Topt up to 50 GHz.
  • FIG. 9 is a frequency response plot comparing the semiphysical and noise equivalent circuit modeled NFmin up to 50 GHz.
  • FIG. 10 is a comparison of the measured and modeled noise figure using the semiphysical noise model and the noise equivalent circuit model.
  • FIG. 11 is schematic diagram of an exemplary small signal equivalent circuit model for a HEMT device.
  • FIG. 12 is an example of a relatively accurate measured-to-model I-V characteristics using the semi-physical modeling method in accordance with the present invention.
  • FIG. 13 is a elevational view illustrating an epi stack for an exemplary HEMT.
  • FIG. 14 is a cross-sectional view of a HEMT for the exemplary epi stack illustrated in FIG. 13.
  • FIG. 15 is a blown up diagram of the cross-sectional parameters pertaining to the T-gate geometry for the exemplary epi stack illustrated in FIG. 13.
  • FIG. 16 is a diagram of an electric conductance model used in the semi-physical example.
  • FIG. 17 is a Smith chart illustrating the measured vs modeled S-parameters S 11 ,
  • FIG. 18 is similar to FIG. 17 and illustrates the measured vs. modeled values for the S21 parameter.
  • FIG. 19 is similar to FIG. 17 but for the S 12 S-parameter.
  • FIG.20 represents an exemplary S-parameter microscope in accordance with the present invention.
  • FIG 21 illustrates the internal and external regions of an exemplary HEMT device.
  • FIG. 22 is similar to FIG. 20 but illustrates the approximate locations of the model elements in the HEMT FET device illustrated is FIG. 20.
  • FIG. 23 is a schematic diagram of a common source FET equivalent circuit model.
  • FIG. 24 is an illustration of specific application of the S-parameter microscope illustrated in FIG. 20.
  • FIG. 25 is similar to FIG. 20 which demonstrates the inability of known systems to accurately predict the internal charge and electrical field structure of a semiconductor device.
  • FIG. 26 is a plan view of a four-fingered, 200 ⁇ m GaAs HEMT device.
  • FIG.27 is a graphical illustration illustrating the measured drain-to-source current
  • I ds as a function of drain-to-source voltage Vds for the sample FET device illustrated in FIG. 26.
  • FIG. 28 is a graphical illustration illustrating the drain-to-source current I ds and transconductance G m as a function of the gate-to-source voltage V gs of the sample FET device illustrated in FIG. 26.
  • FIG. 29 is a Smith chart illustrating the measured Sll, S12 and S22 parameters from frequencies of 0.05 to 40.0 GHZ for the FET device illustrated in FIG. 26.
  • FIG. 30 is a graphical illustration of the magnitude as a function of angle for the S21 S-parameter for frequencies of 0.05 to 40 GHz for the exemplary FET illustrated in FIG. 26.
  • FIG. 31 is a graphical illustration of a charge control map of the charge and electric field distribution in the on mesa source access region shown with R g as a function bias in accordance with the present invention.
  • FIG. 32 is a graphical illustration of a charge control map of charge and electric field distribution in the on-mesa drain access region shown with j as a function of bias in accordance with the present invention.
  • FIG. 33 is a graphical illustration of a charge control map for the non-quasi static majority carrier transport, shown with R ; as a function of bias in accordance with the present invention.
  • FIG. 34 is a graphical illustration of a charge control map for gate modulated charge and distribution under the gate, shown with Cgs and Cgt as function of bias in accordance with the present invention.
  • FIG. 35 is a plan view of an exemplary ⁇ -FET with two gate fingers.
  • FIG. 36 is a plan view of a ⁇ -FET with four gate fingers.
  • FIG. 37 is an illustration of a ⁇ -FET parasitic model in accordance with the present invention.
  • FIG. 38 is an illustration of an off-mesa parasitic model for a ⁇ -FET in accordance with the present invention.
  • FIG. 39 is an illustration of an interconnect and boundary parasitic model in accordance with the present invention for the ⁇ -FET with four gate fingers as illustrated in FIG. 36.
  • FIG.40 is an illustration of an inter-electrode parasitic model in accordance with the present invention.
  • FIG. 41 is a schematic diagram of the inter-electrode parasitic model illustrated in FIG. 40.
  • FIG. 42 is an illustration of an on-mesa parasitic model in accordance with the present invention.
  • FIG.43 is a schematic diagram of the on-mesa parasitic model illustrated in FIG. 42.
  • FIG. 44 is an illustration of an intrinsic model in accordance with the present invention.
  • FIG. 45 is a schematic diagram of the intrinsic model illustrated in FIG. 44.
  • FIG. 46A is an exemplary device layout of a ⁇ -FET with four gate fingers.
  • FIG. 46B is an equivalent circuit model for the ⁇ -FET illustrated in FIG. 46A.
  • FIG. 47 is a single finger unit device cell intrinsic model in accordance with the present invention.
  • FIG. 48 is similar to FIG. 47 and illustrates the first level of embedding in accordance with the present invention.
  • FIG. 49 is similar to FIG. 48 and illustrates the second level of embedding in accordance with the present invention.
  • FIG. 50 is an equivalent circuit model of the ⁇ -FET illustrated in FIG. 46A in accordance with the present invention.
  • FIG. 51 is similar to FIG. 49 and illustrates the third level of embedding in accordance with the present invention.
  • FIG. 52 is similar to FIG. 49 and illustrates the fourth level of embedding in accordance with the present invention.
  • FIG. 53 is similar to FIG. 49 and illustrates the fifth level of embedding in accordance with the present invention.
  • FIG. 54A and 54B is a flow chart of a parameter extraction modeling algorithm that forms a part of the present invention.
  • FIGS. 55 and 56 represent the error metric in accordance with the present invention.
  • FIG 57A is a Smith chart illustrating the measured versus the initial model solutions for the SI 1, S 12 and S22 S-parameters from frequencies from 0.05 to 40.0 GHz.
  • FIG. 57B is a graphical illustration of angle versus magnitude for the initially modeled S-parameter S21 from frequencies of 0.05 to 40 GHz.
  • FIG.58A is a Smith chart illustrating the measured versus simulated S-parameters SI 1, S12 and S22 for frequencies 0.05 to 40 GHz for the first extraction optimization cycle.
  • FIG. 58B is a graphical illustration of magnitude as a function of angle for the measure and first optimized model S-21 parameter for frequencies 0.05 to 40 GHz for the first optimization cycle.
  • FIG. 59A is a Smith chart illustrating the measure as a function of the final model solution for S-parameters SI 1, S 12 and S22 for frequencies 0.05 to 40 GHz for the final solution.
  • FIG. 59B is a graphical illustrations of the magnitude as a function of an angle for S-parameter S21 for the final model solution from frequency 0.05 to 40 GHz.
  • FIG. 60 is a graphical illustration of the semi-physically modeled vs measured small signal Gm.
  • FIG. 61 is a graphical illustration of the semi-physically simulated bias dependence of the small-signal output conductance Rds.
  • FIG. 62 is a graphical illustration of the semi-physically simulated bias dependence of the small signal gate-source and gate-drain capacitance Cgs and Cgd.
  • FIG. 63 is a graphical illustration of the semi-physically simulated bias- dependence of the small signal gate source charging resistance Ri.
  • FIG. 64 is a graphical illustration of the semi-physical bias dependence of the small signal source and drain resistance Rs and Rd.
  • FIG.65 is a graphical illustration of the measured vs modeled bias dependent gain at 23.5 Ghz for a K-band MMIC amplifier.
  • FIG. 66A and 66B are graphical illustrations of the extracted parameters from measured device I-V's for process control monitor testing.
  • FIG. 67 is a graphical illustration of the measured vs semi-physically simulated process variation for Gmpk and Vgspk.
  • FIG. 68 is a graphical illustration of the measured vs semi-physically simulated process variation for Idpk and Gmpk.
  • FIG. 69 is a graphical illustration of the measured vs semi-physically simulated process variation for Imax and Vpo.
  • FIG. 70 is a graphical illustration of the measured/extracted vs semi-physically simulated process variation for the small signal equivalent model Rds and Gm.
  • FIG. 71 is a graphical illustration of the measured/extracted vs semi-physically simulated process variation for the small signal equivalent model Cgs and Gm.
  • FIG. 72 is a graphical illustration of the measured vs semi-physically simulated physical dependence for Imax as a function of physical gate length.
  • FIG. 73 is a graphical illustration of the measured/extracted model vs semi- physically simulated physical dependence for Rds as a function of physical recess undercut width.
  • the present invention relates to a semi-physical device model that represents both the physical device characteristics and measured noise characteristics, which can be used to simulate RF performance through physically-based device models.
  • the semi- physical model is an analytical model based upon empirical expressions that model the physics of HEMT operation, hence the terminology "semi-physical".
  • the model incorporates real process parameters, such as gate length recess etch depth, recess undercut dimensions, passivation nitrite thickness, and the like.
  • the semi-physical model is able to maintain relatively good measured to model accuracy while accounting for the effects of process variations on the device performance.
  • the semi-physical model provides model elements for the standard small signal and noise equivalent and circuit model for FET, as generally shown in FIG. 1.
  • the model elements are derived either through small signal excitation analysis or voltage/current perturbation analysis.
  • Model elements that pertain to the small signal model are derived from a small signal excitation analysis of intrinsic charge and electric fields.
  • the method for implementing the semi-physical model is illustrated in 20-59 small signal excitation analysis is described below and illustrated in FIGS . 11-19.
  • the model elements that pertain to the noise model (Ign, Idn and C) are derived from a current/voltage perturbation analysis following similar steps as set forth in the Statz, et al. reference discussed above.
  • the noise model elements are discussed in connection with FIGS. 5-10.
  • T e [°C] T omb + 10 In ⁇ [1 + 0.0001*(F CHSAT /F S ) 2 ] ⁇
  • Gate Noise Perturbation Polarity ⁇ l Apply current/voltage perturbation analysis to the analytically modeled intrinsic charge and conduction in the linear conducting region of the FET's channel (Region 1): a) Apply current perturbation analysis to the current-control expression for drain current in Region 1. b) Find a relationship governing the magnitude of potential fluctuation as a function of position within Region 1, and magnitude of the current perturbation. c) Apply constraint forcing expression above to be consistent with voltage fluctuation boundary conditions at the boundary of Region 1 and the saturated electron transport region of the FET's channel (Region 2). d) Solve for final voltage fluctuation expression at the end of Region 1. e) From Id find the final RMS expression for noise voltage generation seen at the drain terminal, after amplification factors of Region 2 are applied to Id.
  • the derivation of the semi-physical model for equivalent noise sources is similar to the methodology as set forth in the Statz, et al. reference with the following differences.
  • all analysis solutions are determined by solving analytical equations based solely on the device physics whereas the method in accordance with the present invention semi-physical expressions are used.
  • the semi-physical expressions not only model the known physics of device operation but also contain a degree of freedom in the form of empirical expressions and terms. This freedom allows the semi-physical method to compensate for unknown or over-simplified physical expressions in order to achieve relatively accurate measured-to-model fitting characteristics.
  • the application of the known analytical noise models to a new method of expression provides relatively accurate noise modeling that is physically significant.
  • the inaccuracies in known noise models is due to the fact that the analytical expressions for the device physics within the FET do not capture all of the physics that actually occur.
  • the calculated current control and charge boundaries i.e. between Regions 1 and 2 are not accurately modeled, thus leading to further inaccuracies in the calculated noise performance since the semi-physical approach in accordance with the present invention is not based solely on the device physics, the semi-physical model in accordance with the present invention is able to compensate for such inaccuracies.
  • the semi-physical model utilizes empirical terms to correct the prediction of the physical part in order to achieve better agreement with actual measured data.
  • the semi-physical expressions for noise generating mechanisms in accordance with the present invention are suitable for use in the noise equivalent circuit illustrated in FIG. 1.
  • the current/voltage perturbation analysis outlined above is performed on the appropriate semi-physical model expressions to obtain semi -physical expressions for the noise generating mechanisms.
  • this method is applied to the semi-physical device model as discussed below accurate noise equivalent circuit models are generated.
  • a four fingered 120 ⁇ m total gate periphery device was measured for S-parameters from 0 to 50 GHz and noise parameters from 26-40 GHz.
  • the device cell was laid out as a typical PiFET layout.
  • the device cell was embedded into a microstrip to facilitate on-wafer testing of the device, as generally illustrated in FIG. 5.
  • the resulting semi-physical modeling equivalent circuit yields relatively accurate measured-to-model results for both small signal and noise performance of the measured device.
  • FIGS. 6 and 7 show the measured-to-model comparisons for measured small signal S-parameters.
  • FIG. 6 illustrates a Smith chart comparing three of the four S-parameters is terms of measured-to-model characteristics.
  • FIG. 8 illustrates the final parameter in terms of magnitude and angle.
  • the equivalent circuit model derived through the semi-physical model methods provides relatively accurate results.
  • FIGS. 8 and 9 illustrate comparisons for the noise parameters as modeled using the semi-physical approach and also a known small signal noise equivalent circuit presently used for the design of low noise circuits.
  • a comparison is derived directly from a measured set of noise parameter data.
  • FIG. 8 illustrates a Smith chart comparing the optimum noise matching impedance Topt.
  • FIG. 9 illustrates the minimum noise figure, NFmin in terms of a frequency response plot. In the case of Fopt, the simulated results of the semi-physically modeled noise equivalent circuit model almost exactly matches that of the previous noise equivalent noise circuit model.
  • FIG. 10 illustrates the measured-to-model noise figure for a K-band MMIC (microwave monolithic integration circuit) low noise amplifier illustrated in FIG. 10.
  • the previous noise model predicts a much lower noise figure than it actually measured because it models NFmin as being lower.
  • the semi-physical model provides model elements for the standard small signal equivalent circuit model or FET as illustrated in FIG. 11.
  • the model elements are derived from small signal excitation analysis of the intrinsic charge and electric fields within the device.
  • the simulated small signal model elements represent a relatively accurate physical equivalent circuit description of a physical FET.
  • the general methodology for the semi-physical modeling of intrinsic charge, electrical conductance and electrical field is as set forth below. First, the relationships between the conduction band offsets, electrical permitivities and material composition for the various materials in the epi stack are determined. These relationships can be performed analytically or by fitting simulated data from physical simulators. Subsequently, the basic electron transport characteristics in any of the applicable bulk materials in the epi stack are determined.
  • the undeleted linear channel mobility is determined either through material characterization or physical simulation. Subsequently, the Schottky barrier height value or expressions are determined. Once the Schottky barrier height value is determined, the semi-physical equations are constructed modeling the following characteristics:
  • FIG. 12 illustrates a set of relatively accurate measured-to-modeled I-N characteristics for a HEMT using the semi-physical modeling discussed herein. In particular, FIG.
  • FIG. 12 illustrates the drain-to-source current I ds as a function of the drain-to-source voltage N ds for various gate biases, for example, from 0.4N to -1.ON.
  • solid lines are used to represent the semi-physical model while the Xs are used to represent measured values.
  • a close relationship exists between the measured values and the modeled parameters.
  • FIG. 15 relates to a blown up T-gate characteristic which is correlated to the parameters identified in Table 2.
  • the semi-physical modeling of the intrinsic charge and electric field within the HEMT device is initiated by determining the relationships between the conduction band offset, electrical permitivities and material composition for the various materials in the epi stack.
  • Material composition related band offset and electrical permitivity relationships may be obtained from various references, such as "Physics of Semiconductor Devices," by Michael Shur, Prentice Hall, Englewood Cliffs, New Jersey 1990.
  • the basic electron transport characteristics, for example, for the linear mobility of electron carriers in the bulk GaAs cap layer may be determined to be 1350cm 2 /Vs, available from "Physics of Semiconductor Devices", supra.
  • the linear mobility of electron carriers in the undeleted channels is assumed to be 55 OOcnrVNs .
  • This value may be measured by Hall effect samples which have epi stacks grown identically to the stack in the example, except for some differences in the GaAs cap layer.
  • the Schottky barrier height is assumed to be 1.051 volts, which is typical of platinum metal on a AlGaAs material.
  • Threshold Voltage V ⁇ o M ⁇ b - ⁇ E 0 - V ⁇
  • Ns represents the model sheet carrier concentration within the active channel.
  • Ns' represents the ideal charge control law and is modeled as a semi- physical representative of the actual density of state filling rate for energy states within the chaimel v. gate voltage.
  • the gate-to-channel voltage used for the charge control, Ngt is a function of the Schottky barrier height, conduction band offsets and doping in the epi stack as is known in the art.
  • the following equation represents the semi-physical expressions used to model the bias dependence of linear channel mobility in depleted regions.
  • Depleted Channel Mobility ⁇ av ⁇ [c ⁇ v7V*s] Fixed Depleted Channel Mobility ⁇ dch ar ⁇ [ cr " 2/v * s ] Depleted Channel Mobility Gate Bias Factor ⁇ d ⁇ [cm 2 V 2 *s]
  • the following equations are the semi-physical expressions used to model the bias dependence of saturating electric field and saturation velocity.
  • FIG. 16 is a schematically illustrates how electrical conductance in the source and drain access regions are modeled in the example.
  • Source Access Resistance Channel and Cap "sundepCap l ⁇ * ⁇ m l R s seriously[D sg -(REC s3 +L g /2)] Rs d . pR .TM*l «R,'tanh ⁇ [KC 1K * ( V a ,-VC (0n+ V d ,*MC (L )l + 1 ⁇ /2- /2*[1-tanh(KR, K (V g ,-VR, 0n ))] ⁇ * ⁇ tanh [
  • Equivalent circuit element Cgs and Cgd takes the form of delta(Nsn)/delta(Ngs)*Lgn, where delta ( ⁇ sn) is the appropriate charge control expression, and Lgn is the gate source or gate drain charge partitioning boundary length.
  • Equivalent circuit element Ri Lgs/(Cgschannel * vs) where Cgs channel is the portion of gate source capacitance attributed to the channel only, and vs is the saturated electron velocity.
  • Cds is taken to be the sum of the appropriate fringing capacitance Semi-Physical models, or can take the form of delta( ⁇ sd)/delta(Vds')*Xsat, were Nsd is the charge control expression for charge accumulation between the appropriate source and drain charge boundaries, and Xsat is the length of the saturated region, if in saturation.
  • the RF performance can be predicted at an arbitrary bias point.
  • Table 4 represents a comparison of the values for a high frequency equivalent circuit model derived from equivalent circuit model extraction from and semi-physical modeling for the sample illustrated in Table 3.
  • results of the semi-physical modeling method produce a small-signal equivalent circuit values which are relatively more accurate than the physical device simulator in this case. Furthermore, given the differences in the parasitic embedding, treatment of the two approaches, the results given in Table 3 yield much closer results than a comparison of equivalent circuit values.
  • Table 4 lists the values of parasitic elements used in the model derivations.
  • FIG. 60 illustrates the semi-physically simulated bias equations of the small signal Gm compared to measured data.
  • FIG. 61 illustrates the semi-physically simulated bias-dependence of the small-signal Rds.
  • V DSAT M Drain-Saturated Region voltage drop
  • V ⁇ M V d5 / [1+(V ds V sataschreibH 1 ""
  • Empirical Fringing capacitance-bias shaping expression ⁇ f-forml [] ⁇ 1 - tanh[ KC fK ( V g5 - VC (0n + V d5 MC fL )] ⁇ / 2
  • FIG. 63 shows the semi-physically simulated bias-dependence of the small-signal Ri.
  • FIG. 64 shows the semi-physically simulated bias-dependence of the on-mesa parasitic access resistances, Rs and Rd.
  • the following example verifies how the semi-physical small-signal device model is able to provide accurate projections for bias-dependent small-signal performance.
  • the same semi-physical device model as used in the previous examples was used because the example MMIC circuit was fabricated utilizing the same HEMT device technology.
  • the bias-dependence small-signal gain and noise performance of a two-stage balanced K-band MMIC LNA amplifier is replicated through microwave circuit simulation using small signal and noise equivalent circuits that were generated by the semi-physical model.
  • the results of the measured and modeled results are shown below in Table 5. As seen from these results, the semi-physical device model was able to accurately simulate the measured bias-dependent performance, even though the bias variation was quite wide.
  • Vds 0.5 V 15.2 dB 15.8 dB 2.97 dB 2.77 dB
  • Vds 1.0 V 20.6 dB 21.0 dB 2.29 dB 2.20 dB
  • Vds 2.0 V 19.8 dB 20.2 dB 2.25 dB 2.15 dB
  • Vds 3.0 V 18.9 dB 19.1 dB 2.30 dB 2.11 dB
  • Vds 3.5 V 18.4 dB 18.5 dB 2.34 dB 2.18 dB
  • Vds 4.0 V 18.0 dB 18.0 dB 2.37 dB 2.27 dB
  • Vds 2.0 V 16.4 dB 18.0 dB 2.45 dB 2.21 dB
  • Vds 2.Q V 21.4 dB 20.9 dB 2.38 dB 2.21 dB
  • Vds 2.0 V 22.2 dB 21.0 dB 2.65 dB 2.6 dB
  • Vds 3.0 V 21.4 dB 20.3 dB 2.71 dB 2.61 dB
  • FIG. 65 A plot of measured vs. modeled gain for the values listed in Table 3, above, is shown in FIG. 65.
  • the following example verifies how the semi-physical small-signal device model is able to provide accurate projections for physically dependent small-signal performance.
  • the same semi-physical device model as used in the 0 previous examples was used.
  • FIGS 66A and 66B show schematically the kind of data that is extracted and recorded from measured device I-N's during PCM testing. Since the semi-physical device model is able to simulate I-N's, it was able to simulate the variation of I-N's due to physical process variation. These I-N's were analyzed in the same fashion to extract the same parameters that are recorded for PCM testing.
  • Figures 67, 68 and 69 show how accurately the simulated results match with measured process variation.
  • Figure 67 shows how the semi-physically simulated Ngpk and Gmpk match with actual production measurements.
  • Figure 68 shows how simulated Idpk and Gmpk match, also.
  • Figure 69 shows how simulated Imax and Npo also match very well.
  • Small-signal S-parameter measurements are also taken in process for process control monitoring. These measurements are used to extract simple equivalent circuit models that fit the measured S-parameters. Since the semi-physical device model is able to simulate these equivalent circuit models, it was able to simulate the variation of model parameters due to physical process variation.
  • Figures 70 and 71 show how accurately the simulated results match with measured/extracted process variation for the small-signal model parameters.
  • Figure 70 shows how the semi-physically simulated Rds and Gm match very well with actual extracted model process variation
  • the S-parameter microscopy (SPM) method utilizes bias dependent S-parameter measurements as a form of microscopy to provide qualitative analysis of the internal charge and electrical field structure of the semiconductor device heretofore unknown. Pseudo images are gathered in the form of S-parameter measurements extracted as small signal models to form charge control maps. Although finite element device simulations have heretofore been used to calculate the internal charge/electric field of semiconductor devices, such methods are known to be relatively inaccurate.
  • the S-parameter microscopy provides a relatively accurate method for determining the internal charge and electric field within a semiconductor device. With accurate modeling of the internal charge and electric field, all of the external electrical characteristics of semiconductor devices can be relatively accurately modeled including its high frequency performance. Thus, the system is suitable for making device technology models that enabled high frequency MMIC yield analysis forecasting and design for manufacturing analysis.
  • S-parameter microscopy is similar to other microscopy techniques in that SPM utilizes measurements of energy reflected to and from a sample to derive information. More particularly, SPM is based on transmitted and reflective microwave and millimeter wave electromagnetic power or S-parameters. As such, S-parameter microscopy is analogous to the combined operation of scanning and transmission electron microscopes (SEM and TEM). Scattered RF energy is analogous to the reflection and transmission of the electron beams in the SEM and TEMs. However, instead of using electron detectors as in the SEM and TEMs, reflectometers in a network analyzer are used in S-parameter microscopy to measure a signal. S-parameter microscopy is similar to other microscopy techniques in that both utilize; measurement of scattering phenomenon as data; include mechanisms to focus measurements for better resolution; and include mechanisms to contrast portions of the measurement to discriminate detail as shown in Table 7 below: Table 7
  • RESULT Detailed "images" of device's internal charge and electric field structure.
  • S-parameter microscopy does not relate to real images, but are used provide insight and qualitative detail regarding the internal operation of a device. More specifically, S-parameter microscopy does not provide visual images as in the case of traditional forms of microscopy. Rather, S- parameter microscopy images are more like maps which are computed and based on a non-intuitive set of measurements.
  • FIG. 20 illustrates a conceptual representation of an S-parameter microscope, generally identified with the reference numeral 20.
  • the S-parameter microscope 20 is analogous to a microscope which combines the principles of SEM and TEM. Whereas SEM measures reflections and TEM measures transmissions, the 2-port S-parameter microscope 20 measures both reflective and transmitted power.
  • data derived from the 2-port S-parameter microscope contains information about the intrinsic and extrinsic charge structure of a device. More particularly, as in known in the art, SEM provides relatively detailed images of the surface of a sample through reflected electrons while TEM provides images of the internal structure through transmitted electrons. The reflective signals are used to form the external details of a sample while transmitted electrons provide information about the interior structure of a device.
  • S-parameter microscopy utilizes a process of measuring reflective and transmitted signals to provide similar "images" of the charge structure of a semiconductor device.
  • the internal and external electrical structure of a semiconductor device are commonly referred to as intrinsic device region and 22 and extrinsic parasitic access region 24 as shown in FIG. 21.
  • parasitic components associated with its electrodes and interconnects which are not shown. These are so-called device “layout parasitics”.
  • the ports 26 and 28 are emulated by S-parameter measurements.
  • the S-parameter measurements for a specific semiconductor device, generally identified with the reference number 30, are processed in accordance with the present invention to provide charge control maps, shown within the circle 32, analogous to images in other microscopy techniques.
  • These charge control maps 32 are expressed in the form of equivalent circuit models.
  • linear circuit elements are used in the models to represent the magnitude and state of charge/electric fields inside the semiconductor device 30 or its so-called internal electrical structure.
  • the position of the circuit elements within the model topology is roughly approximate the physical location within the device structure, hence the charge control map represents a diagram of the device's internal electrical structure, hence the above charge control map represents a diagram of the device's internal electrical structure.
  • the S-parameter microscope 20 in accordance with the present invention also emulates a lens, identified with the reference numeral 40 (FIG. 20).
  • the lens 40 is simulated by a method for the extraction of a unique equivalent circuit model that also accurately simulates the measured S- parameter. More particularly, parameter extraction methods for equivalent circuit models that simulate S-parameters are relatively well known. However, when the only goal is accurately fitting measuring S-parameters, an infinite number of solutions exist for possible equivalent circuit parameter values. Thus, in accordance with an important aspect of the present invention, only a single unique solution is extracted which accurately describes the physical charge control map of the device. This method for unique extraction of equivalent circuit model parameters acts as a lens for focus the charge control map solution.
  • the lens 40 is subsequently simulated by a filter that is based on an apparent layout parasitic embedding model.
  • the layout parasitic embedding model consists of linear elements which simulate the effect of the device's electrodes and interconnects upon its external electrical characteristics.
  • a Pi FET embedding model 42 as described below. This model effectively acts as a filter to remove the electrical structure of the extrinsic parasitic access contribution to the preliminary charge control map solution.
  • the resultant filtered charge control map solution represents a clearer "image", which shows only the electrical stracture of the intrinsic device. This enhanced imaging is needed in order to achieve as accurate a view of the internal electric charge/field as possible.
  • the S-parameter microscope 20 in accordance with the present invention is able to relatively accurately model the internal electric charge/field structure within a semiconductor device.
  • FIG. 26 An exemplary application of the S-parameter microscope is illustrated in detail below.
  • an exemplary GaAs HEMT device with four gate fingers and 200 ⁇ m total gate periphery formed in a Pi-FET layout as generally illustrated in FIG. 26 and identified with the reference numeral 43 is used.
  • the GaAs HEMT 43 is adapted to be embedded in a 100- ⁇ m pitch coplanar test structure to facilitate on wafer S-parameter measurement.
  • FIGS. 27 and 28 the I-N characteristics for the device are measured.
  • the drain source current Ids is plotted as a function of drain-to-source voltage Nds at various gate voltages Ngs as shown in FIG.27.
  • FIG. 27 the drain source current Ids is plotted as a function of drain-to-source voltage Nds at various gate voltages Ngs as shown in FIG.27.
  • Ids drain-to-source current
  • Gm transconductance
  • Table 8 shows the bias conditions in which S-parameters were measured.
  • the S- parameters were measured from 0.05 to 40 GHz at each bias condition.
  • F I G . 2 9 illustrates a Smith chart illustrating the measured S-parameters Sll, S 12 and S22 for frequencies from 0.05 to 40.0 GHz.
  • FIG. 30 is a graphical illustration of magnitude as a function of angles for the measured S-parameter S21 for frequencies from 40.05 to 40.0 GHz.
  • Table 9 represent solutions that are close to the charge control map and represent physically significant solutions of the FET's electrical structure. However, the values represented in Table 9 contain the influence of external layout parasitics which are subtracted using a model for the embedding parasitics to obtain the most accurate charge control mapping to the intrinsic device characteristic.
  • an embedding model is applied to filter the extracted equivalent circuit model values to obtain values more representative of the intrinsic device.
  • a PiFET embedding parasitic model is used to subtract capacitive contributions due to interelectrode and off-mesa layout parasitic influences.
  • FIGS. 31-34 illustrate the bias dependent charge control maps for the parameters RS, RD, RI, CGS and CGD as a function of bias. More particularly, FIG. 31 illustrates a charge control map of the charge and electric field distribution in the on-mesa source access region illustrated by the source resistance R s as a function of bias.
  • FIG. 31 illustrates a charge control map of the charge and electric field distribution in the on-mesa source access region illustrated by the source resistance R s as a function of bias.
  • FIG. 32 illustrates a charge control map of the charge and electric field distribution in the on-mesa drain access region illustrated by the drain resistance R d as a function of bias.
  • FIG. 33 illustrates a charge control map for a non-quasistatic majority carrier transport illustrated by the intrinsic device charging resistance R ; as a function of gate bias for different drain bias points.
  • FIG. 34 illustrates a charge control map for gate modulated charge and distribution under the gate shown with the gate capacitance CGS and CGD as a function of bias.
  • the S-parameter microscope 20 utilizes a filter to provide a clearer charge control map for modeling the internal electric charge/field of a semiconductor device.
  • the filter is illustrated in connection with the
  • PiFETs are devices in which the gate fingers and the edge of the active region resemble the greek letter ⁇ , as illustrated.
  • Such PiFET layouts facilitate construction of multi fingered large periphery device cells, for example, as illustrated in FIG 36.
  • the multi-finger semiconductor device is modeled as a combination of single finger device cells.
  • Each single finger device cell is represented by a hierarchy of four models, which, in turn, are assembled together using models for interconnects to represent an arbitrary multifingered device cell, illustrated in Fig.
  • the four models are as follows: off mesa or boundary parasitic model; interelectrode parasitic model; on-mesa parasitic model and intrinsic model.
  • the off-mesa parasitic model is illustrated in FIG. 38. This model represents the parasitics that exist outside the active FET region for each gate finger. In this model, the fringing capacitance of each gate finger off the active device region as well as the off-mesa gate finger resistance is modeled.
  • FIGS. 39-41 The interelectrode parasitic model and corresponding equivalent circuit are illustrated in FIGS. 39-41.
  • This model represents parasitics between the metal electrodes along each gate finger.
  • the following fringing capacitance parasitics are modeled for the gate-to-source air bridge; drain-to-source air bridge; gate-to-source ohmic; gate-to-drain ohmic and source-to-drain ohmic as generally illustrated in
  • FIG. 25 is a diagrammatic representation of FIG. 25.
  • the on-mesa parasitic model and corresponding equivalent circuit are illustrated in FIGS. 42 and 43.
  • This model represents that parasitics around the active FET region along each gate finger including various capacitance fringing parasitics and resistive parasitics .
  • the gate-to-source side recess; gate- drain-side recess; gate-source access charge/doped cap; and gate-drain access charge/doped cap capacitance fringing parasitics are modeled.
  • the gate metallization and ohmic contact resistive parasitics are modeled.
  • the intrinsic model and corresponding equivalent circuit are illustrated in FIGS. 44 and 45.
  • the intrinsic model represents the physics that predominately determine the FET performance.
  • the DC and current voltage response can be determined by physics based analytical equations for magnitude and location of intrinsic charge which are generally know in the art, for example, as disclosed in "Nonlinear Charge Control in AlGaAs/GaAs Modulator-Doped FETs", by Hughes, et al. IEEE Trans. Electron Devices. Vol. ED-34, No.8, August 1987.
  • the small signal model performance is modeled by taking a derivative of the appropriate charge or current control equations to derive various terms such as RI, RJ, RDS, RGS, RGD, GM, TAU, CGS, CDS and CGD.
  • FIGS. 46A-53 An example of a parasitic model for use with the S-parameter microscopy discussed above is illustrated in FIGS. 46A-53.
  • a Pi-FET is illustrated. As shown, the PiFET has four gate fingers. The four fingered Pi-FET is modeled in FIG. 46B.
  • FIG 46B illustrates an equivalent circuit model for Pi-FET illustrated in FIG. 46A as implemented by a known CAD program, for example, LIBRA 6.1 as manufactured by Agilent Technologies. As shown, the equivalent circuit models does not illustrate all of the equivalent circuit elements or network connections involved with implementing the parasitic embedding models, but rather demonstrates a finished product. The actual technical information regarding the construction of the network and its equivalent circuit elements are normally provided in schematic view.
  • FIGS.47-48 demonstrate the application of the parasitic model for use with the S-parameter microscopy.
  • An important aspect of parasitic modeling relates to modeling of multi-gate fingered devices as single gate finger devices.
  • a single unit device cell refers to a device associated with a single gate finger.
  • a four fingered Pi-FET as illustrated in FIG. 46A is modeled as four unit device cells.
  • the four finger Pi-FET illustrated in FIG. 46A is modeled as a single finger unit device cell 100 with an intrinsic model 102, as shown in FIGS. 47 and
  • the Pi-FET intrinsic FET model 104 is substituted for the block 102 defining a first level of embedding.
  • the parameter values for the Pi-FET intrinsic model are added together with the parameter values for the single fingered unit device cell intrinsic model.
  • the intrinsic device model 104 may be developed by S-parameter microscopy as discussed above.
  • the interconnect layout parasitic elements are added to the equivalent model by simply adding the model terms to the value of the appropriate circuit element to form a single unit device cell defining a second level of embedding. Once the single unit device cell is formulated, this device is used to construct models for multi-fingered devices.
  • a Pi-FET with four gate fingers is modeled as four single finger device unit cells as shown in FIG. 50.
  • the off-mesa layout parasitic elements are connected to the multi- fingered layout, defining a third level of embedding as illustrated in FIG.51.
  • These off-mesa layout parasitic elements are implemented as new circuit elements connected at key outer nodes of the equivalent circuit structure.
  • a fourth level of embedding is implemented as generally illustrated in FIG. 55.
  • an inductor model is connected to the sources of each of the various unit device cells to represent the metallic bridge interconnection, as generally shown in FIG. 52.
  • a fifth level of embedding is implemented in which the feed electrodes model 114 and 116 are modeled as lumped linear elements (i.e. capacitors inductors) as well as the distributive elements (i.e. microstrip lines and junctions) to form the gate feed and drain connections illustrated in FIG. 53.
  • the distributive elements are distributed models for microstrip elements as implemented in LIBRA 6.1.
  • FIGS . 54-59 The method for determining FET equivalent circuit parameters as discussed above is illustrated in FIGS . 54-59. This method is based on an equivalent circuit model, such as the common source FET equivalent circuit model illustrated in FIG. 8.
  • a model is initially generated in step 122.
  • the model illustrated in FIG. 23 is used as a small signal model for the FET.
  • the equivalent circuit parameters are based upon measured FET S-parameters. Measurement of S-parameters of semiconductor devices is well known in the art.
  • FIG. 57A is a Smith chart illustrating exemplary measured S-parameters Sl l, S 12 and S22 for frequencies between 0.05 to 40 GHz.
  • step 42B represents a magnitude angle chart for the measured S-parameter S21 from frequencies from 0.05 to 40 GHz.
  • each impedance point in Table 4 is processed by the blocks 130, 132, etc. to develop model parameter values for each of the impedance point in order to develop an error metric, which, in turn, is used to develop a unique small signal device model, as will be discussed below.
  • the processing in each of the blocks 130, 132 is similar.
  • only a single block 130 will be discussed for an exemplary impedance point illustrated in Table 10.
  • the feedback impedance point 17 which correlates to a source resistance R s ohm of 1.7 ⁇ and a source inductance L s of 0.0045pH is used.
  • initial intrinsic equivalent circuit parameters and initial parasitic equivalent circuit parameter are determined, for example, by the Minasian algorithm discussed above and illustrated in Tables 11 and 12 as set forth in steps 134 and 136.
  • step 138 the simulated circuit parameters are compared with the measured S-parameters, for example, as illustrated in FIGS. 58A and 58B.
  • Each of the processing blocks 130 and 132 etc. goes through a fixed number of complete cycles, in this example, six complete cycles. As such, the system determines in step 140 whether the six cycles are complete.
  • Each cycle of the processing block 130 consists of a direct extraction followed by an optimization with a fixed number of optimization iterations, for example 60.
  • a fixed “distance" or calculation time which the model solution must be derived is defined.
  • the algorithm implements a convergence speed requirement of the global error metric by setting up an environment where each trial model solution competes against each other by achieving the lowest fitting error over a fixed calculation time thus causing a "race” criteria to be implemented where "convergence speed" is implicitly calculated for each processing block 130, 132 etc.
  • the system determines whether the racing is done in step 140, the system proceeds to block 142 and optimizes model parameters.
  • Table 14 illustrates the optimized intrinsic equivalent parameter values using commercially available software, such as LIBRA 3.5. These values along with the optimized parasitic values, illustrated in Table 15, form the first optimized model solution for the first extraction-optimization cycle (i.e. one of six). The optimized model parameters are then fed back to the function block 134 and 136 (FIG. 54 A) and used for a new initial model solution. These values are compared with the measured S-parameter value as illustrated in FIGS. 58A and 58B. The system repeats this cycle for six cycles in a similar fashion as discussed above.
  • the extraction-optimization algorithm makes the final optimization fitting error for each point implicitly carry information about both the measured to model fitting error and the speed of convergence. It does so by the fixed optimization time constraint which sets up a competitive race between the various trial model solutions.

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Abstract

L'invention concerne un modèle de dispositif semi-physique (figure 2) pouvant représenter avec précision des caractéristiques physiques connues du dispositif ainsi que des caractéristiques de bruit mesurées. Le modèle de dispositif semi-physique selon l'invention (figure 2) utilise des expressions analytiques pour modéliser la charge fonctionnelle de la structure de champ électrique d'une structure interne de transistor HEMT. Ces expressions sont basées sur la physique du dispositif, mais sont empiriques dans la forme. En tant que tel, le modèle est capable de conserver les dépendances physiques avec grande fidélité tout en conservant des caractéristiques de bruit relativement précises de la mesure au modèle. Le modèle semi-physique selon l'invention fournit également des éléments de modèle pour un modèle de circuit équivalent au bruit d'un transistor FET. En particulier, les éléments de modèle du générateur de bruit sont dérivés d'une analyse de perturbation courant/tension des champs électriques et de charge intrinsèques, comme modélisé à l'intérieur du dispositif par le modèle HEMT semi-physique. Les éléments de modèle de bruit simulés représentent une description d'équipement physique relativement précise du transistor FET physique. Comme les éléments de modèle sont dérivés d'un modèle de charge intrinsèque, le performance RF peut être prédite à un point de polarisation arbitraire.
EP01930749A 2000-04-28 2001-04-25 Modelisation semi-physique de modeles de circuit equivalents au bruit haute frequence d'un transistor hemt Withdrawn EP1285366A1 (fr)

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