EP1282137B1

EP1282137B1 - Redundancy circuit and method for replacing defective memory cells in a flash memory device

Info

Publication number: EP1282137B1
Application number: EP02255361A
Authority: EP
Inventors: Stella Matarrese; Luca Giovanni Fasoli
Original assignee: STMicroelectronics lnc USA
Current assignee: STMicroelectronics lnc USA
Priority date: 2001-08-02
Filing date: 2002-07-31
Publication date: 2008-09-10
Anticipated expiration: 2022-07-31
Also published as: JP2003077290A; US6594177B2; US20030026131A1; EP1282137A1; DE60228797D1

Description

The present invention relates to a redundancy technique for nonvolatile memory devices, and particularly to a circuit and method for replacing defective memory cells in a nonvolatile memory device based upon the type of defect.
The first nonvolatile memories were electrically programmable read-only memories (EPROMs). In these memories, the memory cells include a floating-gate transistor that is programmable using the hot carrier effect. Programming of an EPROM memory cell includes applying a potential difference between the drain and the source of the floating gate transistor in the presence of a high potential difference (of about 20 volts, this value varying according to the desired programming speed) between the control gate and the source. The application of the first of these potential differences generates an electrical field that gives rise to a flow of electrons in the channel. These electrons collide with atoms of the channel, causing the appearance of new free electrons. These electrons have very high energy (hence the term "hot carriers"). The high difference in potential between the control gate and the source of the floating gate transistor gives rise to a strong electrical field between the floating gate and the substrate, the effect of which is that certain of these electrons are injected into the floating gate, thus putting the memory cell in a state known as a "programmed" state.
The fact that the programming of a memory cell requires the application of voltages both to the control gate and to the drain of the floating-gate transistor eliminates the need for the use of a selection transistor to program one particular memory cell without programming the others. This results in a relatively small silicon area and the effectuation of large scale integration . By contrast, the erasure of all the memory cells of the memory is done substantially simultaneously by exposing the memory cells to ultraviolet radiation.
In addressing the need to individually erase EPROM memory cells, electrically erasable programmable read only memories (EEPROMs) were created. These memories are electrically programmable and erasable by tunnel effect (i.e., the Fowler Nordheim effect). The memory cells have a floating-gate transistor whose drain is connected to the bit line by a selection transistor. The gate of the selection transistor is connected to the word line. The gate of the floating-gate transistor is controlled by a bias transistor. Generally, the source of the floating gate transistor is connected to a reference potential, such as ground. These floating-gate transistors have an oxide layer between the substrate and the floating gate that is very thin to enable the transfer of charges by tunnel effect. The advantage of EEPROMs as compared with EPROMs lies in the fact that each memory cell is programmable and erasable independently of the other EEPROM cells. The tradeoff here is that a larger surface area of silicon is required and therefore a smaller scale of integration is achieved.
A third type of memory has more recently gained popularity. This type of memory, flash EPROMs, combines the relatively high integration of EPROMs with the ease of programming and erasure of EEPROMs. Flash memory cells can be individually programmed utilizing the hot carrier effect in the same way as EPROM cells are programmed. Flash memory cells are also electrically erasable by the tunnel effect. The memory cells of a flash EPROM memory includes a floating-gate transistor that has an oxide layer whose thickness is greater than the oxide layer thickness of an EEPROM floating gate transistor but smaller than the oxide layer thickness of an EPROM floating gate transistor. Consequently, the flash memory cell is capable of erasure by the tunnel effect. For erasure, a highly negative potential difference is created between the control gate and the source of the floating gate transistor, the drain being left in the high impedance state or connected to the ground potential so that a high electrical field is created which tends to remove the electrons from the floating gate.
Referring to Figure 1, flash EPROM devices, hereinafter referred to as flash memory devices, typically include at least one array A of flash memory cells organized into rows and columns of flash memory cells. Array A is typically partitioned into blocks B, each of which is further divided into sectors S. Each column of memory cells is coupled to a distinct local column line. Array A typically includes a plurality of main column lines. A plurality of local column lines are selectively connected to each main column line. Each local column line is connected to a distinct column of memory cells. Having the columns of memory cells and local column lines divided into sectors allows for erase operations to be performed on sectors of memory cells. Main column lines are also used to route a signal appearing on a local column line to the periphery of array A without an appreciable time delay or signal degradation. The use of local and main column lines in flash memory devices is known in the art.
A row decoder R and column decoder C are used to select a single row and at least one column of memory cells based upon the value of an externally generated address applied to the flash memory device. Sense amplifiers SA are coupled to the main column lines to amplify the voltage levels on the addressed column lines corresponding to the data values stored in the addressed flash memory cells. The particular implementations of array A, the row and column decoders and sense amplifiers SA are known in the art and will not be described further for reasons of simplicity.
Redundancy has been previously utilized in flash memory devices to, among other things, replace columns of memory cells having a defect with redundant columns of memory cells so as to improve manufacturing yield. Redundant columns RC are disposed in or immediately adjacent each block B. Each block B has a distinct set of redundant columns RC, as shown in Figure 1. A redundant column RC is adapted to replace a column of flash memory cells having a defect (i.e., a defective column) in the block B with which redundant column RC is associated. Nonvolatile storage components SC, which may be maintained in a secondary array of memory cells, are utilized to identify whether the redundant columns RC are used to replace a defective column.
In one existing flash memory design, defective regular columns of memory cells are individually replaced with redundant columns of memory cells. A single storage component SC is associated with a distinct redundant column RC. Each storage component SC is capable of storing the column address of the defective column that the associated redundant column RC replaces, together with an enable bit to enable the column replacement during a memory access operation. This type of existing flash memory device is thereby capable of individually replacing defective columns in the flash memory array A with redundant columns of redundant memory cells. This existing redundancy strategy is more efficient in overcoming random failures appearing in array A, and is less efficient in overcoming clusters of failures therein.
In another existing flash memory design, main column lines and the columns of memory cells associated therewith are replaced as a set. Specifically, a storage component is capable of identifying for replacement a main column line and columns of memory cells associated therewith in a single block, together with an enable bit to enable the replacement during a memory access operation. This type of existing flash memory device is thereby capable of replacing defective columns in a set with a set of redundant columns RC of redundant memory cells. This existing redundancy strategy is more efficient in overcoming clusters of failures appearing in array A and less efficient in handling random failures in array A. Both of the above-described existing flash memory designs are relatively inflexible in that the storage components SC in each case are only available for efficiently overcoming a certain type of defect.
In addition to each of the above-described redundancy schemes being limited in efficiently replacing different types of defects, the ability of the above-described existing flash memory devices to replace defective columns of memory cells is limited as the number of defective columns increases. This reduced inability is due in part to the fact that the maximum number of redundant columns that can be used in a single word is equal to the number of sense amplifiers SAR used for sense amplification of the redundant columns RC. The reduced inability is also due to the fact that the maximum number of defective columns that can be replaced in any block B is equal to the number of redundant columns RC in a block B.
Based upon the foregoing, there is a need to more efficiently replace defective columns in flash memory devices.
WO-9631882 describes an integrated memory array circuit such as a Dynamic Random Access memory (DRAM), has global array bit lines, each of which is connected hierarchically above a plurality of electrically isolatable sub-array bit lines. Each sub-array bit line is connected hierarchically above a plurality of memory cells. The memory cells are selectively coupled to the sub-array bit lines using word lines.
It further has a redundancy logic controller (RCL) which either deactivates or omits activating the defective array structure component while reassigning therefore a redundant memory array structure component. The RCL stores addresses of the activated redundant sub-array structures.
US 5808945 describes a semiconductor memory wherein memory cells are arranged in a matrix and word lines or bit lines have hierarchical structures, where the efficiency of redundancy is increased by replacing a defective memory cell existing in a column or row by a subword line unit or a sub bit line unit.
US 5966366 describes a redundancy technique for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings and spare bit lines, where the redundancy circuit stores a defective address within the memory array.
Embodiments of the present invention overcome shortcomings in prior flash memory devices and satisfy a significant need for a flash memory device having improved repair probability for the redundant circuitry provided.
There is provided according to the invention a nonvolatile memory device, comprising a plurality of sectors of memory cells arranged relative to each other so as to form an array of memory cells wherein the sectors are grouped into blocks of memory cells, with each block comprising one or more sectors, each sector comprising a plurality of memory cells arranged into rows and columns, the columns of memory cells including addressable regular columns of memory cells and redundant columns of memory cells; a plurality of local column lines, each local column line being coupled to a distinct column of memory cells in the sector; and the memory device further comprising a plurality of main column lines which extend substantially from one side of the array substantially to an opposed side thereof, each main column line being coupled to a plurality of local column lines in the sectors; address decode circuitry for receiving an externally generated address and selecting a row, at least one of the regular columns of memory cells and at least one of the main column lines based upon the externally generated address; at least one set of storage elements capable of storing information identifying for replacement one of the regular columns of memory cells and one of the main column lines; and redundancy circuitry for selectively and individually replacing the selected at least one of the regular columns of memory cells with at least one of the redundant columns of memory cells, and selectively replacing the selected at least one of the main column lines together with the corresponding regular columns of memory cells coupled thereto with a redundant main column line and corresponding redundant columns of memory cells coupled thereto; characterized by the at least one set of storage elements further comprising a bit indicating whether said redundancy circuitry is arranged to selectively and individually replace the selected one of the regular columns of memory cells identified by the information identifying for replacement one of the regular columns in the set of storage elements; or selectively replace the selected one of the main column lines identified by the information identifying for replacement one of the main column lines together with the corresponding regular columns of memory cells coupled thereto.
According to a second aspect of the present invention there is provided a method of performing a memory read operation on a nonvolatile memory device comprising an array of memory cells arranged into rows and columns, the columns of the memory cells including addressable regular columns of memory cells and redundant columns of memory cells, each regular column of memory cells being connected to a local column line, wherein the memory device array is partitioned into sectors with multiple sectors being grouped into one or more blocks, a plurality of main column lines extending substantially from one side of the array substantially to an opposed side thereof, each main column line being coupled to a plurality of local column lines and at least one set of storage elements, the method comprising receiving an address corresponding to a row and at least one regular column of memory cells; selecting the row of memory cells, the at least one regular column of memory cells and at least one main column line corresponding to the received address; searching the at least one set of storage elements and determining whether the at least one set of storage elements identifies for replacement the selected at least one regular column of memory cells and the selected at least one main column line; and characterized by at least one set of storage elements further comprising a bit wherein based upon the searching and the bit value, selectively and individually replacing the selected at least one of the regular columns of memory cells with at least one of the redundant columns of memory cells identified by the set of storage elements or the selected at least one of the main column lines and corresponding regular columns of memory cells coupled thereto, with a redundant main column line identified by the set of storage elements and corresponding redundant columns of memory cells coupled thereto.
A more complete understanding of the system and reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein:

Figure 1 is a block diagram of a known flash memory device;
Figure 2 is a block diagram of a flash memory device according to an exemplary embodiment of the present invention;
Figure 3 is a flow chart illustrating an operation of the exemplary flash memory device of Figure 2; and
Figure 4 is a block diagram of a computing/communications device having therein the flash memory device of Figure 2.

The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which an exemplary embodiment of the invention is shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiment set forth herein. Rather, the embodiment is provided so that this disclosure will be thorough and complete.
Referring to Figure 2, there is shown a nonvolatile memory device 1 according to an exemplary embodiment of the present invention. Although it is understood that the nonvolatile memory device 1 may be virtually any type of nonvolatile memory device, nonvolatile memory device 1 will be described below as a bi-level flash memory device for reasons of simplicity.
In general terms, flash memory device 1 includes redundant circuitry for efficiently replacing columns of memory cells 20 having a defect. Flash memory device 1 includes one or more arrays or banks 2 of memory cells 20. Each array 2 of memory cells 20 are arranged into rows and columns 16 of memory cells 20. According to the exemplary embodiment of the present invention, each array 2 is partitioned into sectors 3 of memory cells 20, with multiple sectors 3 being grouped into one or more blocks 30 of memory cells 20. Each block 30 of memory cells 20 includes a plurality of redundant columns 4 of redundant memory cells 20. Each redundant column 4 of redundant memory cells 20 may be capable of replacing any of a plurality of regular (i.e., non-redundant) columns 16 of memory cells 20 in the block 30 in which the redundant column 4 is disposed, as discussed in greater detail below. Although array 2 is illustrated in Figure 2 as being divided into two or more sectors 3 of memory cells 20 that may form one or more blocks 30, it is understood that array 2 may be divided into more than two sectors 3 and blocks 30 of memory cells 20.
Array 2 is shown in Figure 2 as being relatively sparsely populated with memory cells 20 for reasons of clarity. It is understood that array 2 is substantially entirely populated with memory cells 20, arranged in rows and columns of memory cells 20 as described above.
Within each sector 3 of a block, a local column line 5 is connected to a distinct regular column 16 or redundant column 4 of memory cells. In addition, array 2 includes a plurality of main column lines 50 which extend substantially from one side of array 2, such as the top side, to an opposed side thereof. Because columns 16 of memory cells are disposed within sectors 3 so as to effectuate erase operations of memory cells 20 at the sector level, main column lines 50 are utilized to route addressed memory cells to the periphery of array 2. Each main column line 50 is coupled to a plurality of column lines 5 such that any associated column line 5 (and its corresponding column of memory cells) may be connected to a main column line 50 during a memory access operation.
Local columns 16 in different sectors 3 of the same block and having the same address within their respective sectors 3 are replaced by a single redundant column 4.
The redundant columns 4 of each block of memory cells 20 are adapted to replace defective regular columns 16 of memory cells 20 according to a predetermined replacement scheme. For instance, both the regular columns 16 and the redundant columns 4 in a block may be each divided into one or more sets, with each set of redundant columns 4 being capable of replacing columns 16 in a distinct set of regular columns. The particular redundant column 4 of a set of redundant columns that selectively replaces a defective regular column 16 of a set of columns in a block may be based upon the column address of the defective regular column 16. In particular, a portion of the column address of the column(s) to be replaced is used to identify the particular redundant column(s) 4 in the corresponding set of redundant columns 4 to be used in a column replacement. In this way, for a regular given column(s) 16 to be replaced, the redundant column(s) 4 that may selectively used in the replacement may be substantially quickly and simply determined.
Flash memory device 1 may further include row decode circuitry 7 which receives an externally generated address or portion thereof and selects and/or activates a row of memory cells 20 in a sector 3. In particular, the row of memory cells 20 corresponding to the externally generated address is selected and/or activated by being connected to column lines 5. Row decode circuitry 7 may include logic that, for example, in response to receiving an externally generated address, drives a single row line 6 corresponding to the externally generating address to a first voltage level to activate each memory cell in the row, while driving the remaining row lines 6 to another voltage level to deactivate the memory cells 20 in the remaining rows. Row decode circuitry 7 may be implemented with boolean logic gates as is known in the art.
Further, flash memory device 1 may include column decode circuitry 8 which receives an externally generated address and selects one or more columns 16 corresponding to the externally generated address. Column decode circuitry 8 may, for example, be implemented as multiplexing circuitry connected to each column line 5 in array 2 for connecting, based upon the received address, the column lines 5 associated with the addressed columns 16 to their corresponding main column lines 50 and for selecting such main column lines 50. In this way, the local column lines 5 associated with the addressed columns 16, having the data values from the addressed memory cells 20, are provided externally to array 2 for subsequent amplification. Column decode circuitry 8 may include decode circuitry 8a for selecting one or more local column lines 5 associated with the addressed columns 16 as described above, and redundant decode circuitry 8b for selecting one or more column lines 5 associated with redundant columns 4 of redundant memory cells 20. Column decode circuitry 8b connects the column line 5 of one or more redundant columns 4 to redundant main column lines 50 so that data values from selected redundant memory cells 20 are provided externally to array 2 for subsequent amplification.
During a memory read operation, addressed memory cells 20 are connected to the main column lines 50 corresponding thereto, as explained above. Typically, the connection of the addressed memory cells 20 to their corresponding main column lines 50 results in the main column lines 50 being at one of two voltage levels. Flash memory device 1 may include sense amplifiers 9 that sense the voltage levels on the main column lines 50 corresponding to the data stored in the addressed memory cells 20 and drive output signals of the sense amplifiers 9 to voltage levels that are more easily interpreted or otherwise handled by circuitry external to array 2. Sense amplifiers 9 may include sense amplifiers 9a coupled to main column lines 50 of regular columns 16, and sense amplifiers 9b coupled to main column lines 5 of redundant columns 4.
Flash memory device 1 may include a data input/output (I/O) circuit 13 that generally couples addressed memory cells 20 to external I/O data pins 14 of flash memory device 1. As shown in Figure 2, data I/O circuit 13 is coupled to the output of sense amplifiers 9. Flash memory device 1 may also include control circuitry 15 for receiving externally generated, input control signals and controlling the various components of flash memory device 1 (row decode circuitry 7, column decode circuitry 8, sense amplifiers 9, data I/O circuit 13, etc.) to perform memory access operations.
In general terms, flash memory device 1 is adapted to selectively replace individual regular columns 16 of memory cells 20, groups of regular columns 16 that are associated with a main column line 50 in a block, and groups of regular columns 16 in all blocks that are associated with a main column line 50. In this way, flash memory device 1 is capable of efficiently overcoming random defects as well as clusters thereof existing in array 2 associated with local column lines 5 and main column lines 50.
Flash memory device 1 includes a secondary array 10 of memory cells for maintaining a record of column replacements to occur in array 2. Secondary array 10 may include flash memory cells or other non-volatile memory cells/data storage circuits. The memory cells of secondary array 10 is organized into sets 11 of memory cells. According to the exemplary embodiment of the present invention, each set 11 of memory cells in secondary array 10 is capable of identifying for replacement any defective regular column 16 of memory cells 20, or any groups thereof. In other words, each set 11 of memory cells in secondary array 10 is not rigidly associated with only one redundant column 4 of redundant memory cells 20 for replacing a defective regular column 16. In addition, each set 11 of memory cells in secondary array 10 is not rigidly associated with only one group of redundant columns 4 of redundant memory cells 20 for replacing a defective group of regular columns 16. There is no one-to-one correspondence between a set 11 of memory cells in secondary array 10 and a redundant column 4 or group of redundant memory cells 20. Secondary array 10 may be disposed, for example, adjacent to array 2. It is understood, however, that secondary array 10 may be a portion of array 2.
In order to be able to identify any individual column 16 in any block as having a defect, each set 11 of memory cells in secondary array 10 includes a sufficient number of memory cells to store a column address of the defective column 16 as well as the block address to identify the block in which the defective column 16 is located. Each set 11 includes a first sub-set 11a of memory cells capable of storing the column address of a defective column 16, and a second sub-set 11b of memory cells capable of storing the block address of the block in which the defective column 16 is located. A third sub-set 11c of memory cells indicates whether the set 11 has been programmed to store information relating to a defective column 16 in the array 2 of memory cells 20. The third sub-set 11c may be used to enable the replacement of a defective regular column 16 of memory cells 20 with a redundant column 4 of redundant memory cells 20 during a memory access operation.
In order to be able to selectively identify for replacement any group of regular columns 16 of memory cells 20 in an addressed block that is associated with a main column line 50, each set 11 of memory cells in secondary array 10 may further include a fourth sub-set 11d which indicates whether the set 11 corresponds to replacement of a single regular column 16 or a group of regular columns 16 that are coupled to a single main column line 50. The sub-set 11d of a group 11 may be, for example, a single memory cell capable of storing a single data bit. Replacement of a group of regular columns 16 in a block may be performed, for example, upon the presence of a cluster of defects in the block of memory cells 20.
In order to be able to selectively identify for replacement all of the groups of columns 16 of memory cells 20 associated with a main column line 50, each set 11 of memory cells in secondary array 10 includes a fifth sub-set 11e which indicates whether the regular columns 16 associated with a main column line 50 identified for replacement by the set 11 are regular columns 16 in a single block (i.e., a single group of regular columns 16) or in each block having regular columns 16 coupled to the main column line 50 (i.e., a plurality of groups of regular columns 16). In this way, flash memory device 1 may replace some or all of the regular columns 16 associated with a main column line 5. Replacement of all of the columns 16 associated with a main column line 50 may be chosen, for example, upon the existence of a cluster of defects that shorts a local column line 5 with a main column line 50 together, or main column lines 50 together. The value stored in fifth subset 11e may be seen as determining whether an addressed main column line 5 (and its corresponding regular columns 16) is replaced entirely or only with respect to a single block.
Flash memory device 1 may further include redundancy decode circuitry 18 coupled to receive the output of each sense amplifier 9 and selectively replace the output of one or more sense amplifiers 9a associated with a defective column 16 with the output of one or more sense amplifiers 9b associated with redundant columns 4. Redundancy decode circuitry 18 may be implemented, for example, with multiplexing circuitry to effectively replace the output of one or more sense amplifiers 9a with the output of one or more sense amplifiers 9b. Redundancy decode circuitry 18 replaces the output of a sense amplifier 9a with the output of a sense amplifier 9b based upon the contents of secondary array 10.
Redundancy decode circuitry 18 is implemented to replace the output of one or more sense amplifiers 9a with the output of one or more sense amplifier 9b, in order to minimize the timing of a memory read operation and/or maintain the timing of a memory read operation within acceptable limits. It is understood, however, that redundancy decode circuitry 18 may be implemented between column decode circuitry 8 and sense amplifiers 9 and/or otherwise made part of column decode circuitry 8. In this alternative implementation, redundancy decode circuitry 18 selectively replaces one or more column lines 5 associated with one or more defective regular columns 16 with one or more column lines 5 associated with one or more redundant columns 4 of memory cells. The output of redundancy decode circuitry 18 would, in this case, be connected to the input of sense amplifiers 9. In either implementation, the net effect is that defective columns 16 of memory cells are replaced with a redundant column 4 of memory cells based upon the contents of secondary array 10.
Flash memory device 1 may further include a redundancy control circuit 12 for generally performing replacements of defective regular columns 16 during a memory access operation based upon the contents of secondary array 10. In particular, redundancy control circuit 12 examines each set 11 of memory cells in secondary array 10 during a memory access operation to see if a regular column 16 or group thereof is identified for replacement by a set 11. In response to the examination, redundancy control circuit 12 initiates _a replacement of one of more regular columns 16. As explained above, the replacement may be a single regular column 16 or one or more groups of columns 16 associated with a main column line 50.
In performing the examining and replacing operations, redundancy control circuit 12 and secondary array 10 may be seen as forming a content addressable memory (CAM) or otherwise performing CAM type operations.
The operation of flash memory device 1 in performing a memory read operation will be described with reference to Figure 3. Initially, flash memory device 1 is tested for defects at step 40. Any discovered defects requiring column replacement are recorded in secondary array 10 at 41. In the event a random defect is discovered, the column address and block address of the corresponding regular column line 16 are stored in sub-sets 11a and 11b, respectively, of any set 11 of storage elements in secondary array 10. In addition, a value, such as a logic one, is stored in sub-set 11c to indicate that the set 11 now obtains column replacement information. Sub-set 11d of the set 11 is set to a value, such as logic one, to indicate that an individual regular column 16 is being replaced. At this point, the set 11 is fully programmed to facilitate the selective replacement of a single regular column 16 of memory cells 20 during a memory read operation.
In the event that a cluster of defects in a block is discovered, the column address (and/or main column line 50) and block address corresponding to a regular column 16 (main column line 50) in the sector 3 are stored in sub-sets 11a and 11b, respectively, of any set 11 in secondary array 10. Sub-set 11c is loaded with a value, such as a logic one, to indicate that the set 11 now obtains column replacement information. Sub-set 11d is set to a value, such as logic zero, to indicate that at least one group of regular columns 16 is to be replaced, instead of a single column 16 of memory cells 20. If the cluster of defects primarily effect the regular columns 16 in a single block, then a value, such as a logic zero value, is stored sub-set 11e of the chosen set 11 so as to indicate that all of the regular columns 16 associated with the main column line 50 in a single block (identified by sub-set 11b) are to be replaced. At this point, the set 11 is fully programmed to facilitate the replacement of a group of regular columns 16 (and their corresponding main column line 50) in a single block during a memory read operation.
In the event that a cluster of defects are discovered that effect the ability to use any group of regular columns 16 associated with a single main column line 50, the column address corresponding to the single main column line 50 that is impacted by the defect cluster is stored in sub-sets 11a of any set 11 in secondary array 10. The column address of the impacted main column line 50, of course, may be identified by using only a portion of the storage elements in sub-set 11a. Sub-set 11c is loaded with a value, such as a logic one, to indicate that the set 11 now obtains column replacement information. Sub-set 11d is set to a value, such as logic zero, to indicate that at least one group of regular columns 16 is to be replaced, instead of a single column 16 of memory cells 20. Because the cluster of defects effect the use of columns 16 associated with a main column line 50 in more than one block, a value, such as a logic one value, is stored sub-set 11e of the chosen set 11 so as to indicate that the main column line 50 (identified in sub-set 11a) and all of the regular columns 16 associated therewith are to be replaced. At this point, the chosen set 11 is fully programmed to facilitate the replacement of all of the regular columns 16 associated with the addressed main column line 50 during a memory read operation.
It is understood that steps 40 and 41 may be performed by the manufacturer before delivery of the flash memory device 1 to a user.
A memory read operation is subsequently initiated at 42 by applying to flash memory device 1 an externally generated address and input control signals. Upon reception of these input signals, row decode circuitry 7 selects a row of memory cells 20 in memory cell array 2, and column decode circuitry 8 selects column lines 5 associated with the addressed columns 16 for connection to sense amplifiers 9a.
At around this same time, redundancy control circuit 12 examines at 44 the content of secondary array 10 to see if secondary array 10 identifies any of the addressed columns 16 as being defective. If any group 11 of memory cells in secondary array 2 has stored therein the block address and column address corresponding to an addressed column 16 as well as an indication that only the addressed column 16 is to be replaced, then redundancy control circuit 12 determines at 45 the particular redundant column 4 that is to replace the addressed, defective column 16 identified by the group 11. This determination may, for example, be based in part upon the column address corresponding to the defective column 16. Once the particular redundant column 4 is identified, redundancy control circuit 12 controls at 46 redundancy decode circuitry 18 so that the output of sense amplifiers 9a associated with addressed columns 16 that are defect-free are connected to data I/O circuit 13, together with the output of sense amplifiers 9b associated with the particular redundant column 4 identified during step 45. In other words, control circuit 10 controls redundancy decode circuitry 18 so that the particular redundant column 4 identified by secondary array 2 replaces the corresponding defective column 16 at 45. Thereafter, the output of redundancy decode circuitry 18 is available to data I/O circuit 13 for driving the external data I/O pins 14 accordingly, thereby completing the memory read operation.
On the other hand, if any group 11 of memory cells in secondary array 2 has stored therein a column address corresponding to a main column line 50 as well as an indication that a group of regular columns 16 in a block (identified by the block address stored in sub-set 11b) are to be replaced, then redundancy control circuit 12 determines at 48 the particular redundant main column line 50 and corresponding redundant columns 4 in the addressed block that are to replace the main column line 50 and associated regular columns 16 in the addressed block. This determination may, for example, be based in part upon the column address. Once the particular redundant main column line 50 and corresponding redundant columns 4 in a block are identified, redundancy control circuit 12 controls at 49 redundancy decode circuitry 18 so that the output of sense amplifiers 9a associated with addressed regular columns 16 that are defect-free are connected to data I/O circuit 13, together with the output of sense amplifiers 9b associated with the particular redundant columns 4 identified during step 48. In other words, redundancy control circuit 12 controls redundancy decode circuitry 18 so that the particular redundant columns 4 identified by secondary array 10 replaces the corresponding defective columns 16 at 49. Thereafter, the output of redundancy decode circuitry 18 is available to data I/O circuit 13 for driving the external data I/O pins 14 accordingly, thereby completing the memory read operation.
Alternatively, if any group 11 of memory cells in secondary array 2 has stored therein a block address and the column address corresponding to a main column line 50 as well as an indication that all regular columns 16 associated with the main column line 50 are to be replaced, then redundancy control circuit 12 determines at 50 the particular redundant main column line 50 and corresponding redundant columns 4 that are to replace the main column line 50 and corresponding regular columns 16 identified by the group 11. This determination may, for example, be based in part upon the column address corresponding to the main column line 50. Once the particular redundant main column lines 50 and corresponding redundant columns 4 are identified, redundancy control circuit 12 controls at 51 redundancy decode circuitry 18 so that the output of sense amplifiers 9a associated with addressed regular columns 16 that are defect-free are connected to data I/O circuit 13, together with the output of sense amplifiers 9b associated with the particular redundant column 4 identified during step 50. In other words, redundancy control circuit 12 controls redundancy decode circuitry 18 so that the particular redundant columns 4 identified by secondary array 10 replaces the corresponding defective columns 16 at 49. Thereafter, the output of redundancy decode circuitry 18 is available to data I/O circuit 13 for driving the external data I/O pins 14 accordingly, thereby completing the memory read operation.
As discussed above, a shortcoming of prior redundancy schemes for flash memories results in a relatively low repair probability and/or redundancy efficiency. Because there is no one-to-one correspondence between sets 11 of memory cells in secondary array 10 and redundant columns 4, and because each set 11 may identify for replacement any defective column 16 or group thereof, less sets 11 of memory cells are needed to repair the same number of defective columns, relative to prior flash memory devices.
Because the number of groups 11 of memory cells in secondary array 10 is not tied to the number of redundant columns 4, the flash memory device 1 may increase the repair probability without increasing the number of groups 11 in secondary array 10. For instance, if the size of the blocks are halved (i.e., the number of blocks in array 2 are doubled), the repair probability increases. The only real effect the halving of the blocks has on secondary array 2 is that each group 11 in secondary array 2 must now include an additional bit for identifying the addressed block. As a result, the repair probability of flash memory device 1 may be increased without a substantial increase in the size of secondary array 10.
In addition, flash memory device 1 advantageously allows programming and/or assigning on-the-fly (i.e., at wafer test) to each set 11 of memory cells in secondary array 10 the type of column replacement to be associated with the set 11 of memory cells.
It is understood that flash memory device 1 may be utilized in any of a number of devices requiring nonvolatile memory. For instance, flash memory device 1 may be located in an electronics system 100 (Figure 4) having a processing unit 102 that accesses data stored in flash memory device 1. System 100 may be, for example, a computer and/or data processing device, or a telecommunications device, such as a wireless telephone.
The invention being thus described, it will be obvious that the same may be embodied in many ways within the scope of the following claims.

Claims

A nonvolatile memory device, comprising:
a plurality of sectors (3) of memory cells (20) arranged relative to each other so as to form an array (2) of memory cells (20) wherein the sectors (3) are grouped into blocks (30) of memory cells (20), with each block comprising one or more sectors (3), each sector (3) comprising:
a plurality of memory cells (20) arranged into rows and columns, the columns of memory cells including addressable regular columns (16) of memory cells (20) and redundant columns (4) of memory cells (20);

a plurality of local column lines (5), each local column line (5) being coupled to a distinct column (16) of memory cells (20) in the sector (3); and the memory device further comprising:
a plurality of main column lines (50)which extend substantially from one side of the array (2) substantially to an opposed side thereof, each main column line (50.) being coupled to a plurality of local column lines (5) in the sectors (3);

address decode circuitry (7,8) for receiving an externally generated address and selecting a row, at least one of the regular columns (16) of memory cells (20) and at least one of the main column lines (50) based upon the externally generated address;

at least one set (11) of storage elements (10) capable of storing information identifying for replacement one of the regular columns (5) of memory cells and one of the main column lines (50); and

redundancy circuitry (12,18) for selectively and individually replacing the selected at least one of the regular columns (16) of memory cells (20) with at least one of the redundant columns (4) of memory cells (20), and selectively replacing the selected at least one of the main column lines (50) together with the corresponding regular columns (16) of memory cells (20) coupled thereto with a redundant main column line (50) and corresponding redundant columns (4) of memory cells coupled thereto;

characterized by
the at least one set (11) of storage elements (10) further comprising:
a bit (11e) indicating whether said redundancy circuitry (12, 18) is arranged to:
selectively and individually replace the selected one of the regular columns (16) of memory cells (20) identified by the information identifying for replacement one of the regular columns in the set of storage elements; or

selectively replace the selected one of the main column lines (50) identified by the information identifying for replacement one of the main column lines together with the corresponding regular columns (16) of memory cells (20) coupled thereto.
The nonvolatile memory device of claim 1, wherein:
the redundancy circuitry (12,18) is arranged to replace the selected one of the regular columns (16) of memory cells (20) upon an affirmative determination that the at least one set (11) of storage elements (10) identifies for replacement the selected one of the regular columns (16) of memory cells (20);

the redundancy circuitry (12,18) is arranged to replace the selected one of the regular columns (16) of memory cells (20) with the at least one redundant column (4) of memory cells. (20);

the redundancy circuitry (12,18) is arranged to replace the selected one of the main column lines (50) and the regular columns (16) of memory cells (20) coupled thereto in a block upon an affirmative determination that the at least one set (11) of storage elements (10) identified for replacement the selected one of the main column lines (50); and/or

the redundancy circuitry (12,18) is arranged to replace the selected one of the main column lines (50) and the corresponding regular columns (16) of memory cells (20) coupled thereto with the redundant main column line (50) and redundant columns (4) of memory cells (20) coupled thereto.
The nonvolatile memory device of claim 1, wherein:
the redundancy circuitry (12,18) is arranged to selectively replace the selected one of the main column lines (50) together with the corresponding regular columns (16) of memory cells (20) coupled thereto with the redundant main column line (50) together with the corresponding redundant columns (4) of memory cells (20) coupled thereto.
The nonvolatile memory device of claim 1, wherein:
the redundancy circuitry (12,18) is arranged to selectively determine the at least one redundant column (4) of memory cells (20) to replace the selected one of the regular columns (16) of memory cells (20) identified in the at least one set (11) of storage elements (10), and the redundant main column line (50) and corresponding redundant columns (4) of memory cells (20) coupled thereto to replace the selected one of the main column lines (50) identified in the at least one set (11) of storage elements (10), based upon the externally-generated address.
The nonvolatile memory device of claim 1, wherein:
the at least one set (11) of storage elements (10) is capable of further maintaining an enable bit identifying whether the at least one set (11) of storage elements (10) maintains address information corresponding to at least one regular column (16) of memory cells (20) replaced.
The nonvolatile memory device of claim 1, wherein:
the storage elements (10) in the at least one set (11) of storage elements (10) comprise nonvolatile memory cells.
A nonvolatile memory device as claimed in claim 1, wherein:
the redundancy circuitry (12, 18) is arranged for selectively replacing the identified one of the main column lines (50) and regular columns (16) coupled thereto in a single block and for selectively replacing the one of the main column lines (50) and regular columns (16) of memory cells (20) coupled thereto in the plurality of blocks based upon the information stored in the at least one set (11) of storage elements (10).
The nonvolatile memory device of claim 7, wherein:
one or more storage elements (10) in the at least one set (11) of storage elements (10) is arranged to store a value (11d) indicative of whether the identified main column line (50) and the regular columns (16) of memory cells (20) coupled thereto in the single block are to be replaced, or the identified main column line (50) and the regular columns (16) of memory cells (20) coupled thereto in the plurality of the blocks are to be replaced; and

the redundancy circuitry is arranged to perform the selective replacement based upon the value (11d) maintained in the one or more storage elements (10).
The nonvolatile memory device of claim 7, wherein:
the at least one set (11) of storage elements (10) is arranged to maintain an address associated with the identified one of the main column lines (50), the maintained address serving to identify the identified one of the main.column lines (50).
The nonvolatile memory device of claim 7, wherein:
the at least one set (11) of storage elements (10) is arranged to maintain a column address of the selected regular column (16) of memory cells (20); the redundancy circuitry (12,18) is arranged to perform the selective replacement based upon the column address maintained in the one storage element and the bit (11e) indicating whether the indicated regular column (5) of memory cells is to be selectively and individually replaced or the main column line (50) coupled to the indicated regular column (16) of memory cells is to be replaced together with the regular columns (16) coupled thereto.
An electronics device, comprising:
a processing unit; and

a nonvolatile memory device as claimed in claim 1.
A method of performing a memory read operation on a nonvolatile memory device comprising: an array (2) of memory cells (20) arranged into rows and columns (16), the columns of the memory cells including addressable regular columns (16) of memory cells (20) and redundant columns (4) of memory cells (20), each regular column (16) of memory cells (20) being connected to a local column line (5), wherein the memory device array is partitioned into sectors (3) with multiple sectors (3) being grouped into one or more blocks (30), a plurality of main column lines (50) extending substantially from one side of the array (2) substantially to an opposed side thereof, each main column line (50) being coupled to a plurality of local column lines (5) and at least one set (11) of storage elements (10) , the method comprising:
receiving an address corresponding to a row and.at least one regular column (16) of memory cells (20);

selecting the row of memory cells, the at least one regular column (16) of memory cells and at least one main column line (50) corresponding to the received address;

searching the at least one set (11) of storage elements (10) and determining whether the at least one set (11) of storage elements (10) identifies for replacement the selected at least one regular column (16) of memory cells (20) and the selected at least one main column line (50); and characterized by the least one set (11) of storage elements (10) further comprising a bit (11e) wherein

based upon the searching and the bit (11e) value, selectively and individually replacing the selected at least one of the regular columns (16) of memory cells (20) with at least one of the redundant columns (4) of memory cells (20) identified by the set (11) of storage elements (10) or replacing the selected at least one of the main column lines (50) and corresponding regular columns (16) of memory cells (20) coupled thereto, with a redundant main column line (50) identified by the set (11) of storage elements (10) and corresponding redundant columns (4) of memory cells (20) coupled thereto.
The method of claim 12, further comprising:
initially identifying one or more defects in the memory device and storing in the at least one set (11) of storage elements (10) an address corresponding to the one or more defects and a bit (11e) value indicating whether a single regular column (16) of memory cells (20) or the main column line (50) and the regular columns (16) of memory cells (20) associated with the main column line (50) is to be replaced.
The method of claim 12, further comprising:
upon the step of searching the at least one set (11) of storage elements (10) and identifying the selected main column line (50) and regular columns (16) of memory cells (20) coupled thereto for replacement, determining whether the regular columns (16) of memory cells (20) coupled to the identified main column line (50) are regular columns (5) in a single block (30) or a plurality of blocks (30); and

the step of replacing comprises selectively replacing the selected main column line (50) and regular columns (16) of memory cells (20) coupled thereto in the plurality of blocks based upon the determining.
The method of claim 12, further comprising:
upon the step of searching the at least one set (11) of storage elements (10) and identifying the selected main column line (50) and regular columns (16) of memory cells (20) coupled thereto to be replaced, determining whether the regular columns (16) of memory cells (20) coupled to the identified main column line (50) are regular columns (16) of memory cells (20) in a single block or a plurality of blocks; and

the step of replacing comprises replacing the main column line (50) and regular columns (16) of memory cells (20) that are coupled thereto in a single block based upon the determining.
The method of claim 12, further comprising:
upon the searching the at least one set (11) of storage elements (10) and identifying to be replaced the selected main column line (50) and regular columns (16) of memory cells (20) coupled thereto, identifying a main column line (50) and redundant columns (4) of memory cells (20) coupled thereto to replace the identified main column line (50) and regular columns (16) of memory cells (20) coupled thereto, based upon the searching.