EP1269308A2 - Multiplier architecture in a general purpose processor optimized for efficient multi-input addition - Google Patents
Multiplier architecture in a general purpose processor optimized for efficient multi-input additionInfo
- Publication number
- EP1269308A2 EP1269308A2 EP01923028A EP01923028A EP1269308A2 EP 1269308 A2 EP1269308 A2 EP 1269308A2 EP 01923028 A EP01923028 A EP 01923028A EP 01923028 A EP01923028 A EP 01923028A EP 1269308 A2 EP1269308 A2 EP 1269308A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- operands
- bit
- alus
- sum
- multiplier array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3812—Devices capable of handling different types of numbers
- G06F2207/382—Reconfigurable for different fixed word lengths
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
In one embodiment, a dual mode execution unit is described for use in a general purpose digital signal processor (DSP). The execution unit can operate as a 16X16 multiplier in one mode and an 8-bit adder tree in another mode. The adder tree structure is constructed by reutilizing pre-existing arithmetic logic units (ALUs) in the multiplier array of the multiplier architecture. The 8-bit adder tree mode is particularly useful for performing various computation intensive algorithms used in digital video processing, such as motion search and spatial interpolation algorithms.
Claims
1. An apparatus comprising: a decoder to decode an instruction specifying an adder-tree operation; a circuit coupled to the decoder and comprising: a multiplier array comprising a plurality of arithmetic logic units; and a selection circuit to select first and second operands from a 2n-bit word, wherein said first and second operands have fewer bits than 2n, and said selection circuit is adapted to add said first and second operands in a selected one of said ALUs in the multiplier array to produce a first sum.
2. The apparatus according to claim 1 wherein said first and second operands are n-bit words.
3. The apparatus according to claim 1 wherein n is
- 13 -
4. The apparatus according to claim 1 wherein said selection circuit is adapted to operate in response to said instruction to, select a third operand and a fourth operand from a second 2n-bit word, wherein said first and second operands have fewer bits than 2n, and add said third and fourth n-bit operands in a second selected one of said ALUs to produce a second sum.
5. The apparatus of claim 4 wherein said third and fourth operands are n-bit words .
6. The apparatus of claim 4 wherein said selection circuit is adapted to operate in response to said instruction to add said first sum and said second sum in a third selected one of said ALUs to produce a third sum.
7. The apparatus of claim 1 wherein said selection circuit is adapted to operate in response to an instruction specifying a multiplier mode to select first and second 2n-bit multiplicands, and multiply said first and second 2n-bit multiplicands to produce a 4n-bit product.
- 14
8. The apparatus according to claim 1 wherein the operand selector includes a multiplexer.
9. A video processor comprising: a central processing unit (CPU) ; a memory to store instructions to perform video encoding operations; a digital signal processor coupled to said CPU and said memory and including an execution unit comprising: a decoder to decode an instruction specifying an adder-tree operation; and a first circuit coupled to the decoder, and comprising a multiplier array comprising a plurality of arithmetic logic units (ALUs) , said first circuit including an element that, in response to said instructions, selects first and second n-bit operands from a 2n-bit word, and adds said first and second n-bit operands in a selected one of the ALUs in the multiplier array to produce a first sum.
10. The video processor of claim 9 wherein n equals
- 15
11. The video processor of claim 9 wherein said first circuit operates in response to an instruction specifying a multiplier mode to select first and second 2n-bit multiplicands, and multiply said two 2n-bit multiplicands to produce a product.
12. The video processor of claim 9 further comprising: a first multiplicand selector to select said first multiplicand from at least one first 2n-bit word; a second multiplicand selector to select said second multiplicand from at least one second 2n-bit word; a partial product generator to produce a plurality of partial sums from said first and second 2n-bit multiplicands; and an adder to add two 4n-bit words produced in the multiplier array by reducing said partial products.
13. The video processor of claim 9 wherein the instructions to perform video encoding operations conform to MPEG standards.
16 -
14. The video processor of claim 9 wherein the instructions to perform video encoding operations comprise instructions to perform motion search algorithms.
15. The video processor of claim 9 wherein the instructions to perform video encoding operations comprise instructions to perform spatial interpolation algorithms.
16. A method comprising: adding a plurality of operands in a multiplier array comprising a plurality of ALUs; selecting an adder-tree mode; selecting first and second operands from a 2n-bit word; adding said two first and second operands in a first one of the ALUs in the multiplier array; and outputting a sum from the multiplier array.
17. The method of claim 16 wherein said first and second operands have less than 2n bits.
- 17 -
18. The method of claim 16 further comprising: selecting third and fourth operands from a second 2n-bit word, said third and fourth operands having les than 2n bits; adding said third and fourth words in a second one of the ALUs in the multiplier array; adding a first sum from said first ALU and a second sum from said second ALU in a third ALU in the multiplier array.
19. The method of claim 18 wherein said third and fourth operands are n-bit words.
20. The method of claim 16 further comprising: selecting a multiplier mode; selecting a first 2n-bit multiplicand from at least one -first 2n-bit word; selecting a second 2n-bit multiplicand from at least one second 2n-bit word; multiplying said first and second multiplicands to produce a product.
21. The method of claim 16 wherein n is 8.
- IE
22. The method of claim 16 further comprising: performing a motion search algorithm in the adder-tree mode.
23. The method of claim 16 further comprising: performing a spatial interpolation algorithm in the adder-tree mode.
24. The method of claim 16 further comprising: performing a spatial low-pass filtering algorithm in the adder-tree mode.
25. A program storage device readable by a machine, comprising instructions that cause the machine to: add a plurality of operands in a multiplier array comprising a plurality of ALUs; select an adder-tree mode; select first and second operands from a 2n-bit word; add said first and second operands in a first one of the ALUs in the multiplier array; and output a sum from the multiplier array.
19 -
26. The program storage device of claim 25 wherein said first and second operands are n-bit words.
- 20 -
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US53992200A | 2000-03-31 | 2000-03-31 | |
| US539922 | 2000-03-31 | ||
| PCT/US2001/010603 WO2001075587A2 (en) | 2000-03-31 | 2001-04-02 | Multiplier architecture in a general purpose processor optimized for efficient multi-input addition |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1269308A2 true EP1269308A2 (en) | 2003-01-02 |
Family
ID=24153209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP01923028A Withdrawn EP1269308A2 (en) | 2000-03-31 | 2001-04-02 | Multiplier architecture in a general purpose processor optimized for efficient multi-input addition |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1269308A2 (en) |
| CN (1) | CN1422402A (en) |
| AU (1) | AU2001249767A1 (en) |
| TW (1) | TW539989B (en) |
| WO (1) | WO2001075587A2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008524691A (en) * | 2004-12-17 | 2008-07-10 | エヌエックスピー ビー ヴィ | Arithmetic / logical tree computation |
| US7546331B2 (en) * | 2005-03-17 | 2009-06-09 | Qualcomm Incorporated | Low power array multiplier |
| US8713286B2 (en) | 2005-04-26 | 2014-04-29 | Qualcomm Incorporated | Register files for a digital signal processor operating in an interleaved multi-threaded environment |
| CN101320321B (en) * | 2008-06-27 | 2010-06-02 | 北京大学深圳研究生院 | An Array Arithmetic Logic Unit Structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4839845A (en) * | 1986-03-31 | 1989-06-13 | Unisys Corporation | Method and apparatus for performing a vector reduction |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06242928A (en) * | 1993-02-22 | 1994-09-02 | Nec Corp | Adder and multiplying circuit using the same |
| US5974435A (en) * | 1997-08-28 | 1999-10-26 | Malleable Technologies, Inc. | Reconfigurable arithmetic datapath |
-
2001
- 2001-03-30 TW TW90107607A patent/TW539989B/en not_active IP Right Cessation
- 2001-04-02 WO PCT/US2001/010603 patent/WO2001075587A2/en not_active Ceased
- 2001-04-02 EP EP01923028A patent/EP1269308A2/en not_active Withdrawn
- 2001-04-02 AU AU2001249767A patent/AU2001249767A1/en not_active Abandoned
- 2001-04-02 CN CN 01807694 patent/CN1422402A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4839845A (en) * | 1986-03-31 | 1989-06-13 | Unisys Corporation | Method and apparatus for performing a vector reduction |
Non-Patent Citations (1)
| Title |
|---|
| See also references of WO0175587A3 * |
Also Published As
| Publication number | Publication date |
|---|---|
| AU2001249767A1 (en) | 2001-10-15 |
| WO2001075587A2 (en) | 2001-10-11 |
| WO2001075587A3 (en) | 2002-01-24 |
| CN1422402A (en) | 2003-06-04 |
| TW539989B (en) | 2003-07-01 |
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