EP1262094A1 - Method for producing bond pads on a printed circuit - Google Patents
Method for producing bond pads on a printed circuitInfo
- Publication number
- EP1262094A1 EP1262094A1 EP01989644A EP01989644A EP1262094A1 EP 1262094 A1 EP1262094 A1 EP 1262094A1 EP 01989644 A EP01989644 A EP 01989644A EP 01989644 A EP01989644 A EP 01989644A EP 1262094 A1 EP1262094 A1 EP 1262094A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- depositing
- resin
- chromium
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05016—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05016—Shape in side view
- H01L2224/05018—Shape in side view being a conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/05576—Plural external layers being mutually engaged together, e.g. through inserts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05671—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2081—Compound repelling a metal, e.g. solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0361—Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/0542—Continuous temporary metal layer over metal pattern
Definitions
- the invention relates to a method for producing connection pads and in particular connection pads on a printed circuit or an integrated circuit.
- connection pads of very small dimensions, for example with a diameter of 200 ⁇ or even less and with a thickness of 100 microns or even also less.
- these connection pads must be of relatively homogeneous constitution with few defects and this over the entire circuit.
- the delimitation on the surface of the circuit of the dimensions of a connection pad is commonly made by a layer of insulating material.
- This insulating layer has a non-negligible thickness, which means that the height of the connection pad is either relatively large or very little greater than the thickness of the insulating layer.
- the geometry of the stud is of poor quality. The invention aims to remedy these drawbacks.
- the invention therefore relates to a method for producing connection pads on a circuit comprising at least one conductive track, characterized in that it comprises the following steps: a) depositing a thin layer of copper and a layer of chromium on the surface of the entire circuit; b) depositing a layer of resin and removing this resin at the places of the pads to be produced and also at the places where there is no conductive track; c) removal of the chromium layer at the places left free by the resin; d) removal of the resin; e) depositing a photosensitive film and making in this film of openings at the places where it is desired to make connection pads; f) depositing a connection material in said openings; g) removal of the photosensitive film; h) removal of the copper layer in areas of the circuit not covered by the chromium layer or by the connection material; i) heating the assembly so as to reach the melting temperature of the connection material.
- a thin layer of copper 3 is produced then a thin layer of chromium 4 of a few microns or even a few tenths of a micron.
- Figure 2a shows by way of example, a top view of the device of Figure 1a. It can therefore be seen in FIG. 2a that, by way of example, the substrate 1 carries a conductor and an enlarged part corresponding to a connection pad.
- the deposition of a photosensitive resin 5 is carried out.
- a third step represented in FIG.
- any process known in the art is removed, the resin 5 located at the locations of the connection pads to be produced and also where there is no conductive track.
- Figure 2b shows the device at this stage of the process.
- the chromium is removed from the areas not protected by the resin 5 by any process and in particular by a chemical attack process.
- the resin layer 5 is removed.
- a photosensitive film 6 is deposited and in this layer of photosensitive material 6, creates openings corresponding to the surface of the connection pads to be produced.
- a copper overload 7 (5 to 10 ⁇ m) is produced in the openings thus obtained on the thin copper layer 3 (FIG. 1g).
- a conductive material such as retain-lead (SnPb) is deposited, this deposit will make it possible to produce a connection pad 8.
- the photosensitive film 6 is removed (FIG. 1i).
- the copper is removed from the surface of the circuit in all the areas not protected by the chromium layer 4 and the conductive material 8 (FIG. 1j).
- the whole is heated so as to reach the melting point of the tin-lead mixture 8 so that the tin-lead mixture is put under the form of an almost spherical block, the surface of this block being clearly delimited by the layer of chromium 4 situated around the tin-lead mixture.
Abstract
The invention concerns a method for producing a chromium coating (4) so that the material of the bond pad (8) remains in a zone totally limited by the chromium coating (4). The invention is applicable to bond pads for electronic components.
Description
PROCEDE DE REALISATION DE PLOTS DE CONNEXION SUR UN METHOD FOR MAKING CONNECTION PLOTS ON A
CIRCUIT IMPRIMEPRINTED CIRCUIT BOARD
L'invention concerne un procédé de réalisation de plots de connexion et notamment de plots de connexion sur un circuit imprimé ou un circuit intégré.The invention relates to a method for producing connection pads and in particular connection pads on a printed circuit or an integrated circuit.
L'invention est applicable notamment dans la réalisation de plots de connexion de très petites dimensions par exemple de diamètre de 200 μ voire moins et d'épaisseur 100 microns voire également moins. De plus, ces plots de connexion doivent être de constitution relativement homogène avec peu de défauts et cela sur l'ensemble du circuit.The invention is applicable in particular in the production of connection pads of very small dimensions, for example with a diameter of 200 μ or even less and with a thickness of 100 microns or even also less. In addition, these connection pads must be of relatively homogeneous constitution with few defects and this over the entire circuit.
Par ailleurs, dans les techniques connues la délimitation à la surface du circuit des dimensions d'un plot de connexion est faite couramment par une couche de matériau isolant. Cette couche d'isolant a une épaisseur non négligeable, ce qui fait que la hauteur du plot de connexion est soit relativement importante soit très peu supérieure à l'épaisseur de la couche d'isolant. De plus, la géométrie du plot est de qualité médiocre. L'invention vise à remédier à ces inconvénients.Furthermore, in known techniques, the delimitation on the surface of the circuit of the dimensions of a connection pad is commonly made by a layer of insulating material. This insulating layer has a non-negligible thickness, which means that the height of the connection pad is either relatively large or very little greater than the thickness of the insulating layer. In addition, the geometry of the stud is of poor quality. The invention aims to remedy these drawbacks.
L'invention concerne donc un procédé de réalisation de plots de connexion sur un circuit comportant au moins une piste conductrice, caractérisé en ce qu'il comporte les étapes suivantes : a) dépôt d'une fine couche de cuivre et d'une couche de chrome sur la surface de l'ensemble du circuit ; b) dépôt d'une couche de résine et enlèvement de cette résine aux endroits des plots à réaliser et également aux endroits où il n'y a pas de piste conductrice ; c) enlèvement de la couche de chrome aux endroits laissés libres par la résine ; d) retrait de la résine ; e) dépôt d'un film photosensible et réalisation dans ce film d'ouvertures aux endroits où l'on désire réaliser des plots de connexion ; f) dépôt d'un matériau de connexion dans lesdites ouvertures ; g) retrait du film photosensible ;
h) retrait de la couche de cuivre dans les endroits du circuit non recouverts par la couche de chrome ou par le matériau de connexion ; i) chauffage de l'ensemble de façon à atteindre la température de fusion du matériau de connexion.The invention therefore relates to a method for producing connection pads on a circuit comprising at least one conductive track, characterized in that it comprises the following steps: a) depositing a thin layer of copper and a layer of chromium on the surface of the entire circuit; b) depositing a layer of resin and removing this resin at the places of the pads to be produced and also at the places where there is no conductive track; c) removal of the chromium layer at the places left free by the resin; d) removal of the resin; e) depositing a photosensitive film and making in this film of openings at the places where it is desired to make connection pads; f) depositing a connection material in said openings; g) removal of the photosensitive film; h) removal of the copper layer in areas of the circuit not covered by the chromium layer or by the connection material; i) heating the assembly so as to reach the melting temperature of the connection material.
Les différents objets et caractéristiques de l'invention vont maintenant être décrits en se reportant à la description qui va suivre faite à titre d'exemple et des figures annexées qui représentent :The various objects and characteristics of the invention will now be described with reference to the description which follows, given by way of example and of the appended figures which represent:
- les figures 1a à 1k, un exemple du procédé de réalisation selon l'invention montrant par des vues en coupe du dispositif réalisé, les différentes étapes du procédé ;- Figures 1a to 1k, an example of the production method according to the invention showing in sectional views of the device produced, the different stages of the process;
- les figures 2a et 2b, un dispositif en vue du dessus à différentes étapes du procédé selon l'invention.- Figures 2a and 2b, a device seen from above at different stages of the method according to the invention.
On va donc décrire maintenant un procédé de réalisation selon l'invention.We will therefore now describe an embodiment method according to the invention.
Au cours d'une première étape, sur un substrat 1 portant au moins une piste conductrice ou un plot conducteur 2, on réalise une fine couche de cuivre 3 puis une fine couche de chrome 4 de quelques microns voire quelques dixièmes de microns. La figure 2a représente à titre d'exemple, une vue du dessus du dispositif de la figure 1a. On voit donc sur la figure 2a, qu'à titre d'exemple, le substrat 1 porte un conducteur et une partie élargie correspondant à un plot de connexion. Au cours d'une deuxième étape, telle que représentée en figure 1b, on réalise le dépôt d'une résine photosensible 5. Au cours d'une troisième étape, représentée en figure 1c, on enlève par tout procédé connu dans la technique, la résine 5 située aux endroits des plots de connexion à réaliser et également là où il n'y a pas de piste conductrice. La figure 2b représente le dispositif à ce stade du procédé. Au cours d'une quatrième étape, tel que cela est représenté en figure 1d, on procède à l'enlèvement du chrome dans les zones non protégées par la résine 5 par tout procédé et notamment par un procédé d'attaque chimique. Au cours d'une cinquième étape, telle que représenté en figure 1e, on enlève la couche de résine 5.During a first step, on a substrate 1 carrying at least one conductive track or a conductive pad 2, a thin layer of copper 3 is produced then a thin layer of chromium 4 of a few microns or even a few tenths of a micron. Figure 2a shows by way of example, a top view of the device of Figure 1a. It can therefore be seen in FIG. 2a that, by way of example, the substrate 1 carries a conductor and an enlarged part corresponding to a connection pad. During a second step, as shown in FIG. 1b, the deposition of a photosensitive resin 5 is carried out. During a third step, represented in FIG. 1c, any process known in the art is removed, the resin 5 located at the locations of the connection pads to be produced and also where there is no conductive track. Figure 2b shows the device at this stage of the process. During a fourth step, as shown in FIG. 1d, the chromium is removed from the areas not protected by the resin 5 by any process and in particular by a chemical attack process. During a fifth step, as shown in FIG. 1e, the resin layer 5 is removed.
Au cours d'une sixième étape (figure 1f), on réalise le dépôt d'un film photosensible 6 et dans cette couche de matériau photosensible 6, on
réalise des ouvertures correspondant à la surface des plots de connexion à réaliser.During a sixth step (FIG. 1f), a photosensitive film 6 is deposited and in this layer of photosensitive material 6, creates openings corresponding to the surface of the connection pads to be produced.
Ensuite, au cours d'une septième étape, on réalise dans les ouvertures ainsi obtenues une surcharge en cuivre 7 (5 à 10 μm) sur la fine couche de cuivre 3 (figure 1g).Then, during a seventh step, a copper overload 7 (5 to 10 μm) is produced in the openings thus obtained on the thin copper layer 3 (FIG. 1g).
Puis, au cours d'une huitième étape représentée en la figure 1h, on procède à un dépôt de matériau conducteur tel que de rétain-plomb (SnPb), ce dépôt permettra de réaliser un plot de connexion 8.Then, during an eighth step shown in FIG. 1h, a conductive material such as retain-lead (SnPb) is deposited, this deposit will make it possible to produce a connection pad 8.
Au cours d'une neuvième étape, on retire le film de photosensible 6 (figure 1i).During a ninth step, the photosensitive film 6 is removed (FIG. 1i).
Puis au cours d'une dixième étape, on retire le cuivre à la surface du circuit dans toutes les zones non protégées par la couche de chrome 4 et le matériau conducteur 8 (figure 1j).Then during a tenth step, the copper is removed from the surface of the circuit in all the areas not protected by the chromium layer 4 and the conductive material 8 (FIG. 1j).
Enfin, au cours d'une onzième étape, on procède à un chauffage de l'ensemble de façon à atteindre le point de fusion du mélange d'étain- plomb 8 de telle façon que le mélange d'étain-plomb se mette sous la forme d'un plot quasiment sphérique, la surface de ce plot étant nettement délimitée par la couche de chrome 4 située autour du mélange d'étain-plomb.
Finally, during an eleventh step, the whole is heated so as to reach the melting point of the tin-lead mixture 8 so that the tin-lead mixture is put under the form of an almost spherical block, the surface of this block being clearly delimited by the layer of chromium 4 situated around the tin-lead mixture.
Claims
1. Procédé de réalisation de plots de connexion sur un circuit comportant au moins une piste conductrice, caractérisé en ce qu'il comporte les étapes suivantes : a) dépôt d'une fine couche de cuivre (3) et d'une couche de chrome (4) sur la surface de l'ensemble du circuit ; b) dépôt d'une couche de résine (5) et enlèvement de cette résine aux endroits des plots à réaliser et également aux endroits où il n'y a pas de piste conductrice ; c) enlèvement de la couche de chrome aux endroits laissés libres par la résine (5) ; d) enlèvement de la résine (5) ; e) dépôt d'un film photosensible (6) et réalisation dans ce film d'ouvertures aux endroits où l'on désire réaliser des plots de connexion ; f) dépôt d'un matériau de connexion (8) dans lesdites ouvertures ; g) retrait du film photosensible (6) ; h) retrait de la couche de cuivre dans les endroits du circuit non recouverts par la couche de chrome ou par le matériau de connexion (8) ; i) chauffage de l'ensemble de façon à atteindre la température de fusion du matériau de connexion.1. Method for producing connection pads on a circuit comprising at least one conductive track, characterized in that it comprises the following steps: a) depositing a thin layer of copper (3) and a layer of chromium (4) on the surface of the entire circuit; b) depositing a layer of resin (5) and removing this resin at the locations of the pads to be produced and also at the locations where there is no conductive track; c) removing the chromium layer at the places left free by the resin (5); d) removing the resin (5); e) depositing a photosensitive film (6) and making in this film openings at the locations where it is desired to make connection pads; f) depositing a connection material (8) in said openings; g) removal of the photosensitive film (6); h) removal of the copper layer in areas of the circuit not covered by the chromium layer or by the connection material (8); i) heating the assembly so as to reach the melting temperature of the connection material.
2. Procédé selon la revendication 1 , caractérisé en ce que le matériau de connexion est de l'étain-plomb. 2. Method according to claim 1, characterized in that the connection material is tin-lead.
3. Procédé selon la revendication 1 , caractérisé en ce qu'il prévoit entre les étapes (d) et (e), une étape de dépôt d'une couche de cuivre (7) dans les ouvertures réalisées dans le film (6) de l'étape (e). 3. Method according to claim 1, characterized in that it provides between steps (d) and (e), a step of depositing a layer of copper (7) in the openings made in the film (6) of step (e).
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0017230 | 2000-12-28 | ||
FR0017230A FR2819143B1 (en) | 2000-12-28 | 2000-12-28 | METHOD FOR MAKING CONNECTION PLOTS ON A PRINTED CIRCUIT |
PCT/FR2001/004117 WO2002054842A1 (en) | 2000-12-28 | 2001-12-20 | Method for producing bond pads on a printed circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1262094A1 true EP1262094A1 (en) | 2002-12-04 |
Family
ID=8858350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01989644A Withdrawn EP1262094A1 (en) | 2000-12-28 | 2001-12-20 | Method for producing bond pads on a printed circuit |
Country Status (6)
Country | Link |
---|---|
US (1) | US20030013045A1 (en) |
EP (1) | EP1262094A1 (en) |
JP (1) | JP2004517500A (en) |
KR (1) | KR20020089367A (en) |
FR (1) | FR2819143B1 (en) |
WO (1) | WO2002054842A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8901736B2 (en) * | 2010-05-28 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strength of micro-bump joints |
CN107709505B (en) * | 2015-05-27 | 2020-04-28 | Agc株式会社 | Water-and oil-repellent agent composition, method for producing same, and article |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5024734A (en) * | 1989-12-27 | 1991-06-18 | Westinghouse Electric Corp. | Solder pad/circuit trace interface and a method for generating the same |
FR2666173A1 (en) * | 1990-08-21 | 1992-02-28 | Thomson Csf | HYBRID INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUITS AND MANUFACTURING METHOD. |
US5376584A (en) * | 1992-12-31 | 1994-12-27 | International Business Machines Corporation | Process of making pad structure for solder ball limiting metallurgy having reduced edge stress |
FR2701602B1 (en) * | 1993-02-12 | 1995-03-31 | Thomson Csf | Thermal detector comprising a thermal insulator made of expanded polymer. |
US5480835A (en) * | 1993-05-06 | 1996-01-02 | Motorola, Inc. | Electrical interconnect and method for forming the same |
JPH0845941A (en) * | 1994-08-03 | 1996-02-16 | Oki Electric Ind Co Ltd | Forming method of semiconductor device bump |
US5800726A (en) * | 1995-07-26 | 1998-09-01 | International Business Machines Corporation | Selective chemical etching in microelectronics fabrication |
FR2740933B1 (en) * | 1995-11-03 | 1997-11-28 | Thomson Csf | ACOUSTIC PROBE AND METHOD FOR PRODUCING THE SAME |
FR2745973B1 (en) * | 1996-03-08 | 1998-04-03 | Thomson Csf | MASS MEMORY AND METHOD FOR MANUFACTURING MASS MEMORY |
JP3352352B2 (en) * | 1997-03-31 | 2002-12-03 | 新光電気工業株式会社 | Plating apparatus, plating method and bump forming method |
US6293457B1 (en) * | 2000-06-08 | 2001-09-25 | International Business Machines Corporation | Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization |
US6586322B1 (en) * | 2001-12-21 | 2003-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of making a bump on a substrate using multiple photoresist layers |
US6696356B2 (en) * | 2001-12-31 | 2004-02-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of making a bump on a substrate without ribbon residue |
-
2000
- 2000-12-28 FR FR0017230A patent/FR2819143B1/en not_active Expired - Fee Related
-
2001
- 2001-12-20 EP EP01989644A patent/EP1262094A1/en not_active Withdrawn
- 2001-12-20 JP JP2002555597A patent/JP2004517500A/en not_active Withdrawn
- 2001-12-20 WO PCT/FR2001/004117 patent/WO2002054842A1/en not_active Application Discontinuation
- 2001-12-20 KR KR1020027011250A patent/KR20020089367A/en not_active Application Discontinuation
- 2001-12-20 US US10/204,561 patent/US20030013045A1/en not_active Abandoned
Non-Patent Citations (1)
Title |
---|
See references of WO02054842A1 * |
Also Published As
Publication number | Publication date |
---|---|
KR20020089367A (en) | 2002-11-29 |
US20030013045A1 (en) | 2003-01-16 |
FR2819143A1 (en) | 2002-07-05 |
FR2819143B1 (en) | 2003-03-07 |
JP2004517500A (en) | 2004-06-10 |
WO2002054842A1 (en) | 2002-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6136668A (en) | Method of dicing semiconductor wafer | |
US5747222A (en) | Multi-layered circuit substrate and manufacturing method thereof | |
WO1985002060A1 (en) | Method for substituting an electronic component connected to the conductor tracks of a carrier substrate | |
FR2727569A1 (en) | Solder connection of electronic device substrates | |
FR2567709A1 (en) | GLITTER ASSEMBLY COMPRISING A MULTI-LAYER WIRING SUBSTRATE | |
DE69632969D1 (en) | Solder bump manufacturing process and structures with a titanium barrier layer | |
US5455461A (en) | Semiconductor device having reformed pad | |
FR2915573A1 (en) | METHOD FOR PRODUCING A MATRIX FOR DETECTING ELECTROMAGNETIC RADIATION AND IN PARTICULAR INFRARED RADIATION | |
EP1262094A1 (en) | Method for producing bond pads on a printed circuit | |
US5283206A (en) | Method of removing germanium particles precipitated in an aluminum/germanium alloy film | |
FR2760850A1 (en) | METHOD FOR MANUFACTURING INTEGRATED OPTICAL CIRCUITS FOR MINIMIZING OPTICAL COUPLING LOSSES | |
FR2528657A1 (en) | ELECTRICAL ASSEMBLY COMPRISING A CONDUCTOR PATTERN RELATING TO A NON-METALLIC SUBSTRATE AND METHOD OF MANUFACTURING THE SAME | |
JP3078489B2 (en) | Soldering method and equipment manufactured from the method | |
FR2785449A1 (en) | SUBSTRATE ASSEMBLY SYSTEM WITH CAVITY HANGING AREAS | |
EP0034530A1 (en) | Method of mounting electronic components on a printed-circuit board, and product obtained by this method | |
EP0486392B1 (en) | Hybrid circuit formed by two circuits whose tracks are joined by electrical connection balls | |
US6074728A (en) | Multi-layered circuit substrate | |
EP0614215B1 (en) | Process for forming a metal contact on a relief of a semicondactor substrate, including a step of flowing a photosensitive resin layer | |
FR2473834A1 (en) | Soldering micro-components onto printed circuits - using liq. heated to above solder m.pt. to heat substrate | |
EP0858252A1 (en) | Double resist process for manufacturing printed circuits | |
FR2722916A1 (en) | Connection element comprising solder-coated core | |
EP1350418A1 (en) | Method for producing interconnection in a multilayer printed circuits | |
EP0895627B1 (en) | Electronic assembly comprising an electronic unit connected to a coil | |
WO2019170987A1 (en) | Method for producing a soulder bump on a substrate surface | |
WO2002052633A2 (en) | Assembly for mounting an integrated circuit on a support |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20020904 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
RBV | Designated contracting states (corrected) |
Designated state(s): DE FI GB SE |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20050701 |