EP1261905B1 - Method for synchronizing computer clocks in networks used for information transmission, device for carrying out said method and data packet suitable for the synchronization of computer clocks - Google Patents

Abstract

The invention relates to a method for synchronizing computer clocks in networks used for the transmission of information according to which information is dispatched with a time stamp when being dispatched and which is re-transmitted with a time stamp in a confirmation of receipt. The time stamps are inserted in the outgoing or arriving data packet by a clock module (8) mounted downstream of a network controller (4, 10) once said network controller has authorized transmission. A CPU (2) generates actuator signals that are provided with an identifier and that correct the clock modules (8) on the basis of a comparison between the time stamps in a confirmation of receipt of the addressee of the information and the time stamp of the corresponding transmitted information.

Description

The invention relates to a method for synchronizing computer clocks in networks for the transmission of information, in which information is sent on their dispatch with a time stamp and returned with a time stamp in an acknowledgment, a device for synchronizing computer clocks in networks for information transmission, at which timestamps the information at the time of transmission and timestamps at the time of arrival at the destination address, and a data packet for synchronizing computer clocks in networked information transmission networks.

Computers require for their operation in addition to a central processor (CPU) and a memory and interfaces to the outside world, which can be designed differently. Immediately connected to the computer is a system bus, which is usually designed as a parallel interface, so that a plurality of bits can be read in and out simultaneously depending on the processor clock or the bus clock. If information is to be transmitted via lines, this can in principle also take place via parallel interfaces, wherein the maximum line length is limited due to the high borrowing effort. For the remote transmission of information or data, therefore, transmission methods have been developed in which the initially present in parallel signals have been converted into serial signals, so that they can be transmitted and received in the sequence over a smaller number of lines. For this purpose, computers usually have network cards which are connected to the respective system bus, in which case standardized parallel interfaces have been proposed.

An example of such a standardized interface is the so-called PCI bus. With such a bus, a network controller or a network card is connected in the sequence, which also contains a further interface in addition to the network controller, which is adapted to the selected transmission medium or the selected network structure. This media-specific interface or interface takes over u.a. the adjustment of the level to the downstream line network, with bus networks are very common. In bus networks, all computers are connected to a common bus, each participant can access the bus and reach each participant connected there. In order to regulate access to such bus structures, for example, the CSMA method is used (Carrier Sense Multiple Access). This method attempts to prevent collisions caused by concurrent shipments. If two subscribers simultaneously detect and transmit a free line network, such collisions would occur. This is prevented by the stations listening to the transmission media before the start of transmission, for which purpose bit structures are used with which collision detection is possible. Such bit structures are referred to as CSMA / CD packets, where CD stands for "Collision Detection" or collision detection. In addition to bus networks, star networks, ring networks and token ring networks are common and different transmission protocols are used with which a more or less large maximum transmission speed is achieved. Such transmission protocols have become known, for example, as an Ethernet protocol (IEEE 803) or as a Firewire protocol (IEEE 1394). The same applies, for example, to CAN, FDDI, ATM or Gigabit Ethernet protocols.

The network controller together with the media-specific interface for the translation of the parallel data streams into a serial data stream, wherein the desired conventions or protocols are complied with in order to avoid collisions. Network cards usually include one Memory to retain information as long as a data line is busy or the data packet is incomplete or in an unsuitable form for the protocol. This stored information is then fed into the network when a free line is detected. Due to this temporary storage until the release of the transmission, data packets are subject to different delays due to the network card. This also applies to so-called switches, in which certain information for an addressee is stored until a time at which a larger packet can be sent at a higher speed.

However, in computer networks where it must be ensured that all computers have a universal time base, it is also important to know when the information was sent, and also to know when the information was received from another networked computer WO99 / 33207 , Although computer clocks for the clocking of the computer allow to determine the time at which a computer has provided information to the network card, but not to recognize when the network card has actually carried out the transmission over the data transmission line. Therefore, additional computer clocks have been proposed, with which the time-critical data packets at the time of the actual transmission a time stamp is printed. Such computer clocks have already been switched between network controller and media-specific interface, wherein the network controller and the media-specific interface via a media-independent interface (MIIF) are connected to each other and the computer clock is switched between these two components. In order to provide the respective sending CPU with complete information about the actual time of the transmission of the information, this intermediate computer clock must confirm the time of the actual transmission to the assigned computer. In this context, it is now obvious, via a separate module to make a response in the system bus, such components may be referred to as a PCI bridge, for example, and communicate with the PCI bus of the computer. The circuitry and hardware complexity of such modifications is relatively large and requires additional equipment of computers with additional interfaces and other interface cards.

The invention now aims to reduce the hardware and circuitry overhead for the synchronization of a universal time base in information transmission networks and to subsequently avoid hardware changes, so that only by an appropriate software adaptation, the desired universal time base can be achieved with much higher precision. To solve this problem, the inventive method consists essentially in the fact that the time stamp are inserted after release of the program by a network controller from a downstream clock module in the outgoing or incoming data packet and that a CPU from the comparison of time stamps in an acknowledgment of the addressee Information and the timestamp of the associated transmitted information with an identifier provided actuating signals for the correction of the clock modules generated. Characterized in that the time stamps are inserted after release of the program by a network control circuit of a clock module, such clock modules can be arranged within the media-independent interface and also be placed directly on the network card, so that only the corresponding network card must be connected to the corresponding system bus of the computer , At the same time, this arrangement ensures that the time stamp is actually only inserted when the network controller carries out the transmission. A feedback of the correct reception, which is also provided with a time stamp, but now does not lead to a corresponding active synchronization of the clock circuits, since for the purpose of improving the precision and accuracy of the Time base control signals or setup signals and possibly control signals and / or status signals must be replaced with the clock module. However, such control signals may then, if a disturbance of the time base is to be reliably prevented by external influences, only from the associated CPU or a special network computer to be sent, these control signals may only be utilized by the respective addressed clock module. In the control of all clocks by a single computer in the network, the data transmission of each clock to the control computer by a simple (uncommented) return of the data packet is achieved by each local CPU. Hiebei can be done for the correction and control of a local computer clock by another computer in the network feedback status information by returning all marked for the local computer clock data packets to the other computer by the local CPU. According to the invention, it is therefore provided that a CPU from the comparison of timestamps in an acknowledgment of receipt of the addressee of the information and the timestamp of the own transmitted information now generates control signals provided with an identifier and makes them available exclusively to the clock module which is to make the corresponding correction. The additionally required in the context of such control signals identifier thus ensures that the computer associated clock module can be selectively addressed and can not be influenced by any signals from the network itself, so a high degree of security and the possibility of a continuous or iterative adjustment Also a higher precision can be achieved.

Advantageously, the inventive method hiebei performed so that control signals for the correction, control signals and / or status signals of the clock modules are transmitted with an identifier which is evaluated by a packet detection logic of a clock module and that such transmitted with the identifier control signals for correcting the time of respective clock module are used. In principle, As already mentioned, a separate bus connection for the feedback to the associated CPU for reasons of simplification of the hardware costs are avoided. In order to ensure that the corresponding actuating signals, control signals and / or status signals are actually only supplied to the respective associated clock module, it is thus necessary to ensure that the identifiers are recognized and evaluated by a component of the clock module itself or the network controller.

Some media-specific interfaces can be switched, for example by an additional data line to the effect that such signals are not returned to the network, but to the CPU, which have generated the signals, wherein such interface circuit can also be implemented directly in an assembly containing the clock circuit , Advantageously, the procedure is such that the network controller communicates directly with an interface circuit and generates a command for returning the control, control and / or status signals of a CPU sent to the clock circuit to the CPU which has generated the signals.

In this context, it is in principle possible and advantageous to use a special computer for the synchronization worfür the procedure is such that the data packets for the correction, control and status signals of a local computer clock on another computer in the network and calculated as a data packet to the network controller the respective computer clock are sent.

In a particularly simple manner can be done so that the synchronization of computer clocks in networks with switches, wherein the dwell time of each data packet is measured with correction, control and status signals for a local computer clock in a switch, and each switch with computer clock and appropriate timing devices on all switch ports.

The inventive means for synchronizing a universal time base is essentially characterized in that each network controller is associated with a clock module containing a packet detection logic and a clock controller, wherein sent by a CPU control, and / or status signals after checking the destination address in the network controller executed by the clock controller or processed and entered into the recognized package information. The recognition of the signals provided with an identifier can, as already mentioned, be carried out by a component of the clock module. The device can also be configured such that the network controller is connected to the interface for the transmission device reversal for the purpose of detecting setting, control and / or status request signals via a separate line, bypassing the clock module.

In order to further reduce the extent of the circuit modification, but can also be dispensed with such a separate control line between the network controller and media-specific interface, if in the switched into the media-independent interface clock module, the appropriate logic for detecting control, and / or Status query signals and a corresponding interface is integrated, which makes the return of such signals to the respective CPU, which has generated the signals. Advantageously, therefore, the training is such that the packet detection logic for detecting control, and / or status request signals and the associated computer clock combined to form an assembly, in particular integrated. In this way, a particularly simple and easily integrable in conventional network cards circuit arrangement is created in which it is only required in the sequence of the CPU by appropriate software programming to provide the opportunity to evaluate the returning signals accordingly to generate the required setup signals for the readjustment of the clock module.

The data packet according to the invention for the synchronization of clock circuits in information transmission networks for networked computers is characterized for this purpose in that the data packet contains, in addition to the fields for destination address, source address and data at least one identifier for packet types, which for control, control and / or Status request signals is characteristic. The usual transmission protocols, as used in data and communication technology, usually contain a defined number of bits for the packet type identifier, so that such identifiers can be accommodated without modification, for example in the bit structure of CSMA data packets with collision detection.

The invention will be explained in more detail with reference to embodiments shown schematically in the drawing. In this show Fig. 1 a first embodiment of the device according to the invention in the form of a block diagram and Fig. 2 a further embodiment of the device according to the invention.

In Fig. 1 1 is a clock for a CPU 2. The CPU 2 represents hiebei the central part of the computer, which is connected via a formed as a parallel bus bus structure 3 with a network controller 4 of a network card. In training after Fig. 1 and 2 For example, a bus structure was chosen as an example whose backbone is denoted by 5. The connection to this backbone of the network is established by the media-specific interface 6, in which the adaptation to the level required by the respective medium takes place. Between the media-specific interface or the interface 6 and the network controller 4 lines 7 are provided, which in total represent media-independent interface between network controller 4 and the media-specific interface 6. In these lines 7, a clock module 8 is now turned on, which always when the network controller forwards a data packet to the media-specific interface 6, the media pack in the case of time-critical information imprints a timestamp. The feedback that a signal has been received from another CPU 2, again via the line 5, the media-specific interface 6, the network controller 4 and the parallel bus 3 to the CPU 2. A comparison of the time stamp of the own clock module with the time stamp of Receiver allows, taking into account the known or measured transit time of the signals between two known addresses a conclusion on the accuracy of the time base and allows it to generate in the sequence of a CPU 2 signals with which the clock frequency of the own clock module 8 is adjusted accordingly to increase the accuracy. In this way, synchronizations can be achieved in which the known maximum deviation of the clocks in the clock generators from each other computers can be kept in the nanosecond range. The corresponding setup or control signals are then routed from a CPU 2 again via the network controller 4 to the clock module 8, wherein in the training after Fig. 1 the network controller 4 itself is able to recognize such setup signals due to their identifier as setup signals. In these cases, the network controller 4 communicates via the line 9 to the media-specific interface 6, that this information is not intended for transmission to the network 5, but rather, together with a corresponding confirmation of the clock module 8 via the correction carried out in turn the own CPU 2 returned shall be.

In training after Fig. 2 are essentially the same components in use, in which case the additional control line 9 is omitted. The clock module 8, with which the time stamp is impressed, contains hiebei in addition a simple variant of a network controller 10 in the form of a packet detection logic and a clock controller 11, so that within the module containing the clock module 8, the corresponding detection of setup signals can be done.

Claims (8)

1. Method for synchronizing computer clocks in networks used for information transfer, in which information is sent with a time stamp at the moment of its sending and is returned with a time stamp in a receipt confirmation, characterized in that the time stamps, after the release of the transfer by a network controller (4,10), are inserted by a clock module (8) subsequent in the data path into the outgoing or incoming data packet and that a CPU (2) generates configuration signals being equipped with an identifier for correction of the clock modules (8) based on a comparison of time stamps in a receipt confirmation of the addressee of the information and the time stamp of the corresponding sent information and taking into account the known or measured run times of signals between the sender and the addressee.
2. Method according to claim 1, characterized in that the configuration signals for correction, control signals and/or status signals of the clock modules (8) are transferred with an identifier that is evaluated by a packet detection logic of a clock module (8) and that such configuration signals transferred with the identifier are used for correction of time of the respective clock module (8).
3. Method according to claim 1 or 2, characterized in that the network controller (4) directly communicates with an interface circuit (6) and generates a command for the local return of configuration, control and/or status signals of the CPU (2) sent to the clock module (8) back to the CPU (2).
4. Method according to claims 1, 2 or 3, characterized in that the data packets for the configuration, control and status signals of a local computer clock (8) are calculated on another computer in the network and are sent as a data packet to the network controller (4,10) of the respective computer clock (8).
5. Method according to anyone of claims 1 to 4, characterized in that the synchronization of computer clocks (8) is performed in networks having switches, the residence time of each data packet with configuration, control and status signals for a local computer clock (8) is measured in a switch, and each switch is equipped with a computer clock (8) and suitable time measurement devices at all switch ports.
6. Device for synchronizing computer clocks in networks for information transfer, in which the information is provided with a time stamp at the moment of its sending and is provided with a time stamp at the moment of its receipt at the target address, characterized in that a clock module (8) is assigned to each network controller (4, 10), the network controller containing a packet detection logic and a clock controller (11), wherein configuration, control and/or data signals sent by a CPU (2) are executed or processed by the clock controller (11) after the network controller (4,10) has checked the target address and information is entered into the detecting packet.
7. Device according to claim 6, characterized in that the packet detection logic for detecting configuration, control and/or status query signals and the corresponding computer clock (8) are combined into one component group, and in particular are formed integrated.
8. Data packet for the synchronization of computer clocks according to anyone of claims 1 to 5, characterized in that the data packet in addition to the fields for the target address, source address and data contains at least one identifier for packet types, that is characteristic for configuration, control and/or status query signals.

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