EP1261025A3 - Semiconductor device and method of fabricating same - Google Patents

Semiconductor device and method of fabricating same Download PDF

Info

Publication number
EP1261025A3
EP1261025A3 EP02011760A EP02011760A EP1261025A3 EP 1261025 A3 EP1261025 A3 EP 1261025A3 EP 02011760 A EP02011760 A EP 02011760A EP 02011760 A EP02011760 A EP 02011760A EP 1261025 A3 EP1261025 A3 EP 1261025A3
Authority
EP
European Patent Office
Prior art keywords
dielectric layer
base
base region
stopper
graft base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP02011760A
Other languages
German (de)
French (fr)
Other versions
EP1261025A2 (en
EP1261025B1 (en
Inventor
Hisamitsu Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of EP1261025A2 publication Critical patent/EP1261025A2/en
Publication of EP1261025A3 publication Critical patent/EP1261025A3/en
Application granted granted Critical
Publication of EP1261025B1 publication Critical patent/EP1261025B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248Combination of bipolar and field-effect technology
    • H01L21/8249Bipolar and MOS technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts

Abstract

A semiconductor device raises the maximum oscillation frequency fmax of the bipolar transistor. The stopper dielectric layer is formed on the substrate to cover the transistor section and the isolation dielectric. The interlayer dielectric layer is formed on the stopper dielectric layer. The base contact plug, which is formed in the interlayer dielectric layer, is located over the isolation dielectric in such a way as to contact the graft base region near its bottom end corner. Therefore, the base contact needs not to entirely overlap with the graft base region, which means that the graft base region can be narrowed without increasing the base resistance Rb and that the collector-base capacitance Ccb is reduced. Also, electrical short circuit between the graft base region and the collector region can be effectively suppressed by the stopper dielectric layer.
EP02011760A 2001-05-25 2002-05-27 Semiconductor device and method of fabricating same Expired - Fee Related EP1261025B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001157313A JP3621359B2 (en) 2001-05-25 2001-05-25 Semiconductor device and manufacturing method thereof
JP2001157313 2001-05-25

Publications (3)

Publication Number Publication Date
EP1261025A2 EP1261025A2 (en) 2002-11-27
EP1261025A3 true EP1261025A3 (en) 2005-01-12
EP1261025B1 EP1261025B1 (en) 2008-07-09

Family

ID=19001200

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02011760A Expired - Fee Related EP1261025B1 (en) 2001-05-25 2002-05-27 Semiconductor device and method of fabricating same

Country Status (6)

Country Link
US (1) US6906363B2 (en)
EP (1) EP1261025B1 (en)
JP (1) JP3621359B2 (en)
KR (1) KR20020090352A (en)
DE (1) DE60227451D1 (en)
TW (1) TW556339B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7084485B2 (en) * 2003-12-31 2006-08-01 Freescale Semiconductor, Inc. Method of manufacturing a semiconductor component, and semiconductor component formed thereby
KR101118652B1 (en) * 2004-12-17 2012-03-07 삼성전자주식회사 Bipolar Junction Transistor with high Gain integratable with CMOS FET process and Method for Forming the Same
KR101030295B1 (en) * 2004-12-30 2011-04-20 동부일렉트로닉스 주식회사 Field Transistor for Testing Isolation in Semiconductor Device
KR20060078251A (en) * 2004-12-31 2006-07-05 동부일렉트로닉스 주식회사 Composite pattern for measuring semiconductor device characteristics
JP4455356B2 (en) * 2005-01-28 2010-04-21 Necエレクトロニクス株式会社 Semiconductor device
US9123558B2 (en) * 2011-06-20 2015-09-01 Mediatek Inc. Bipolar junction transistor
CN102412272B (en) * 2011-07-28 2013-09-11 上海华虹Nec电子有限公司 Vertical parasitic type PNP device in BiCMOS technology
CN109148416B (en) * 2018-08-31 2020-06-16 上海华虹宏力半导体制造有限公司 Semiconductor device structure and forming method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0349107A2 (en) * 1988-06-30 1990-01-03 Sony Corporation Semiconductor devices
US4892837A (en) * 1987-12-04 1990-01-09 Hitachi, Ltd. Method for manufacturing semiconductor integrated circuit device
EP0409370A2 (en) * 1985-05-07 1991-01-23 Nippon Telegraph And Telephone Corporation Bipolar transistor

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2280550A1 (en) 1974-08-01 1976-02-27 Multivac Haggenmueller Kg Sealed object packing machine - with endless chain drive via sprockets with ratchet teeth
US4789885A (en) * 1987-02-10 1988-12-06 Texas Instruments Incorporated Self-aligned silicide in a polysilicon self-aligned bipolar transistor
JPH03165039A (en) * 1989-11-24 1991-07-17 Nec Corp Vertical bipolar transistor
JPH0422133A (en) * 1990-05-17 1992-01-27 Fujitsu Ltd Bipolar transistor
US5121184A (en) 1991-03-05 1992-06-09 Hewlett-Packard Company Bipolar transistor containing a self-aligned emitter contact and method for forming transistor
EP0529717A3 (en) 1991-08-23 1993-09-22 N.V. Philips' Gloeilampenfabrieken Method of manufacturing a semiconductor device having overlapping contacts
JPH05267317A (en) * 1992-03-18 1993-10-15 Fujitsu Ltd Semiconductor device and its manufacture
JPH0677241A (en) * 1992-09-17 1994-03-18 Sony Corp Bipolar transistor
JP3472623B2 (en) * 1994-07-08 2003-12-02 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP2000252294A (en) * 1999-03-01 2000-09-14 Nec Corp Semiconductor device and its manufacture
JP3748744B2 (en) 1999-10-18 2006-02-22 Necエレクトロニクス株式会社 Semiconductor device
JP2002252294A (en) 2001-02-22 2002-09-06 Sumitomo Metal Electronics Devices Inc Solder and semiconductor package using it

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0409370A2 (en) * 1985-05-07 1991-01-23 Nippon Telegraph And Telephone Corporation Bipolar transistor
US4892837A (en) * 1987-12-04 1990-01-09 Hitachi, Ltd. Method for manufacturing semiconductor integrated circuit device
EP0349107A2 (en) * 1988-06-30 1990-01-03 Sony Corporation Semiconductor devices

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 0161, no. 85 (E - 1197) 6 May 1992 (1992-05-06) *
PATENT ABSTRACTS OF JAPAN vol. 0183, no. 26 (E - 1565) 21 June 1994 (1994-06-21) *

Also Published As

Publication number Publication date
JP2002353232A (en) 2002-12-06
US20040195586A1 (en) 2004-10-07
EP1261025A2 (en) 2002-11-27
US6906363B2 (en) 2005-06-14
JP3621359B2 (en) 2005-02-16
TW556339B (en) 2003-10-01
DE60227451D1 (en) 2008-08-21
EP1261025B1 (en) 2008-07-09
KR20020090352A (en) 2002-12-02

Similar Documents

Publication Publication Date Title
TW200505033A (en) Capacitor and method of fabricating the same
US8785987B2 (en) IGFET device having an RF capability
TWI267164B (en) Bipolar transistor structure and methods using shallow isolation extension to reduce parasitic capacitance
US9780164B2 (en) Silicon-on-insulator radio frequency device and silicon-on-insulator substrate
TW200518338A (en) Semiconductor device and making thereof
WO2005034201A3 (en) Metal-insulator-metal capacitor and method of fabrication
TW200507258A (en) Device with low-k dielectric material in close proximity thereto and its method of fabrication
KR930020666A (en) Vertical Integrated Semiconductor Structures
US6987983B2 (en) Radio frequency monolithic integrated circuit and method for manufacturing the same
TW200505032A (en) Capacitor with enhanced performance and method of manufacturing the same
WO2003103032A3 (en) A method for making a semiconductor device having a high-k gate dielectric
US9299601B2 (en) SOI RF device and method for forming the same
US7323749B2 (en) Semiconductor device comprising an integrated circuit
EP1261025A3 (en) Semiconductor device and method of fabricating same
WO2007015194A3 (en) Semiconductor device and method of manufacturing such a device
CN105161491A (en) Integrated gate driver transistor (IGDT) power device and manufacturing method thereof
WO2003041171A3 (en) Heterojunction bipolar transistor with integrated mim capacitor
TW200644124A (en) Bipolar transistor and method of fabricating the same
WO2002103785A3 (en) Cmos process
KR960043167A (en) Semiconductor integrated circuit device and manufacturing method thereof
EP1191604A3 (en) Semiconductor memory device
WO2003075361A3 (en) Monolithic integrated soi circuit with capacitor
WO2000045441A3 (en) Semiconductor device with a multiple dielectric
KR940008130A (en) Semiconductor device and manufacturing method thereof
TW200514193A (en) Deep trench capacitor and method for fabricating the same

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: NEC ELECTRONICS CORPORATION

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

17P Request for examination filed

Effective date: 20041202

17Q First examination report despatched

Effective date: 20050504

AKX Designation fees paid

Designated state(s): DE NL

17Q First examination report despatched

Effective date: 20050504

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE NL

REF Corresponds to:

Ref document number: 60227451

Country of ref document: DE

Date of ref document: 20080821

Kind code of ref document: P

NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20080709

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20090414

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20091201