EP1213700B1 - Display device with adaptive selection of the number of simultaneously displayed rows - Google Patents

Abstract

Display device with a driver circuit (1) and a display (2) with a number of rows (R) and columns (C) with a number (P) of rows controlled simultaneously using multiple row addressing (MRA). The number of rows used in the display can be adjusted for a partial display mode. With the voltage supply required for each unused row not activated. An Independent claim is made for a driver circuit with a number of voltage driver steps for production of a number of partial voltage values for controlling a partial display.

Description

The invention relates to a display device with a driver circuit and a liquid crystal display with several rows R and columns C. Furthermore, the invention relates to a driver circuit for driving a display.

In the next few years, display technology will play an increasingly important role in information and communication technology. As an interface between humans and the digital world, the display device has a central significance for the acceptance of modern information systems. In particular, portable devices such as notebooks, telephones, digital cameras and personal digital assistant are not feasible without the use of displays. A very widespread LCD technology is the passive matrix LCD technology, which is used, for example, in laptops and mobile phones. By means of the passive matrix display technology large displays can be realized, whereby these are mostly based on the (S) TN (Super Twisted Nematic) effect. A passive matrix LCD consists of a number of layers. The display is divided into rows and columns in matrix form. In this case, the row and column electrodes which are respectively arranged on substations form a grid. Between these substrates, the layer is arranged with the liquid crystal. The intersections of these electrodes form pixels or pixels. Voltages are applied to these electrodes which align the liquid crystal molecules at the driven pixels in a corresponding direction and thus make the driven pixel visible.

With increasing display sizes, power consumption is becoming more important in passive matrix LCD displays for mobile applications, as these passive matrix displays are commonly used in portable devices, it is particularly important to achieve low power consumption. A suitable means of reducing power consumption is the effective use of a standby mode. In mobile telephones, for example, all unnecessary components are deactivated. The display is also switched to a partial display mode.

In addition to the power consumption is also the optical performance of these STN LC displays a key criterion for the selection of such display devices. In this type of STN LC displays an addressing technique is known in which several rows are controlled simultaneously and the encoded image information is added to the columns. This MRA technique (multiple row addressing) allows a very good optical performance with low power consumption.

In this MRA technique, a number of p-rows are driven simultaneously. In this case, a set of orthogonal functions is applied to the simultaneously driven rows p. From this set of orthogonal functions, a function for controlling the corresponding column is calculated according to a calculation rule. By means of this function for controlling the column, a voltage is selected from a set of partial voltage values which is applied to the corresponding column and thus the corresponding pixels or pixels are switched to an input or output state in dependence on the data supplied from a memory.

In the partial display mode, the entire display is not driven, i. only parts of the display are needed to display information. In the case of addressing by means of the MRA technique, however, it is necessary for the best optical performance to select an optimum value p of the number of simultaneously driven rows.

To control p simultaneously driven rows p + 1 different voltages are needed. These are generated in a driver circuit for driving the display by means of a plurality of voltage driver stages. The driver circuit is designed such that these driver circuits drive the maximum possible number p of rows to be controlled simultaneously and also have so many voltage driver stages.

With such driver circuits, it is not possible to influence the circuit in the partial display mode in such a way that the power saving is optimized. In addition, with such a driver circuit only a limited number of different can be controlled.

In the publication "Some new addressing techniques for rms responding matrix LCDs", February 1998 by T.N. Ruckmongathan; PHD Thesis, Indian Institute of Science, Bangalore, XP 002240917 a display device with a driver circuit for driving a display with N rows and M columns is described. It is described that 1 lines can be controlled simultaneously, whereby 1 can assume different values. An improved hybrid driving method (IHAT) for LCDs is described in which the requirements for the power supply are reduced. IHA. The supply voltages are significantly lower than with the improved control method according to Alt & Pleshko (IAPT).

EP 0811866 A1 describes a drive method for a display in which only one voltage value is used to deactivate the lines. The same voltage is applied to the data lines (columns) so there is no voltage difference. Since only one voltage value is used to disable the rows, the requirement to provide multiple partial voltage values is reduced.

EP 0990940 A1 describes a method for driving an LC display in which several lines of an LC display are simultaneously activated. In this case, a reduced number of partial voltages is used. In particular, it is described to select the line voltage equal to the column voltage.

JP 10 214063 A describes an LC display in which a selection and disconnection of stages of a voltage supply for column and row electrodes, a reduction in power consumption is achieved when only a part of the display is operated.

The article "Mos integrated circuit μPD 16683,4 gray scale1 / 100, 1/64 duty lcd controller / driver built in RAM, Preliminary Product information, NEC Corporation December 1998, Japan, describes the shutting off of stages of power supply for row and column electrodes an LC display.

The object of the invention is to provide a device by means of which the number p of simultaneously driven rows of a display can be adaptively selected with decreasing power consumption and for different display sizes.

This object is achieved according to the invention by a driver circuit for controlling a LC display subdivided into N rows and C columns in matrix form, the driver circuit comprising: a voltage generation unit having p-1 voltage driver stages for providing p-1 partial voltages and two supply voltages Vdd and Vss, a first Means for driving the N rows of the LC display, the p rows of the display at the same time a combination of p orthogonal functions with a maximum Reihenspannüng F or a minimum row voltage -F supplies, a second means for driving the columns of the LC display with column voltages which selects the column voltages from an amount of p-1 sub-voltages having a maximum sub-voltage GMAX and a minimum sub-voltage -Gmax, where both the maximum sub-voltage GMAX and the maximum series voltage F and the minimum sub-voltage -GMAK and the minimum series voltage -F equal are big and a partial operation mode for driving a portion of the LC display having N 'lines, with N'<N, and the driver circuit includes a calculation unit for calculating the number of orthogonal functions p 'simultaneously p' rows of the portion of the LC display are supplied, depending on the number of lines N ', and means for switching off the pp' voltage driver stages not required in the partial operating mode are arranged.

The invention is based on the idea that in the partial display mode, the optimum number p of the simultaneously driven rows is generally lower than in the control of the entire display. Since the use of the MRA addressing technique always p + 1 different partial voltage values are required, the two voltage levels V _LCD and Vss are included, consequently less partial voltage values are required in the partial display mode.

In order to achieve the best optimal performance with this MRA addressing technique, the number p of the simultaneously selected rows must be optimally selected. For example. For a LCD display with 64 or more rows, a number p of simultaneously driven rows of 8 must be selected to achieve the best optical performance with low LCD supply voltage.

A first step in reducing the complexity of the driver circuit and at the same time reducing the power consumption of the LCD driver circuit is achieved by equal maximum voltages for driving the columns and rows. When the row voltages F, -F and the highest and lowest column voltages G _MAX , -G _{MAX are set} equal, only p-1 sub-voltages are needed. This results in fewer partial voltage levels that must be generated for the LCD display, thereby reducing the complexity and power consumption of the LCD driver, as it eliminates the need to drive all existing voltage driver stages.

But only with equal maximum column and row voltages can be None Realize partial display mode.

LCD fluids have a property called multiplexibility m. This property indicates how many rows can be driven at maximum. This multiplexibility m is selected such that it is at least as large as the maximum possible number of rows of the display to be controlled requires. This gives you a further degree of freedom in the choice of p, which makes it possible to set F and G _MAX to the same voltage level for different display sizes in a partial display mode. To achieve this, p and m can be varied.

According to the invention, it is proposed to make the number p of the simultaneously driven rows adaptive. This makes it possible to use the LCD driver for many different purposes. A partial display mode is thus feasible while reducing the complexity of the driver and reduced power consumption. The voltage driver stages required for the generation of the individual partial voltage values are only switched on as required in such a case by means of a switching device. This reduces power consumption in general and especially in partial display mode. Derived from an operating mode of the device in which the display is operated, a processor generates a signal with which the display is switched to the partial display mode. Then, based on the display size and the operating mode, the optimum number p is calculated or determined, with which the power consumption can be minimized. By means of this number p, the switching device is controlled. This switching device switches off the power driver stages that are no longer needed so that they do not consume any power. In a partial display mode with 32 rows in which, for example, only 2 rows are controlled simultaneously, only 3 voltage values are required, two of these being the two supply voltages and only one partial voltage being required.

Fig.1

eine Prinzipschaltung der erfindungsgemäßen Anzeigevorrichtung

Fig.2

Teilspannungswerte für einen MRA-LCD-Treiber p=8

Fig.3

Teilspannungserzeugung für einen LCD-Treiber mit p=8

Fig.4

Teilspannungserzeugung für p=4

Fig.5

Teilspannungserzeugung für p=2

Fig. 6

Auslesesequenz für p=8

Fig. 7

Auslesesequenz für p=4

Fig. 8

Auslesesequenz für p=2

The invention will now be described and explained in detail with reference to exemplary embodiments shown in the drawings. Show it:

Fig.1

a principle circuit of the display device according to the invention

Fig.2

Partial voltage values for an MRA-LCD driver p = 8

Figure 3

Partial voltage generation for a LCD driver with p = 8

Figure 4

Partial voltage generation for p = 4

Figure 5

Partial voltage generation for p = 2

Fig. 6

Readout sequence for p = 8

Fig. 7

Readout sequence for p = 4

Fig. 8

Readout sequence for p = 2

Fig. 1 shows; the driving circuit 1, the display 2 and the microcontroller 3. Here, the driving circuit 1 includes a memory 9 in which the image data is stored. Further, the driving circuit 1 includes a voltage generating unit 4. In a calculating unit 5, the optimum value for the number p is calculated. By means of this optimum value of p, the switching device 10 of the voltage generating unit 4 is controlled. The partial voltages generated in the voltage generation unit 4 and the two supply voltages are fed to a switch 7. A function generator 6 generates sets of orthogonal functions which are supplied to the rows as a function of the value p. These sets of orthogonal functions are also routed to this switch 7. There, the provided partial voltages and the orthogonal functions are linked and fed as a set of orthogonal functions respectively to the p rows to be controlled simultaneously. The p-1 partial voltage values and the two supply voltages V _LCD and Vss are also supplied to the switch 8. The set of orthogonal functions generated by function generator 6 is also supplied to switch 8. In the switch 8, by means of the set of orthogonal functions, the value p and image data read from the memory 9 corresponding to the p-driven rows of a column, the column voltage G is calculated according to the MRA theory. This column voltage is selected from the set of partial voltages.

The microcontroller 3 may, for example, be integrated in a mobile telephone. Depending on the operating status of this device, it is determined in which display mode the display must be operated. If only a partial display is required in standby mode, the look-up table stored in a memory (not shown) is used to select the corresponding p-value which offers the best optical performance. By means of this p value, the individual stress heat states in the voltage generation unit 4 turned on when needed. This makes it possible that in a case in which 4 rows are driven simultaneously, only 5 different partial voltage values are generated and thus the power consumption for driving a display is lower than if 5 partial voltages were used for p = 4 and still 9 Partial stresses would be generated or prepared.

Table 1 shows the necessary supply voltages for the display for different partial display modes and multiplexibilities m of the display. Here, F [V] is the voltage with which the rows of the display are controlled and G _MAX [V] the maximum voltage with which the columns of the display are controlled. Both voltages can tend to both positive and negative, so that a total supply voltage V _LCD [V] is required for the display, which is twice that of F and G _MAX . Table 1: required V <sub> LCD </ sub> for a V <sub> TH </ sub> = 1.8 V for partial display mode with adaptive p value Display Size N m p F [V] _Gmax [V] V _LCD [V] 16 16 25 2 2:55 2:55 5.1 24 24 49 2 2:55 2:55 5.1 32 32 81 2 2:55 2:55 5.1 40 40 49 4 3.29 3.29 6:58 48 48 64 4 3:33 3:33 6.66 56 56 81 4 3:38 3:38 6.76 64 64 64 8th 3.85 3.85 6.70 80 80 81 8th 4:02 4:02 8:04

$$Vd=V_{TH}·\sqrt{\frac{N}{2·\left(\sqrt{m}-1\right)·\left(\sqrt{m}\pm \sqrt{m-N}\right)}}$$

$$F=\frac{V_S}{\sqrt{p}}$$

$$G_{\mathrm{MAX}}=\sqrt{p}\cdot V_D$$

Fig. 2 shows the partial voltage levels for an MRA system with 8 simultaneously selected rows. Here are the row voltage and the maximum column voltage read Different values. Accordingly, different voltages are required at p = 8 and F ≠ G _MAX 11. The series voltage (-F, V _C , F) and the column voltages (-G _MAX ... V _C .. G _MAX ) are equidistant around the level Vc. In general, four different p + 1 voltage values are needed to control the columns. By means of the formulas 3 and 4, the row voltages F and the maximum column voltage G _MAX can be calculated. The voltages Vd and Vs are variables from the Alt & Pleshko method (Alt & Pleshko "scanning limitations of liquid crystal displays", IEEE Trans El.Dev, Vol.Ed21, No.2 feb. 1974 pp-146-155) and are with following formulas (1) and (2) calculated. $$V_S=V_{TH}·\sqrt{\frac{\mathrm{<figure-callout\; id="2"\; label="N"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">N</figure-callout>}}{2}·\frac{\sqrt{m}\pm \sqrt{m-N}}{\sqrt{m}-1}}$$

$$Vd=V_{TH}·\sqrt{\frac{\mathrm{<figure-callout\; id="2"\; label="N"\; filenames="imgf0001.png,imgf0003.png"\; state="\{\{state\}\}">N</figure-callout>}}{2·\left(\sqrt{m}-1\right)·\left(\sqrt{m}\pm \sqrt{m-N}\right)}}$$

$$F=\frac{V_S}{\sqrt{p}}$$

$$G_{\mathrm{MAX}}=\sqrt{p}\cdot V_D$$

In order to reduce the number of necessary different voltage values, the row voltages F and the maximum column voltage G _{MAX are set} equal. In Fig. 3, the voltage generating unit 4 is shown in the case that 8 rows are driven simultaneously. Here, the series voltage F and the maximum column voltage G _{MAX are set} equal, so that V ₁ = V ₂ = V _LCD and V ₁₀ = V ₁₁ = V _SS , so that only 9 different voltage levels are needed, the V _LCD and The V _SS need not be generated separately, but are necessary for the general power supply of the driver circuit. Since the maximum column voltage is not necessarily lower than the row voltage, equalizing the maximum column voltage G _MAX with the row voltage F and -F achieves a reduction in the complexity of the voltage generation unit. The switching device 10 controls the disconnection of the voltage driver stages V ₃ to V ₉ as a function of the optimum value p. In the case of p = 8, all 7 possible partial voltages are generated by means of the voltage driver stages.

4 shows the generation of 5 voltage values V _LCD , V ₄ , V ₆ , V ₈ and V _SS in case the number p of the simultaneously driven rows is equal to 4. The disconnected voltage driver stages V ₃ , V ₅ , V ₇ , V ₉ are shown in dashed lines, wherein the switching means are open in the switching device 10 for the corresponding unused voltage driver stages.

Table 2 shows the partial voltage values for different values p which are fed to the display. Table 2: Partial voltage values for different p values Bias level p = 8 p = 4 p = 2 V1 V _LCD V _LCD V _LCD string V2 V _LCD V _LCD V _LCD columns V3 7/8 V _LCD - - columns V4 3/4 V _LCD 3 / 4V _LCD - columns V5 5/8 V _LCD - - columns V6 1 / 2V _LCD 1 / 2V _LCD 1 / 2V _LCD Rows and columns V7 8.3 V _LCD - - columns V8 1/4 V _LCD 1/4 V _LCD - columns V9 1/8 V _LCD - - columns V10 V _ss V _ss V _ss columns V11 V _ss V _ss V _ss string

Here it becomes visible that for p values lower than 8 the corresponding voltage drivers are switched off. Since the voltage generation unit 4 only has to generate fixed partial voltage values, the complexity of the driver circuit is reduced.

5 shows the generation of partial voltage values for the control of a display in which only 2 rows are simultaneously activated. Here, only 3 different voltage levels are required, two of these are already given by the two Vesorgungsspannungslevel V _LCD and V _SS , so that only V ₆ must be generated as a partial voltage value.

The adaptive selection of the simultaneously driven rows makes it possible, with a reduction in power consumption, to always provide the best optical performance for each Display size is possible. At the same time switching to a partial display mode while reducing the power consumption is possible, Furthermore, the driver circuit can be used for many different display sizes, the requirements for the multiplexibility of the LCD liquid can be reduced.

In the case of the adaptive selection of the rows addressed simultaneously, it must also be taken into account at the same time that, given different values of p, different sets of orthogonal functions are used.

In order not to complicate the complexity of the driver circuit by changing memory access at different p values, it is necessary to design the memory access sequence independently for all values p. The function generator provides different sets of orthogonal functions for different values p supplied to the switches 7 and 8. For the case p = 8, 8 orthogonal functions are combined with the 8 data bits read from the RAM 9. In this case, p data bits which determine the state of the driven pixels of the simultaneously driven rows are read out with a single access for each column.

If the value p is reduced to 4 simultaneous rows, only 5 partial voltage values are necessary, so that 4 voltage drivers are switched off and the whole system is downscaled and thus the LCD supply voltage is reduced.

The sequence of the control of the rows remains the same for all possible numbers p of the rows to be controlled simultaneously. In particular, the memory access is unchanged. The sequence of the control of the series is designed for the maximum possible number p and on the basis of this value p the sequences for the lower values p are derived. Thus, for p = 8, the data of 8 rows per column is read from the memory, linked to the 8 orthogonal functions, and the column driven accordingly. At the same time, the associated 8 rows are selected and driven (Figure 6). If p = 4 (Figure 7), the same 8 data bits are read as at p = 8. However, the selection of the series is divided into 2 sub-steps. In a first step, the first 4 rows of the 8 become maximum driven simultaneously controllable rows and in a second step, the other 4 rows are driven, in which case no memory access is necessary. For p = 2 (Figure 8), the drive of the 8 rows is further divided into 4 by 2 row increments. Again, the 8 data bits are read from the memory 9 in one go. This has the advantage that the memory access remains unchanged. Thus, the addressing of the memory 9 is independent of the selection p.

However, the sequence of driving the rows is not always as simple as shown in Figs. 6-8, where the first row of the first block is also the first row on the display and will be described top to bottom. This sequence can be much more complicated. The above-described mechanism of deriving the drive at a lower number p from the maximum allows easy adaptation to the various functionalities of modern applications such as scrolling, mirroring or the compatibility of Tape Carrier Packags TCP over chip-on-glass applications and the system is easier to adapt to different display chips.

Claims (4)

1. A driver circuit for addressing a matrix formed LC display (2) subdivided into N rows and C columns, the display comprising:

   - a voltage generator unit (4) with p-1 voltage driver stages for rendering available p-1 component voltages and two supply voltages Vdd and Vss

   - a first driver means (7) for addressing the N rows of the LC display, which first driver means simultaneously supplies a combination of p orthogonal functions with a maximum row voltage F or a minimum row voltage -F each time to p rows of the display,

   - a second driver means (8) for addressing the columns of the LC display with column voltages, which second driver means selects the column voltages from a plurality of the p-1 component voltages having a maximum component voltage GMAX and a minimum component voltage -GMAX, while both the maximum component voltage GMAX and the maximum row voltage F and the minimum component voltage

   - GMAX and the minimum row voltage -F are equally large

   characterized in that

   - a partial operation mode is provided for driving a sub-range of the LC display of the driver circuit with N' rows, with N'<N, and the driver circuit has a computation unit (5) for computing the number of the orthogonal functions p', which are simultaneously supplied with p' rows of the sub-range of the LC display in dependence on the number of rows N', and means (10) are arranged for switching off the p-p' voltage driver stages which are not needed in the partial operation mode.
2. A driver circuit as claimed in claim 1, characterized in that a memory access sequence, which comprises a sequence of bits and with which the image data to be displayed can be supplied from a memory (9) to the columns C and the number of p is the same for all different values.
3. A driver circuit as claimed in claim 1 or 2, characterized in that for the value of p', which is smaller than a maximum value p_max, there is provided that p_max data bits are to be read from a memory (9) where the p_max data bits are divided over p_max/p' sub-ranges.
4. Display devices comprising a driver circuit (1) as claimed in claim 1 and an LC display (2), characterized in that the display (2) contains an LCD liquid that has a multiplexibility where the multiplexibility m ≥ N.

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