EP1164593A1 - Voltage regulator for a reference cell in a dynamic memory, reference cell, memory and method thereof - Google Patents

Abstract

The voltage regulation unit (5) is a reference for a memory in lines and columns. There is a capacity (6) of predetermined value adapted to discharge during memory access.

Description

The invention relates to the field of memory cells or memory points of a dynamic random access memory (DRAM: dynamic random access memory).

As opposed to static random access memory (SRAM) in which the stored information remains at least indefinitely as long that this memory remains supplied, the dynamic memories have the peculiarity of requiring a periodic refreshment of information stored due, in particular, to leakage currents parasites which discharge the storage capacity of each memory point.

Classically, dynamic random access memories are organized in rows and columns of memory cells and include, for each column, an amplification device for reading / rewriting each memory cell selected, this device comprising precharge means for precharging the corresponding column of the matrix (commonly called "bit line" by human profession) at a selected voltage level and amplification means comprising, for example, two looped reversers, forming a rocker bistable, each formed of two complementary transistors and controlled by two successive read and rewrite signals.

Most dynamic memories include cells for equalizing the charges in the bit lines and for maximize the average amplitude of the signal between the logical 0 and the 1 logic. Reference cells usually include a connection or port connected to the bit line and another connection or port connected to a reference voltage. The fact of using reference cells having the same capacity value as the memory cell allows to obtain exactly the same capacity at each node when accessing on a line. The voltage value that is stored in the reference cell is equal to half of the reference voltage. To get the same margin of variation for the two binary values 0 logical and 1 logical, the reference must be set at the midpoint, i.e. at half the reference voltage. A voltage equal to half the value of reference must therefore be preloaded in the reference cell between two line access.

Generally, a voltage generator is used provided with active components. Such a generator must be fast, otherwise the duration preload will have an effect on performance, which means that the generator is large and consumes a lot of current understood in slow motion. Changing the setting of such a generator is the more often impossible because it offers satisfactory precision only on a reduced voltage range.

The invention proposes to remedy these drawbacks.

A new means for providing a adequate voltage for a reference cell, economical, versatile and low energy consumption.

The device, according to one aspect of the invention, is intended for voltage regulation for reference cell of a random access memory dynamic organized in rows and columns, comprising a plurality of memory cells. The device includes at least one capacity for predetermined value capable of being discharged during a memory access.

Preferably, said capacity is able to be completely discharged during a memory access.

In one embodiment of the invention, the value of said capacity is equal to: C _cell * (V _rcf -V _rci ) / V _rci with C _cell the capacity of the reference cell, V _rcf the voltage of the cell of reference after a memory access, and V _rci the voltage of the reference cell before a memory access.

In one embodiment of the invention, the device includes a first switch arranged at the input of said capacity for controlling a charge of said capacity, a charge current being likely to come from a reference cell. We can thus obtain a precisely known voltage on the reference cell.

In one embodiment of the invention, the device includes a second switch disposed at the output of said capacity to command a discharge of said capacity. We can bring it back to zero the voltage across said capacitance.

Preferably, the device comprises a plurality of capacities existing on an integrated circuit.

Advantageously, the device shares at least one capacity with at least one other similar device. Several devices will be able to share a certain number of capacities.

The reference cell, according to one aspect of the invention, is intended for dynamic random access memory and includes a device such as above.

Preferably, the cell comprises a first port able to be connected to a memory cell and a second port connected to the regulation.

The memory, according to one aspect of the invention, comprises a cell as above.

The method, according to one aspect of the invention, is intended for the voltage regulation of a reference cell for random access memory dynamic organized in rows and columns, comprising a plurality of memory cells. We share a load between at least two capacities of predetermined values during an initialization step and we discharge one of the two capacities during memory access.

So, we charge said capacity during load sharing and we discharge during memory access.

Preferably, the load that we share comes from a capacity a reference cell.

In one embodiment of the invention, one or more several existing capacities of an integrated circuit.

In one embodiment of the invention, n capacities are used for regulating the voltage of p reference cells, with n different from p. Each reference cell has a capacity value equal to the sum of the capacities divided by p. If the capacities are of equal values C _cal , each reference cell benefits from a capacity value equal to C _cal * n / p.

One thus obtains a means of generating a voltage of reference perfectly suited to the reference cells, not occupying that a small surface of silicon and whose energy consumption is almost zero.

• la figure 1 est une vue schématique d'une cellule de référence et d'un dispositif de régulation de tension ; et
• la figure 2 est une vue schématique d'une cellule mémoire.

An embodiment of the invention is illustrated by the accompanying drawings:

• Figure 1 is a schematic view of a reference cell and a voltage regulation device; and
• Figure 2 is a schematic view of a memory cell.

In Figure 1, there is shown, for simplification purposes, a single reference cell 1 comprising a storage capacity 2 and a transistor 3, for example of the MOS type. The command input of the transistor 3 is connected to a word line receiving a WLREF signal. One of the other two terminals of transistor 3 is connected to a bit line BL and the other is connected to capacity 2, the other terminal of capacity 2 being connected to a circuit ground. We note 4 the common point between the transistor 3 and capacity 2. More generally, it will be understood that the circuit includes a reference cell 1 per bit line BL.

A means of regulating the charging voltage of capacity 2 of the reference cell 1 is provided by the device 5 which includes a capacitor 6, one terminal of which is connected to a ground in the circuit, a transistor 7, for example of the MOS type, one terminal of which is connected to the other terminal of the capacity 6 and the other terminal of which is connected to point 4 of the reference 1. The control input of transistor 7 is connected to a line of words capable of receiving a WLPRECH signal.

The device 5 further comprises a transistor 8, for example of MOS type, mounted in parallel with capacity 6 and whose input command is intended to receive an INIT signal.

The operation of the regulating device 5 and of the memory cell 1 takes place as follows. The role of the reference cell 1 is to maintain a voltage on the bit line BL. By noting V _dd the supply voltage of the circuit, it is possible to provide that the reference cell maintains on the bit line BL a voltage equal to V _dd / 2.

Advantageously, to increase the operational safety of the circuit, provision may be made to maintain a lower voltage, for example equal to V _dd / 3, from which it follows that a voltage lower than V _dd / 3 is considered to be a logic level 0 and that a voltage greater than V _dd / 3 is considered as a logic value 1, the voltage equal to V _dd x 2/3 being the nominal logic level 1. Thus, the voltage present on the bit line BL can weaken from V _dd to V _dd x 2/3 without any major drawback.

The reference cell must therefore be preloaded to a voltage value equal to V _dd / 3 between two line accesses. We denote by C _cell the value of the capacitance 2, C _bl the value of the capacitances of the bit line BL. The operation of the memory is based on a load sharing between the bit line BL and the reference cell 1. The values C _bl and C _cell are known with precision. The bit line BL is preloaded at a voltage between V _dd / 2 and V _dd . Load sharing occurs between the bit line BL and the reference cell 1 which results in a decrease in the voltage on the bit line BL and an increase in the voltage in the reference cell 1 according to the following equation : V _b1f = V _rcf = C _bl / (C _bl + C _cell ) x V _bli + C _cell / (C _cell + C _bl ) x V _rci , with V _b1f the final voltage of the bit line BL, V _rcf the final voltage of the reference cell 1, V _bli the initial voltage of the bit line BL and V _rci the initial voltage of the reference cell 1.

For proper operation, the reference cell 1 must return to the voltage V _rci for the next access, that is to say before the signal WLREF turns on the transistor 3 of the reference cell 1.

Thanks to the regulating device 5, the point 4 forming the second port of the reference cell 1 is connected to the capacitor 6, the value C _{cal of which} is determined with precision and which is the subject of a complete discharge during access . In other words, the transistors 3 and 8 are turned on at substantially the same time while the transistor 7 is blocked. At a time when the transistors 3 and 8 are blocked, the transistor 7 can be turned on to allow load sharing between the capacitors 2 and 6. This load sharing is governed by the following equation: V _rcp = V _rci = C _cell / (C _cell + C _cal ) x V _rcf + C _cal / (C _cell + C _cal ) x 0, with V _rcp the voltage of reference cell 1, i.e. the voltage between the point 4 and the circuit mass after this second charge sharing in other words after the WLPRECH signal has turned transistor 7 on.

From this equation, we deduce that: C _cal = C _cell x (V _rcf - V _rci ) / V _rci . However, all the terms on the right-hand side of this equation are known with precision and we can therefore calculate the value C _cal .

In Figure 2, there is shown a bit line BL _i belonging to a memory comprising a plurality of bit lines. A memory cell 9 has been shown connected to the bit line BL _i and also connected to a word line WL _j . The memory cell 9 comprises a capacitor 10 and a transistor 11, for example of the MOS type, the transistor 11 and the capacitor 10 being arranged in series between the bit line BL _i and a ground of the circuit. The control input of transistor 11 is connected to the word line WLj. On this bit line BL _i to which a plurality of memory cells similar to cell 9 are connected, a reference cell 1 is connected. In other words, a reference cell 1 is provided per bit line BL.

The regulating device 5 is provided according to the same principle as in the previous embodiment but produced slightly differently by sharing a plurality of capacitors 12 and a transistor 13 with other regulating devices intended for other bit lines BL _k , k different from i. In other words, to each reference cell 1 is connected a transistor 7, the control terminal of which is connected to the word line WLPRECH and the other terminal of which is connected to a line 14 to which a plurality of capacitors 12 are connected. the other terminal of which is connected to a circuit ground. The resetting of the capacitors 12 is carried out by means of a transistor 13 connected in parallel. Thus, a single transistor 13 can be used to discharge a plurality of capacitors 12.

This embodiment is interesting in the sense that the value C _cal which it is desired to obtain may turn out to be less than C _cell or even less than 25% of C _cel which is the smallest capacity that can be achieved with precision. suitable. Thus, by pooling a number n of capacities between a number p of reference cells 1, one obtains a capacity of total value equal to nx C _cal but whose charges are distributed towards p reference cells 1 via p transistors 7 so that the charge supplied to a reference cell 1 is equal to the charge that a single capacity of value C _{cal would provide} which is simulated by making available to each reference cell 1 a charge corresponding to a capacity of n / p times the value of a capacity 12. Now, in general, the capacities 12 are of value equal to C _cel since it is the minimum that can be obtained with suitable precision. Thus, a reference cell 1 is made to benefit from a capacity value C _cal = n / px C _cell . In addition, by pooling these capacities 12 between several reference cells, the transistor 13 is also shared, which makes it possible to reduce the number of active components of the circuit.

Furthermore, integrated circuits, in particular memories generally comprise a row of capacitances of value C _cell arranged in line at one end of the circuit and not, as a general rule, playing any particular role. We can therefore use these unused capacities as voltage regulation capacities of the reference cells.

In the case of the embodiment of Figure 2 where the number n of capacity that we need is less than the number p of cells of associated reference 1, we will use n capacities arranged at one end of the circuit and the remaining p - n capacities will be left unused. The fact to use these circuit end capabilities doesn't change so important the manufacturing process. The connection can be made by changing a single mask.

The invention is particularly applicable to integrated circuits whose engraving width is small and for which the generators of tension are difficult to achieve. The invention therefore applies so advantageous for circuits with a width of 0.18 microns, 0.12 microns, 0.09 microns and of future generations with lines of even reduced width. Of more, the consumption of such a means of regulating the voltage of reference cell is extremely weak and in any event lower than those of a voltage generator. In practice, we will use between one fifth and one third of the circuit end capacities. As for example, we can use 27% of these capacities.

Assuming an initial state where all the signals on the word lines are inactive, a memory access is made when the signal WL _j is active. Simultaneously, the WLREF signal is activated to maintain a satisfactory voltage on the bit line BL, and the INIT signal to discharge the capacity 6 of FIG. 1 or the capacities 12 of FIG. 2. After returning to the inactive state of these different signals, the WLPRECH signal is activated which turns transistor 7 on and allows a reduction in the voltage of reference cells 1 by passing charges to capacitor 6 or capacitors 12. After a determined period of time, the WLPRECH signal is reduced to the inactive state.

Claims (12)

Voltage regulation device (5) for reference cell (1) of a dynamic random access memory organized in rows and columns, comprising a plurality of memory cells, characterized in that it comprises at least one capacity (6) of predetermined value capable of being discharged during a memory access. Device according to claim 1, characterized in that the value of said capacity is equal to: C _cell * (V _rcf -V _rci ) / V _rci with C _cell the capacity of the reference cell, V _rcf the voltage of the reference cell after a memory access, and V _rci the voltage of the reference cell before a memory access. Device according to claim 1 or 2, characterized in that it comprises a first switch (7) disposed at the input of said capacity for controlling a charge of said capacity, a load current being able to come from a reference cell . Device according to any one of the preceding claims, characterized in that it comprises a second switch (8) disposed at the outlet of said capacity (6) to control a discharge of said capacity. Device according to any one of the preceding claims, characterized in that it shares at least one capacity (12) with at least one other similar device. Reference cell (1) for dynamic random access memory, characterized in that it comprises a device according to any one of the preceding claims. Cell according to claim 6, characterized in that it comprises a first port able to be connected to a memory cell and a second port connected to the regulation device. Memory, characterized in that it comprises a cell according to any one of claims 6 or 7. Method for regulating the voltage of a reference cell for dynamic random access memory organized in rows and columns, comprising a plurality of memory cells, in which one shares a charge between at least two capacities of predetermined values during a initialization step and one of the two capacities is discharged during a memory access. The method of claim 9, wherein the charge that we share comes from a capacity of a reference cell. Method according to claim 9 or 10, in which use is made one or more existing capacities of an integrated circuit. The method of claim 9, 10 or 11, wherein uses n capacities for the voltage regulation of p reference cells, with n different from p.

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