EP1151386A1 - Microcontroller apparatus for providing network access to a host system - Google Patents

Microcontroller apparatus for providing network access to a host system

Info

Publication number
EP1151386A1
EP1151386A1 EP99939558A EP99939558A EP1151386A1 EP 1151386 A1 EP1151386 A1 EP 1151386A1 EP 99939558 A EP99939558 A EP 99939558A EP 99939558 A EP99939558 A EP 99939558A EP 1151386 A1 EP1151386 A1 EP 1151386A1
Authority
EP
European Patent Office
Prior art keywords
network
host system
control unit
data
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99939558A
Other languages
German (de)
French (fr)
Inventor
Gábor BORJ N
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Flatstack Ltd
Original Assignee
Flatstack Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from HU9900103A external-priority patent/HU9900103D0/en
Priority claimed from HU9901701A external-priority patent/HUP9901701A2/en
Application filed by Flatstack Ltd filed Critical Flatstack Ltd
Publication of EP1151386A1 publication Critical patent/EP1151386A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/02—Protocols based on web technology, e.g. hypertext transfer protocol [HTTP]
    • H04L67/025—Protocols based on web technology, e.g. hypertext transfer protocol [HTTP] for remote control or remote monitoring of applications
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9005—Buffering arrangements using dynamic buffer space allocation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/14—Session management
    • H04L67/142—Managing session states for stateless protocols; Signalling session states; State transitions; Keeping-state mechanisms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/565—Conversion or adaptation of application format or content
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12—Protocol engines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/329—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the application layer [OSI layer 7]

Definitions

  • Microcontroller apparatus for providing network access to a host system
  • the invention relates to a microcontroller apparatus for providing network access to a host system that comprises a peripheral interface coupled to the host system which can be regarded as a peripheral unit, and a network interface coupled to the network towards which said access should be provided.
  • network access and “commumcation” are generally used phrases under which in everyday use Internet access is understood.
  • Internet access will be broadly understood that involves all kinds of network access.
  • Network commumcation In conventional network commumcation solutions the connection is established between computers, and the creation and mamtaining of the communication are ensured by the operational system of the computer that has multi-layered hierarchical structure.
  • Network commumcation is based on standard and fixed conventions applied in a uniform way also in international level. These conventions include a predetermined number of protocols that all have respective functions. The protocols are sequential series of signals that precede the actual transmittal of data.
  • the RFC (Request For Comments_) documents comprise the valid Internet protocols as standards, and they can be found by the route of FTP or Kermit on the place NIC.DDN.MIL, having the address of rfc/rfc####.txt or rfc/rfc####.PS, wherein the designation "####" is the RFC number of the required protocol when the initial zeros are omit ted. As examples in the following addresses the designation "####" means the RFC number of the requested protocol: FTP://NIC.DDN.MIL/rfc/rfc####.txt or FTP://NIC.DDN.MIL/rfc/rfc####.ps.
  • the RFC identifiers of the protocols used in the present specification are:
  • IP protocol 791 and 815 and 1332
  • TCP protocol 793
  • the HTTP protocol is not defined directly in RFC, but it can be accessed at the address: http://www.w3.org and here always the most recent version is available.
  • the object of the invention is to provide a microcontroller apparatus which can satisfy the above defined demand and which can create network access for all electronic devices that have at least a significant state or parameter available through a standard bus connection in digital form.
  • Such electronic devices, towards which network access will be provided, are referred to in the followings as "host systems”.
  • microcontrollers are small,Gmass produced cheap and intelligent devices that can be programmed by microcodes, and in a suitable structural arrangement and programming they can be made to provide a communication between a host system and the network.
  • a microcontroller apparatus that creates a network access to a host system and comprises: -a peripheral interface coupled to the host system;
  • -a storage means coupled to the network interface for storing data associated with traffic to and from the network
  • control unit operated by microcodes, having a memory and coupled to all listed means and being programmed to provide network access for the host system by checking, processing and in case of host system-to-network communication generating standard network protocols in a single layer structure without using any separate operational system.
  • the apparatus according to the invention does not comprise any separate operational system, therefore it can be made with low price and with low power consumption, and it has a small space requirement.
  • the storage means coupled to the network interface comprise input and output buffers, having control lines connected to the control unit, the input buffers are adapted to store data arriving from the network through the network interface, and the output buffers are adapted to store data to be transferred to the network through the network interface.
  • the data stored in the input buffers are sequentially processed including the checking of protocols comprised in the received data and carrying out decisions required for establishing the communication, provided the conditions therefor are met.
  • the control unit examines whether sufficient free capacity is available, and the connection is allowed only if such available capacity is found.
  • HTTP protocol includes the examination of "GET” and "POST" commands. If “GET” command is found, the previously obtained information is read in the output buffers, and if "POST" command is found, the received information is stored for the host system.
  • microprogramming of the control unit by microcodes comprises the generation of standard Internet protocols, and in case of information transmittal towards the network, the generated Internet protocols are added to this information.
  • the microcontroller apparatus according to the invention can be used in all fields of technique, since the host system can be constituted by devices for measuring physical parameters (e.g. temperature, speed, pressure) as well as by individual security systems, heating equipment or by automated industrial process control equipment.
  • the wide range of applicability justifies mass production which can be the source of a further substantial cost reduction.
  • Fig. 1 shows the schematic structural design of the microcontroller apparatus according to the invention
  • Fig. 2 is a flow chart showing the general operation of the apparatus
  • Fig. 3 is a flow chart showing the processing of the signals of the input buffer
  • Fig. 4 is a flow chart showing how a new connection is built up
  • Fig. 5 is a flow chart showing the processing of HTTP commands
  • Fig. 6 is a flow chart showing the processing of the signals of the output buffer.
  • the main task of the apparatus according to the invention lies in to provide a bi-directional network access e.g. Internet or Intranet access to a host system.
  • the units shown in Fig. 1 are connected between bi-directional bus lines coupled to the host system and to the Internet, respectively.
  • the maun unit of the apparatus is constituted by control unit 1 made of a microcontroller that has an own memory having a predetermined storage capacity and which is capable of storing microcodes. This storage capacity is substantially smaller than the capacity of generally used personal computers, and it is typically below 16 Kbytes.
  • the control unit 1 is coupled with all other units of the apparatus, and the operation thereof is controlled by commands written in microcodes.
  • the tasks of the control unit 1 include the control of network communication, the servicing of the interface of the host system, the coordination of the data transfer and connections between peripheral registers, and the accomplishment of the requests arriving from the network. From certain points of view the apparatus can also be regarded as a periphery of the host system, since the apparatus receives the data of the host system and stores them into registers.
  • the processing of the requests obtained from the network takes place by the recognition and use of appropriate protocols. By using the same protocols and by applying specific operations the control unit 1 is capable of forwarding infoLmation stored in the registers towards the network.
  • Network communication does not require a continuous and active operation of the apparatus, and for the sake of decreasing power consumption, the apparatus is automatically switched to standby mode in all inactive periods.
  • the control unit 1 supports the standby mode and generates the required control signals if the conditions for that mode are all met. It should be noted, that in the apparatus the control unit 1 has the highest power consumption.
  • the control unit 1 is associated with the microcode routines it uses. These routines are operational program routines that assist in the appropriate and consequent handling of the network protocols and of the peripheral and network interfaces. From the aspect of the actual circuit implementation it has not significance what parts or units have been built in the microcontroller and what parts were made as separate circuits. In case of designs having a higher degree of integration, the physical dimensions and the power consumption are decreased, and the price will also be smaller. Naturally, the best implementation will be if the whole apparatus is made as a single integrated unit. The range of operations that can be performed by the apparatus is not influenced by the extent of integration. For the sake of future enhancements, it is advisable to provide the apparatus with a certain amount of excess memory and processing capacity.
  • a significant part of the apparatus is constituted by its protocol interpretation capability, which is entirely different from the ways how commumcation is provided in conventional computer networks, and this function can be regarded as an independent protocol manager which is indispensable for performing the required functional tasks.
  • the apparatus according to the invention cannot be regarded as any of the generally used systems providing communication, and it does not use any general purpose computer either, thus there is no need for using a multi-layered system to provide communication with the network.
  • the whole system has become much simpler by the use of a single protocol interpreter.
  • control unit 1 is coupled to a real time clock 2 for providing time and date data required for the operation.
  • a quartz controlled clock 2 is preferable that supplies the time data with sufficient accuracy.
  • the time data are defined in a format of hour/minute/second and the date as year/month/day.
  • the apparatus comprises registers 3 which are the most important devices in the communication between the apparatus and the host system.
  • the information is transferred by the host system through the registers 3, and this is the information which will later be forwarded towards the network.
  • the registers 3 have important role in forwarding information from the network towards the host system.
  • the registers 3 are constituted by memory circuits, and the control unit and all buses of the apparatus have access to the information stored in the registers 3.
  • Input buffers 4 are used to store incoming data from the network.
  • the control unit 1 can directly interpret and process these data.
  • the input buffers 4 are memory circuits, into which data arriving from the network through network interface 7 are directly stored. During operations performed on these data the control unit 1 can write further data in the input buffers 4, and it can also change the order of the data.
  • Output buffers 5 are further elements of the apparatus that provide network communication. The storage of data that should be transferred through the network occurs here, and this is the memory area where the control unit 1 collects information characteristic to the protocols.
  • the output buffers 5 are made also of memory circuits, and the control of the data transfer is provided by the control unit 1. The content of the output buffers 5 will be transferred directly towards the network.
  • the control unit 1 is associated with an NV RAM controller 6 performing the task of protecting the stored data in case of any failure in power supply. It continuously monitors the power supply and if its value decreases below a critical limit value, the data will be retained e.g. by providing a memory protection, and this guarantees the safe operation of the apparatus. The normal operation is allowed to commence only if the supply voltage returns to the normal range.
  • the NV RAM controller 6 has an internal power supply, and it comprises an intelligent logic circuit that prevents any false memory control if the supply voltage fluctuates.
  • the apparatus according to the invention is coupled to the network by means of the network interface 7, the task of which is to provide all electronic and logical parameters required for the apparatus to appear, when seen from the network, as a normal station.
  • the network interface 7 alone is capable of coordinating the data traffic on the network, it can receive information from the network and write this information into the input buffer 4.
  • the network interface 7 transfers the information stored in the output buffer 5 automatically to the network. It performs timing functions in accordance with the requirements of the associated network, and monitors the status of the apparatus. It transmits information to the control unit 1 on the status of the network, and in response to instructions of the control unit 1 it transfers status information to the network.
  • the network interface 7 is a per se known, conventional unit, and it can be e.g. an RS 232 or Ethernet type network interface.
  • peripheral interface 8 is to provide a standard bus connection between the apparatus and the host system.
  • This unit can be made e.g. by the IIC bus of the Philips company or by the SPI bus of Motorola Inc. or by any other standard bus connection.
  • the apparatus can be used both in bus master and slave modes, whereby the circuit designer can utilize a wider range of possibilities.
  • bus master mode as a result of the connection provided through the peripheral bus 8, the apparatus automatically receives the data arriving from the host system. This function can be used if owing to any reason the host system is not capable of performing even the lowest level commumcation with the apparatus.
  • bus slave mode the apparatus fulfills the task of being the periphery of the host system, thus the host system can both receive and send data from and to the network.
  • the flow chart of Fig. 2 shows the main functional units of the operation of the apparatus.
  • the capital letters shown on the flow charts designate associated operational stages that create logical connections between the different flow charts.
  • the apparatus performs a check function, and the first inspected unit is the network interface 7.
  • the control unit 1 examines whether during the standby state preceding the issue of the start command there has been any failure in the network that might influence normal operation. If such a fail is detected, the network interface will be controlled to an initial base state.
  • the second check stage is the inspection of the peripheral interface 8.
  • the control unit 1 checks the registers in the peripheral interface and determines whether the controller of the IIC bus operates properly. In case of detecting any failure, the control unit 1 will bring the peripheral interface 8 into an initial state.
  • the microcode integrity is inspected, wherein the control unit 1 calculates the control sum for the microcode integrity. If any discrepancy is found between the stored and calculated values, the operation is stopped and a failure signal is provided.
  • the control unit 1 determines only whether any of the input buffers comprises information waiting for being processed. If such information is found, then the processing of the input information stage will be started, and this is illustrated in Fig. 3. This is associated with status X. If such information to be processed is not found, the next step is the inspection of the status of the output buffers 5. This inspection will start after the functions shown in Fig. 3 are performed, and this can be seen from the status Z shown both on Figs. 2 and 3.
  • the control unit 1 examines the status of the registers indicating the status of the output buffers 5 and establishes which one of the output buffers 5 comprises information to be forwarded. If such information exists, the process shown in Fig. 6 and designated by the status W is started. If the control unit 1 has not found such data, it controls the apparatus into standby mode. The condition of sending the apparatus to standby mode can be met during the performance of the other stages as well, and this condition is designated by the status V. The process will start again if the status of the network becomes active, since the control unit 1 is capable of inspecting the activity of the network even in standby mode, and the experiencing of such an activity will thus trigger a next cycle.
  • the packet can be divided into two main parts, the first is the header of the protocols and the second is the data carried by the packet.
  • the headers consist of several distinct parts, which are:
  • the decision and operation processes in Fig. 3 have been designated by letters of the alphabet in lower case.
  • the first step a of the process is an examination that deterniines whether the signal sequence comprises a PPP protocol header.
  • the examination lies in whether the value of the first byte (Table 1, row 1, first byte) is cO or not. If the value is not cO, the process will be terminated and the state Z is generated. If the expected value is found, the next step is the checking of the PPP packet (step b) and its storage (step c). During the checking step the only examination is whether the header of the PPP packet comprises information after the 21st bit. If such information exists, it will be stored in the active memory of the control unit 1.
  • the decision d it is examined whether the header of an IP protocol comes next. In this decision the existence of the value 21 is examined in the previous header. If this is found, the next data belong to the header of an IP protocol, and the processing operation is continued by operation e. Otherwise the process is finished again (state Z).
  • the examination of the IP protocol requires the knowledge of the header of the IP protocol. The first four bits designate the number of the version. Currently the version 4 is used, and the shown embodiment is capable of processing signals having such a version only.
  • the header of the IP protocol is checked, wherein first the field "time to live" is examined. If the value of this field is 0, the process is stopped, and if this value is different from 0, the control sum of the IP protocol header will be examined.
  • This value should be the one's-complement of the sum of the one's-complement of the bytes in the header of the IP protocol.
  • the decision f examines whether the destination address given in the header of the IP protocol is the same as the Internet address assigned to the apparatus according to the invention. In case of yes, the checking of the header of the TCP protocol is carried out in the step g. This examination relates to the control sum in the header of the TCP protocol.
  • the control sum is the result of the sum of the values of the bytes starting from the beginning of the TCP protocol header till the end of the whole length of the packet.
  • the storage of the parameters of the TCP protocol is carried of in step h.
  • the TCP protocol includes the address of the source port, which is 16 bits long, the address of the destination port, which is also that long, and these addresses serve for the identification of the connection between the two parties.
  • the address of the port of the sender is 6843
  • the value of the destination port is " I”.
  • the "sequence number” is a 32 bits long number, which is the serial number of the first byte of the data in the data packet in a continuously increasing order.
  • the six bits in the TCP protocol just after the field "reserved" have outstanding significance, of them the bit SYN is 1 if the protocol refers to a new connection, and its value is 0 if an old connection is continued. The examination of this bit occurs during he operation i. In case of a new connection the state U is generated, and the establishment of a new connection is shown in Fig. 4.
  • the step j is started which is not else than the decision on the basis of the header of the TCP protocol that the next information will be a HTTP protocol header.
  • the yes response generates the state T shown in Fig. 5, and in case of a no response the processing is continued by the state Z.
  • the processing of the incoming information is continued by the process shown in Fig. 5, wherein the first decision is the arrival of the expected "GET" word in the HTTP protocol.
  • This command means the request of the remote party.
  • the primary task of the apparatus according to the invention is to carry out the incoming HTTP requests.
  • the simplest request consists of the key word GET, a space and the identifier of the requested information.
  • the requested information is preferably the address of a file that can be found in the memory of the control unit 1. In the exemplary case this address is: A.HTML.
  • the symbols "CR” and "LF" are the signals of the carriage return and line feed commands and they have no other function.
  • the exemplary address reads the content of the stored file from the control unit 1, which is e.g. the signal of a remote temperature sensor, or it can be several data representing the status of the host system.
  • the control unit 1 fills these data into the output buffers 5 and adds to these data a standard response header generated from the stored data of the incoming protocol headers. This operation can be carried out in the knowledge of the Internet standards by means of routine microprogramming work.
  • the transmittal of the data will be triggered by the state W shown in Fig. 2, since the operations described there comprise the examination of the content of the output buffers 5.
  • the control unit 1 As soon as data are found in the output buffers 5, the control unit 1 generates according to the order of Fig. 6 the outgoing protocol headers of the packet to be transmitted, stores them in the output buffers 5, then forwards them towards the network. If the result of the examination for the GET command was negative, the control unit searches in the HTTP protocol for a POST command.
  • the founding of such a command means that information has been received from the network, and as a result of this, the control unit 1 transmits the data corresponding to the received information to the host system.
  • the exemplary embodiment of the apparatus according to the invention is inappropriate to process incoming commands other than GET and POST, however, based on the disclosed information numerous other functions can be realized, but all of these additional functions require the use of associated hardware and software elements and appropriate microprograms.
  • the connection was new. If this is the case, the state U is generated, and the process illustrated in Fig. 4 is started.
  • the first decision is based on the examination whether there is sufficient available hardware capacity for processing the received packet.
  • the apparatus according to the invention has a predetermined amount of hardware units and processing capacity, and it cannot establish more simultaneous connections than determined by its finite capacity. In the simplest embodiment this number can be as few as 1, and the examination will be not else than a simple examination for engagement. If there is no sufficient available capacity found, the establishment of the new connection will be denied, and the control unit 1 generates an appropriate response.
  • control unit 1 will prepare for creating such a connection, that is the generation of an appropriate response towards the sender.
  • the control unit 1 also examines whether data have arrived after the HTTP protocol in the incoming packet. The establishment of a connection will have sense only if data have arrived (Y branch), and the processing will be directed to step j of Fig.3.
  • the apparatus according to the invention is capable of providing a full value bi-directional Internet access for the host system without using a computer system utilizing an operational system.
  • the described way of operation of the control unit 1 does not require higher processing capacity than expected from usual microcontrollers.
  • the apparatus according to the invention can be regarded as a general purpose device, since its applicability is unlimited.
  • the host system can be security systems, telemechanical devices, process control equipment, household and industrial devices, wherein their control and the reading of the status information can occur through a standard bus line.
  • the apparatus according to the invention worth being built in a single chip, and in case of a suitable high production number the price can be sufficiently low not to render a cost bar for the possible wide range of applications.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
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Abstract

Microcontroller apparatus for providing network access to a host system, comprising: a peripheral interface (8) coupled to the host system; a network interface (7) coupled to a network towards which the access should be provided; a storage means (4, 5) coupled to the network interface (7) for storing data associated with traffic to and from the network; and a control unit (1) operated by microcodes and having a memory, the control unit is coupled to all listed means and it is programmed to provide network access for the host system by checking, processing and in case of host system-to-network communication generating standard network protocols in a single layer structure without using any separate operational system.

Description

Microcontroller apparatus for providing network access to a host system
Field of the invention
The invention relates to a microcontroller apparatus for providing network access to a host system that comprises a peripheral interface coupled to the host system which can be regarded as a peripheral unit, and a network interface coupled to the network towards which said access should be provided.
Description of the prior art
With the rapid increase of the range of Internet applications one direction of development of electronic industry, especially of computer industry is constituted by enhancing communication that includes involvement of devices having different types and purposes, and by the creation of network access for such devices. The terms "network access" and "commumcation" are generally used phrases under which in everyday use Internet access is understood. In the present specification the term Internet access will be broadly understood that involves all kinds of network access.
In conventional network commumcation solutions the connection is established between computers, and the creation and mamtaining of the communication are ensured by the operational system of the computer that has multi-layered hierarchical structure. Network commumcation is based on standard and fixed conventions applied in a uniform way also in international level. These conventions include a predetermined number of protocols that all have respective functions. The protocols are sequential series of signals that precede the actual transmittal of data.
The detailed definition and description of these protocols constitute public and available information. The RFC (Request For Comments_) documents comprise the valid Internet protocols as standards, and they can be found by the route of FTP or Kermit on the place NIC.DDN.MIL, having the address of rfc/rfc####.txt or rfc/rfc####.PS, wherein the designation "####" is the RFC number of the required protocol when the initial zeros are omit ted. As examples in the following addresses the designation "####" means the RFC number of the requested protocol: FTP://NIC.DDN.MIL/rfc/rfc####.txt or FTP://NIC.DDN.MIL/rfc/rfc####.ps. The RFC identifiers of the protocols used in the present specification are:
PPP protocol: 1661 and 1570 and 1334,
IP protocol: 791 and 815 and 1332,
TCP protocol: 793 The HTTP protocol is not defined directly in RFC, but it can be accessed at the address: http://www.w3.org and here always the most recent version is available.
In view of the fact that such communication requires the presence of a computer hierarchy at both ends, the available conditions and conventions have not made possible for electronic devices not equipped with a computer-based operational system to be participants of any direct network communication.
In a very wide field of technique there are electronic devices in use, wherein the knowledge of their momentary states, or their control or regulation might be required through the network, e.g. for the purpose of telemetry, telecontrol or process control. The demand is very high, and up to the present this could be satisfied only by providing a separate computer for perforating this task. In most of the practical applications the use of a separate computer structure has been impossible owing to price limitations or to the limited availability of space, energy or protection against weather.
Object of the invention
The object of the invention is to provide a microcontroller apparatus which can satisfy the above defined demand and which can create network access for all electronic devices that have at least a significant state or parameter available through a standard bus connection in digital form. Such electronic devices, towards which network access will be provided, are referred to in the followings as "host systems".
Summary of the invention
To achieve this object it has been recognized that microcontrollers are small,Gmass produced cheap and intelligent devices that can be programmed by microcodes, and in a suitable structural arrangement and programming they can be made to provide a communication between a host system and the network.
According to the invention a microcontroller apparatus has been provided that creates a network access to a host system and comprises: -a peripheral interface coupled to the host system;
-a network interface coupled to a network towards which the access should be provided;
-a storage means coupled to the network interface for storing data associated with traffic to and from the network; and
- a control unit operated by microcodes, having a memory and coupled to all listed means and being programmed to provide network access for the host system by checking, processing and in case of host system-to-network communication generating standard network protocols in a single layer structure without using any separate operational system.
In this way the apparatus according to the invention does not comprise any separate operational system, therefore it can be made with low price and with low power consumption, and it has a small space requirement.
In a preferable embodiment the storage means coupled to the network interface comprise input and output buffers, having control lines connected to the control unit, the input buffers are adapted to store data arriving from the network through the network interface, and the output buffers are adapted to store data to be transferred to the network through the network interface. In a further embodiment the data stored in the input buffers are sequentially processed including the checking of protocols comprised in the received data and carrying out decisions required for establishing the communication, provided the conditions therefor are met. In the apparatus prior to the establishment of a new network connection the control unit examines whether sufficient free capacity is available, and the connection is allowed only if such available capacity is found.
During the sequential processing of the input data the examination of the
HTTP protocol includes the examination of "GET" and "POST" commands. If "GET" command is found, the previously obtained information is read in the output buffers, and if "POST" command is found, the received information is stored for the host system.
In a further embodiment the microprogramming of the control unit by microcodes comprises the generation of standard Internet protocols, and in case of information transmittal towards the network, the generated Internet protocols are added to this information.
The microcontroller apparatus according to the invention can be used in all fields of technique, since the host system can be constituted by devices for measuring physical parameters (e.g. temperature, speed, pressure) as well as by individual security systems, heating equipment or by automated industrial process control equipment. The wide range of applicability justifies mass production which can be the source of a further substantial cost reduction.
The provision of a simple network access for host systems has created thereby an unlimited wide range of applications.
Brief description of the drawings
The structural design and operation of the microcontroller apparatus according to the invention will now be described, wherein reference will be made to the accompanying drawings. In the drawing: Fig. 1 shows the schematic structural design of the microcontroller apparatus according to the invention; Fig. 2 is a flow chart showing the general operation of the apparatus; Fig. 3 is a flow chart showing the processing of the signals of the input buffer; Fig. 4 is a flow chart showing how a new connection is built up; Fig. 5 is a flow chart showing the processing of HTTP commands; and Fig. 6 is a flow chart showing the processing of the signals of the output buffer.
Description of the preferred embodiments
The main task of the apparatus according to the invention lies in to provide a bi-directional network access e.g. Internet or Intranet access to a host system. The units shown in Fig. 1 are connected between bi-directional bus lines coupled to the host system and to the Internet, respectively.
The maun unit of the apparatus is constituted by control unit 1 made of a microcontroller that has an own memory having a predetermined storage capacity and which is capable of storing microcodes. This storage capacity is substantially smaller than the capacity of generally used personal computers, and it is typically below 16 Kbytes. The control unit 1 is coupled with all other units of the apparatus, and the operation thereof is controlled by commands written in microcodes. The tasks of the control unit 1 include the control of network communication, the servicing of the interface of the host system, the coordination of the data transfer and connections between peripheral registers, and the accomplishment of the requests arriving from the network. From certain points of view the apparatus can also be regarded as a periphery of the host system, since the apparatus receives the data of the host system and stores them into registers. The processing of the requests obtained from the network takes place by the recognition and use of appropriate protocols. By using the same protocols and by applying specific operations the control unit 1 is capable of forwarding infoLmation stored in the registers towards the network.
Network communication does not require a continuous and active operation of the apparatus, and for the sake of decreasing power consumption, the apparatus is automatically switched to standby mode in all inactive periods. The control unit 1 supports the standby mode and generates the required control signals if the conditions for that mode are all met. It should be noted, that in the apparatus the control unit 1 has the highest power consumption.
The control unit 1 is associated with the microcode routines it uses. These routines are operational program routines that assist in the appropriate and consequent handling of the network protocols and of the peripheral and network interfaces. From the aspect of the actual circuit implementation it has not significance what parts or units have been built in the microcontroller and what parts were made as separate circuits. In case of designs having a higher degree of integration, the physical dimensions and the power consumption are decreased, and the price will also be smaller. Naturally, the best implementation will be if the whole apparatus is made as a single integrated unit. The range of operations that can be performed by the apparatus is not influenced by the extent of integration. For the sake of future enhancements, it is advisable to provide the apparatus with a certain amount of excess memory and processing capacity.
A significant part of the apparatus is constituted by its protocol interpretation capability, which is entirely different from the ways how commumcation is provided in conventional computer networks, and this function can be regarded as an independent protocol manager which is indispensable for performing the required functional tasks.
Conventional communication protocols use mainly functions provided by the operational system. In the apparatus according to the invention there is no separate operational system, thus it does not use the conventional ways of communication based on the operational system. The protocol interpreter is used to perform this task, since in addition to transferring the information associated with the protocols it also evaluates and interprets the information included in the protocol headers. Since in computer communication each protocol is comprised in superimposed hierarchical layers, the information forwarded by the protocol headers is arranged in a sequential order in all forwarded data package. The protocol interpreter utilizes the fact that all parameters of any given information is included in this data package. By this way there will be no need for the hierarchical processing, and there will be no need for a substantial amount of processing and storage capacity. When network protocols were designed, the primary objective was to enable communication between computers having differing architectural designs, thus the modular design and the hierarchical structure was made.
The apparatus according to the invention cannot be regarded as any of the generally used systems providing communication, and it does not use any general purpose computer either, thus there is no need for using a multi-layered system to provide communication with the network. The whole system has become much simpler by the use of a single protocol interpreter.
Returning to the preferable embodiment shown, the control unit 1 is coupled to a real time clock 2 for providing time and date data required for the operation. The use of a quartz controlled clock 2 is preferable that supplies the time data with sufficient accuracy. The time data are defined in a format of hour/minute/second and the date as year/month/day.
The apparatus comprises registers 3 which are the most important devices in the communication between the apparatus and the host system. The information is transferred by the host system through the registers 3, and this is the information which will later be forwarded towards the network. The registers 3 have important role in forwarding information from the network towards the host system. The registers 3 are constituted by memory circuits, and the control unit and all buses of the apparatus have access to the information stored in the registers 3.
Input buffers 4 are used to store incoming data from the network. The control unit 1 can directly interpret and process these data. The input buffers 4 are memory circuits, into which data arriving from the network through network interface 7 are directly stored. During operations performed on these data the control unit 1 can write further data in the input buffers 4, and it can also change the order of the data.
Output buffers 5 are further elements of the apparatus that provide network communication. The storage of data that should be transferred through the network occurs here, and this is the memory area where the control unit 1 collects information characteristic to the protocols. The output buffers 5 are made also of memory circuits, and the control of the data transfer is provided by the control unit 1. The content of the output buffers 5 will be transferred directly towards the network.
The control unit 1 is associated with an NV RAM controller 6 performing the task of protecting the stored data in case of any failure in power supply. It continuously monitors the power supply and if its value decreases below a critical limit value, the data will be retained e.g. by providing a memory protection, and this guarantees the safe operation of the apparatus. The normal operation is allowed to commence only if the supply voltage returns to the normal range. The NV RAM controller 6 has an internal power supply, and it comprises an intelligent logic circuit that prevents any false memory control if the supply voltage fluctuates. The apparatus according to the invention is coupled to the network by means of the network interface 7, the task of which is to provide all electronic and logical parameters required for the apparatus to appear, when seen from the network, as a normal station. The network interface 7 alone is capable of coordinating the data traffic on the network, it can receive information from the network and write this information into the input buffer 4. The network interface 7 transfers the information stored in the output buffer 5 automatically to the network. It performs timing functions in accordance with the requirements of the associated network, and monitors the status of the apparatus. It transmits information to the control unit 1 on the status of the network, and in response to instructions of the control unit 1 it transfers status information to the network. The network interface 7 is a per se known, conventional unit, and it can be e.g. an RS 232 or Ethernet type network interface.
The task of peripheral interface 8 is to provide a standard bus connection between the apparatus and the host system. This unit can be made e.g. by the IIC bus of the Philips company or by the SPI bus of Motorola Inc. or by any other standard bus connection. The apparatus can be used both in bus master and slave modes, whereby the circuit designer can utilize a wider range of possibilities. In bus master mode, as a result of the connection provided through the peripheral bus 8, the apparatus automatically receives the data arriving from the host system. This function can be used if owing to any reason the host system is not capable of performing even the lowest level commumcation with the apparatus. In bus slave mode the apparatus fulfills the task of being the periphery of the host system, thus the host system can both receive and send data from and to the network.
The operation of the apparatus according to the invention will now be described in connection with the flow charts of Figs. 2 to 5 and with an example showing how a request command arriving from the network and directed to the status data of the host system will be processed.
The flow chart of Fig. 2 shows the main functional units of the operation of the apparatus. The capital letters shown on the flow charts designate associated operational stages that create logical connections between the different flow charts. Following a start command the apparatus performs a check function, and the first inspected unit is the network interface 7. The control unit 1 examines whether during the standby state preceding the issue of the start command there has been any failure in the network that might influence normal operation. If such a fail is detected, the network interface will be controlled to an initial base state.
The second check stage is the inspection of the peripheral interface 8. The control unit 1 checks the registers in the peripheral interface and determines whether the controller of the IIC bus operates properly. In case of detecting any failure, the control unit 1 will bring the peripheral interface 8 into an initial state. In the third check stage the microcode integrity is inspected, wherein the control unit 1 calculates the control sum for the microcode integrity. If any discrepancy is found between the stored and calculated values, the operation is stopped and a failure signal is provided. During the checking of the input buffers 4 the control unit 1 determines only whether any of the input buffers comprises information waiting for being processed. If such information is found, then the processing of the input information stage will be started, and this is illustrated in Fig. 3. This is associated with status X. If such information to be processed is not found, the next step is the inspection of the status of the output buffers 5. This inspection will start after the functions shown in Fig. 3 are performed, and this can be seen from the status Z shown both on Figs. 2 and 3.
The control unit 1 examines the status of the registers indicating the status of the output buffers 5 and establishes which one of the output buffers 5 comprises information to be forwarded. If such information exists, the process shown in Fig. 6 and designated by the status W is started. If the control unit 1 has not found such data, it controls the apparatus into standby mode. The condition of sending the apparatus to standby mode can be met during the performance of the other stages as well, and this condition is designated by the status V. The process will start again if the status of the network becomes active, since the control unit 1 is capable of inspecting the activity of the network even in standby mode, and the experiencing of such an activity will thus trigger a next cycle.
From the point of view of the operation of the apparatus according to the invention the processing of the content of the input buffers 4 has outstanding significance. The information coming from the network will be written through the network interface 7 directly in the input buffers 4. The processing of the received information is shown in Fig. 3. For the clear understanding of this process, the way of processing the signal sequence shown in Table 1 will be explained. The data of Table 1 show exactly the content of the input buffers 4. The stored data represent a standard TCP/IP packet used in Internet traffic. The columns of the table indicate the places of the bits of the sequentially arriving information, and each row corresponds to 4 bytes i.e. 32 bits. The contents of the respective rows follow each other in a sequential order. Since the detailed description of the signal sequences used in Internet traffic cannot be the objective of the present specification, in the following only those portions of such signals will be described, which are thought to be required for understanding the present invention. Table 1
0 1 2 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
I OxCO I 0x21 I I Version I IHL I Type of Service | Total Length |
+-+-+-+-+-4—+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-4--+-+ I Identification | Flags | Fragment Offset |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ I Time to Live | Protocol | Header Checksum | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ ! Source Address I
4—+-+-+-+-+-+-4—+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ I Destination Address I I Options I Padding |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ I Source Port | Destination Port |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ I Sequence Number I +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ I Acknowledgment Number I
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ I Data I |U|A| P I R| S | F| I
I Offsetl Reserved |R|C| S | S| Y| I | Window I I I |G|K|H|T|N|N| I
I Checksum I Urgent Pointer I
I Options i 0 I
I G E T I
I A . H T I
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-4--+-+-+-+-+-+-+-+-+-+-+-+-+ I M L CR' λLF' I
+-+-+-4—+-+-+-+-+-+-+-+-+-4—+-+-+-+-4—+-+-4—+-+-+-+-4—4—4--+-+-+-+
The packet can be divided into two main parts, the first is the header of the protocols and the second is the data carried by the packet. The headers consist of several distinct parts, which are:
- PPP protocol header (the first row in Table 1);
- IP protocol header (rows 2-7 in Table 1);
- TCP protocol header (row 14 in Table 1); - HTTP REQUEST data (rows 15 and 16 in Table 1).
The decision and operation processes in Fig. 3 have been designated by letters of the alphabet in lower case. The first step a of the process is an examination that deterniines whether the signal sequence comprises a PPP protocol header. The examination lies in whether the value of the first byte (Table 1, row 1, first byte) is cO or not. If the value is not cO, the process will be terminated and the state Z is generated. If the expected value is found, the next step is the checking of the PPP packet (step b) and its storage (step c). During the checking step the only examination is whether the header of the PPP packet comprises information after the 21st bit. If such information exists, it will be stored in the active memory of the control unit 1.
During the decision d it is examined whether the header of an IP protocol comes next. In this decision the existence of the value 21 is examined in the previous header. If this is found, the next data belong to the header of an IP protocol, and the processing operation is continued by operation e. Otherwise the process is finished again (state Z). The examination of the IP protocol requires the knowledge of the header of the IP protocol. The first four bits designate the number of the version. Currently the version 4 is used, and the shown embodiment is capable of processing signals having such a version only. During the operation step e the header of the IP protocol is checked, wherein first the field "time to live" is examined. If the value of this field is 0, the process is stopped, and if this value is different from 0, the control sum of the IP protocol header will be examined. This value should be the one's-complement of the sum of the one's-complement of the bytes in the header of the IP protocol. The decision f examines whether the destination address given in the header of the IP protocol is the same as the Internet address assigned to the apparatus according to the invention. In case of yes, the checking of the header of the TCP protocol is carried out in the step g. This examination relates to the control sum in the header of the TCP protocol. The control sum is the result of the sum of the values of the bytes starting from the beginning of the TCP protocol header till the end of the whole length of the packet. The storage of the parameters of the TCP protocol is carried of in step h. Of the various parameters of the TCP protocol it is noted that it includes the address of the source port, which is 16 bits long, the address of the destination port, which is also that long, and these addresses serve for the identification of the connection between the two parties. In the exemplary case the address of the port of the sender is 6843, the value of the destination port is " I". The "sequence number" is a 32 bits long number, which is the serial number of the first byte of the data in the data packet in a continuously increasing order. The six bits in the TCP protocol just after the field "reserved" have outstanding significance, of them the bit SYN is 1 if the protocol refers to a new connection, and its value is 0 if an old connection is continued. The examination of this bit occurs during he operation i. In case of a new connection the state U is generated, and the establishment of a new connection is shown in Fig. 4.
In case if the connection has already been established earlier, the step j is started which is not else than the decision on the basis of the header of the TCP protocol that the next information will be a HTTP protocol header. Here the yes response generates the state T shown in Fig. 5, and in case of a no response the processing is continued by the state Z.
The processing of the incoming information is continued by the process shown in Fig. 5, wherein the first decision is the arrival of the expected "GET" word in the HTTP protocol. This command means the request of the remote party. The primary task of the apparatus according to the invention is to carry out the incoming HTTP requests. The simplest request consists of the key word GET, a space and the identifier of the requested information. The requested information is preferably the address of a file that can be found in the memory of the control unit 1. In the exemplary case this address is: A.HTML. The symbols "CR" and "LF" are the signals of the carriage return and line feed commands and they have no other function.
Returning to Fig. 5 following the identification of the command GET the exemplary address reads the content of the stored file from the control unit 1, which is e.g. the signal of a remote temperature sensor, or it can be several data representing the status of the host system. The control unit 1 fills these data into the output buffers 5 and adds to these data a standard response header generated from the stored data of the incoming protocol headers. This operation can be carried out in the knowledge of the Internet standards by means of routine microprogramming work.
The transmittal of the data will be triggered by the state W shown in Fig. 2, since the operations described there comprise the examination of the content of the output buffers 5. As soon as data are found in the output buffers 5, the control unit 1 generates according to the order of Fig. 6 the outgoing protocol headers of the packet to be transmitted, stores them in the output buffers 5, then forwards them towards the network. If the result of the examination for the GET command was negative, the control unit searches in the HTTP protocol for a POST command. The founding of such a command means that information has been received from the network, and as a result of this, the control unit 1 transmits the data corresponding to the received information to the host system. The exemplary embodiment of the apparatus according to the invention is inappropriate to process incoming commands other than GET and POST, however, based on the disclosed information numerous other functions can be realized, but all of these additional functions require the use of associated hardware and software elements and appropriate microprograms.
In the operation i of Fig. 3 it was examined whether the connection was new. If this is the case, the state U is generated, and the process illustrated in Fig. 4 is started. The first decision is based on the examination whether there is sufficient available hardware capacity for processing the received packet. The apparatus according to the invention has a predetermined amount of hardware units and processing capacity, and it cannot establish more simultaneous connections than determined by its finite capacity. In the simplest embodiment this number can be as few as 1, and the examination will be not else than a simple examination for engagement. If there is no sufficient available capacity found, the establishment of the new connection will be denied, and the control unit 1 generates an appropriate response.
If the new connection can be made, the control unit 1 will prepare for creating such a connection, that is the generation of an appropriate response towards the sender. The control unit 1 also examines whether data have arrived after the HTTP protocol in the incoming packet. The establishment of a connection will have sense only if data have arrived (Y branch), and the processing will be directed to step j of Fig.3.
Based on the above example it can be seen that the apparatus according to the invention is capable of providing a full value bi-directional Internet access for the host system without using a computer system utilizing an operational system. The described way of operation of the control unit 1 does not require higher processing capacity than expected from usual microcontrollers.
In the described configuration the apparatus according to the invention can be regarded as a general purpose device, since its applicability is unlimited. The host system can be security systems, telemechanical devices, process control equipment, household and industrial devices, wherein their control and the reading of the status information can occur through a standard bus line.
Owing to the high degree of universality the apparatus according to the invention worth being built in a single chip, and in case of a suitable high production number the price can be sufficiently low not to render a cost bar for the possible wide range of applications.

Claims

Claims:
1. Microcontroller apparatus for providing network access to a host system, comprising: -a peripheral interface (8) coupled to the host system;
-a network interface (7) coupled to a network towards which said access should be provided; -a storage means (4, 5) coupled to the network interface (7) for storing data associated with traffic to and from the network; and - a control unit (1) operated by microcodes and having a memory, said unit being coupled to all listed means and being programmed to provide network access for the host system by checking, processing and in case of host system-to-network communication generating standard network protocols in a single layer structure without using any separate operational system.
2. The microcontroller apparatus as claimed in claim 1, wherein said storage means coupled to the network interface (7) comprising input buffers (4) and output buffers (5), having control lines connected to the control unit (1), said input buffers (4) being adapted to store data arriving from the network through the network interface (7), said output buffers (5) being adapted to store data to be transferred to the network through the network interface (7).
3. The microcontroller apparatus as claimed in claim 1, wherein the data stored in the input buffers (4) being sequentially processed including the checking of protocols comprised in the received data and carrying out decisions required for establishing the communication provided the conditions therefor are met.
4. The microcontroller apparatus as claimed in claim 1, wherein prior to the establishment of a new network connection said control unit (1) examines whether sufficient free capacity is available, and the connection is allowed only if such available capacity is found.
5. The microcontroller apparatus as claimed in claim 3, wherein during the sequential processing of the input data the examination of the HTTP protocol includes the examination of "GET" and "POST" commands, if "GET" command is found, previously obtained information being read in said output buffers (5), if
"POST" command is found, the received information is stored for the host system.
6. The microcontroller apparatus as claimed in claim 1, wherein said nticroprograrnming of the control unit (1) by microcodes comprises the generation of standard Internet protocols, and in case of information transmittal towards the network, the generated Internet protocols are added to this information.
EP99939558A 1999-01-14 1999-08-12 Microcontroller apparatus for providing network access to a host system Withdrawn EP1151386A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
HU9900103A HU9900103D0 (en) 1999-01-14 1999-01-14 Apparatus for coupling a parent system to a network
HU9900103 1999-01-14
HU9901701 1999-05-21
HU9901701A HUP9901701A2 (en) 1999-05-21 1999-05-21 Microcontroller arrangement for providing network access to a host system
PCT/HU1999/000058 WO2000042516A1 (en) 1999-01-14 1999-08-12 Microcontroller apparatus for providing network access to a host system

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