Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
  • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
  • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
  • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
  • H04N21/4405—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video stream decryption
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
  • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
  • H04N21/45—Management operations performed by the client for facilitating the reception of or the interaction with the content or administrating data related to the end-user or to the client device itself, e.g. learning user preferences for recommending movies, resolving scheduling conflicts
  • H04N21/462—Content or additional data management, e.g. creating a master electronic program guide from data received from the Internet and a Head-end, controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
  • H04N21/4623—Processing of entitlement messages, e.g. ECM [Entitlement Control Message] or EMM [Entitlement Management Message]
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
  • H04L69/22—Parsing or analysis of headers

Definitions

• the present invention relates to the dissemination of data from a server.
• a server We can for example consider a broadcasting, by satellite, of television image data, Internet data or others.
• a plurality of programs is broadcast in the form of encrypted data packets, to the MPEG 2 standard.
• a packet contains an address field specifying the subscriber or the group of recipient subscribers and, in their receivers, the packets are decrypted by a key provided only to subscribers and are then used as image streams. 'they correspond to the address of the receiver, initially supplied to subscribers by the server operator.
• the receivers cannot communicate in return with the server, to confirm the good reception of each data packet. It is obviously out of the question to establish a return telephone connection each time. As a result, the operator operating the server could not a priori foresee an indisputable charging at the transmission level and, moreover, the receivers did not include a charging function.
• a third possible solution was to replace the software of the second solution by an electronic module, forming a logical key, to be connected to a connector of the PC.
• Such a more secure hardware solution would have been just as expensive, however.
• the Applicant then had the idea of combining the flexibility of a technical upgrade by software, therefore at low cost, with the good robustness to fraud offered by electronic circuits, with combinatorial logic programmable on site, present in the receiver to perform address filtering.
• the Applicant then considered the programmable "image" of the network of circuits with combinational logic, an image defining their various functions, as an electronic key making it possible to keep in service only receivers upgraded by new reception software, further introducing, into the receiver, a function of certification of the good reception of the data and therefore allowing the charging.
• the data transmission protocol was modified, to oblige subscribers to install the new reception software, using, different from the previous one, the circuits with combinatorial logic above, and thus to introduce the charging function, this is ie the certification of the good reception of the data.
• the present invention thus aims to certify the correct reception of data disseminated, whether for accounting, routing security, legal or other purposes.
• the invention relates first of all to a method of technical upgrading of a receiver of data broadcast in packets, from a transmitter, each packet comprising a recipient address field having a reserved position and a useful data field and, in the receiver, the address field being compared, by combinable logic circuits programmable on site, with an address memorized locally so that, in the event of a match, the programmable circuits control a processor for reading the useful data, method characterized by the fact that, in the transmitter, the reserved position of the address field is shifted to a new reserved position and, in the receiver, a data block is loaded comprising, at the same time, circuit programming data programmable, specifying the new position of the address field, and the programming data of the processor, to certify and memorize the good reception of the data.
• the invention also relates to a removable computer data medium, for implementing the method of the invention, comprising a data block for managing a receiver of broadcast data packets, block comprising - a programming data area field programmable circuits, with combinatorial logic, data specifying the position, in a packet, of a recipient address field and specifying a configuration of the programmable circuits making it possible to compare the address field of each packet received with a stored address locally and detect a match and - a software area to control a processor for certification and storage of the good reception of the data.
• FIG. 1 is a block diagram of a satellite data broadcasting network with a transmitter and a receiver implementing the method of the invention
• FIG. 2 is a block diagram of the receiver
• Figure 3 formed of Figures 3A and 3B, illustrates the format of a data packet.
• a server 1 transmitting by broadcasting of data comprises a set 12 of encryption of affluent digital data, controlled by a management circuit 11 and supplying encrypted data to a satellite transmitter 13.
• a satellite 2 ensures the broadcasting of data over a large geographic area comprising a plurality of data receivers, like the one referenced 3.
• the receiver 3 is connected to a PC 35, by a bidirectional connection cord 34, comprising a reader 36 of removable data medium, reader 36 which can receive here floppy disks like the one referenced 37.
• the receiver 3 of FIG. 2 comprises at the head circuits 31 for receiving and re-shaping the data, which transmit them to a processing unit 33 and to a circuit 32, here a smart card, which is responsible for cyclically extracting , the received data flow, a new decryption word or key.
• a smart card which is responsible for cyclically extracting , the received data flow, a new decryption word or key.
• this key is scrambled on transmission, by the management circuit 12, and unscrambled by the smart card 32 by a descrambling key complementary to the scrambling key of the management circuit 12, stored locally in the chip 32.
• the cycle for modifying the encryption / decryption keys is here 10 seconds.
• the assembly 33 receives each time in due time, from the chip card 32, the new decryption key, descrambled, and uses it to decrypt each packet received.
• the assembly 33 could be partially integrated into the chip 32, in order to decrypt the packets and transmit them to the rest of the assembly 33, analyzing their content with a view to reading the useful data.
• the chip 32 could re-encrypt the data, but this time with a local key of fixed value, the assembly 33 performing the corresponding decryption.
• FIG. 3A very schematically represents a conventional PI packet of data and transmitted according to the principles of the MPEG 2 standard.
• the PI packet comprises at the head a field 11 of a few bytes containing a descriptor of the types of fields of the packet, a field 12 d recipient address and a field 13 containing the useful data.
• Field 12 can be an INTERNET address.
• the corresponding FIG. 3B represents a P2 packet as transmitted by the server 1.
• the P2 packet also includes a descriptor field, 21, a recipient address field, 22, and a useful data field 23, such as digital television, data transmitted over the INTERNET, or voice. It further comprises, in this example, a field containing a specific pattern of data 20.
• the pattern 20 is a succession of data bits, here 10 bits, forming, like address 22, a remote control key for the receiver 3, so that it recognizes and reads the data.
• the pattern 20 is an additional address also filtering the reception of packets and defining a group of subscribers, here the subscribers whose receiver 3 has been upgraded.
• the transmission protocol or format has been modified so that it is incompatible with the original protocol of the PI packets.
• the motif 20 has been inserted, passing from FIG. 3A to FIG. 3B, so that it occupies, if it were in the conventional package PI, at least partly the position of the one of the two data fields 11, 12 making it possible to correctly receive the useful data 13.
• overwriting the field 11 and / or, as here, the field 12 by the pattern 20 would prohibit any reception and / or use of useful data 13. Therefore, in FIG.
• the pattern 20 partly occupies, in the P2 package, the position corresponding to the address field 12 of the PI package, but the position of the address field 12 has been shifted to position 22 by so, first of all, that it occupies a different position from the field 12 and, moreover here, that this offset position is outside the position of the pattern 20, avoiding any overlap between the fields 20 and 22, here adjacent.
• a conventional receiver which would read the address field 12 could therefore not read the offset address field 22: in this example it would read all or part of the pattern 20 and therefore could not, for lack of concordance with its local address, extract the useful data 23.
• the receiver 3 is on the contrary a receiver, initially conventional, which has been upgraded technically to, in addition to the field 21, recognize the fields 20 and 22.
• the assembly 33 comprises a sequencer processor 330 , here a microprocessor controlled by software stored in a downloadable memory 331, and an integrated circuit comprising a network of circuits with programmable combinational logic 332 (FPLA or FPGA).
• FPLA or FPGA programmable combinational logic
• Such programmable circuits are marketed under the reference "VLEX 6000 family" by the company ALTERA Corp., 101 Innovation Drive, San Jose, California 95134.
• Two parallel / parallel buffer registers 333 and 338 are connected at input to memory output 331.
• the output of the reception circuits 31 is connected to decryption circuits 348 receiving, here through the microprocessor 330, the decryption key, descrambled, supplied by the smart card 32.
• the output of the circuits 348 feeds three shift registers in 342, 341 and 336 series intended to contain, once a P2 packet received, respectively, the useful data field 23, the address field 22 and the pattern 20.
• a serial register receiving the field 21 has not been drawn , for the sake of clarity.
• a first comparator 334 with two channels (group of parallel inputs) is connected by these respectively to the parallel outputs of registers 333 and 336, while a second comparator 339 with two parallel channels is connected by these with the parallel outputs respective registers 338 and 341.
• a multi-channel multiplexer 335 Between the outputs of the register 336 and the inputs of the comparator 334 is interposed a multi-channel multiplexer 335 whose parallel inputs can thus read a section of variable position in the data of the packet P2.
• a multi-channel multiplexer 340 is interposed between the outputs of register 341 and comparator 339.
• the address inputs of multiplexers 335 and 340 are controlled by buffer registers, respectively 337 and 342, loaded from memory 331, in order to read, by the multiplexers 335 and 340, the pattern 20 and the field 22 at the position provided in the packet P2.
• the outputs of comparators 334 and 339 control the two inputs of an AND gate 343, for validation of reception, connected as an output to a first input of an AND gate 344 receiving, on a second input, the serial output of the register at offset 342 containing field 23 of useful data.
• the output of the gate 344 is connected to the cord 34 of bidirectional connection with the PC 35.
• a data exchange protocol between the receiver 3 and the PC 35 is stored in the memory 331 to control the processor 330 and similarly stored in the PC 35.
• the floppy disk 37 makes it possible, in this example, to load and change this protocol.
• the representation, in three registers 342, 341 and 336, of the global reception register has only one purpose of clarity, and that the multiplexers 335 and 340 for selecting the position of the fields 20 and 22 can each be connected at any stage, or bit memory point, of this global register, possibly external to the register 341 or 336 associated in the figure.
• the data read input of gate 344 can be linked to this global register by a multiplexer if the position of field 23 is also likely to vary.
• a data receiver line circuit 345 connects the link 34 to the memory 331 controlling the microprocessor 330, for loading update software from the PC 35.
• the output of the validation gate 343 is also connected to microprocessor 330 and to the input for activating a counter 349 connected, by its parallel outputs, to the data inputs of a multiplexer 350 for reading the state of counter 349 and itself connected by its output to link 34.
• the microprocessor 330 controls the addressing of the multiplexer 350. Physically, the counter 349 and the multiplexer 350 are in fact conventional elements of any microprocessor like 330 and are therefore integrated into it. It is the programming which in fact shows, by the software of the memory 331, the functional existence of these two elements and of the associated function of certification of the good reception of the data, activated by the gate 343.
• the method makes it possible to upgrade the receiver 3 of data broadcast in packets, from the transmitter 1, each packet comprising a recipient address field 12 having a reserved position and a useful data field 13, in the receiver 3, the address field 12 being compared, by the circuits 332 with combinable logic programmable on site, to an address stored locally so that, in the event of a match, the programmable circuits 332 control the processor 330 for reading useful data.
• the position of the address field 12 is shifted to the new position 22 and, in the receiver 3, a data block is loaded comprising, at the same time, programming data for the programmable circuits 332 , and in particular 337 and 342, specifying the new position of the address field 22, and of the programming data 331 of the processor 330, to certify and memorize the good reception of the data 23.
• a determined data pattern 20 is inserted in each packet P2, occupying at least partially the position initially reserved for the address field 12, the new position of the latter is determined. 22 to avoid overlapping with the pattern 20, the value of the pattern and the positions of the pattern 20 and of the address 22 are supplied to the receiver 3 and, in the receiver 3, the addresses 22 and the pattern are searched for at the said positions 20 in order, if successful, to control the read processor 330.
• the floppy disk 37 contains a receiver management data block 3, making it possible to adapt it to the format of the P2 packets and therefore to read the field 23 thereof, in order to use it.
• the data block includes:
• a programming data area of the circuit 332 programmable on site with combinational logic, data specifying the position, in a P2 packet, of the destination address field 22 and specifying a configuration of the programmable circuits 332 making it possible to compare the field of address 22 of each P2 packet received at a locally stored address and to detect a match, and
• a software zone for controlling the processor 330 for certification and storage of the good reception of the data.
• the block comprises a data area specifying the value and the position, in a P2 packet, of the data pattern 20, complementary to the address 22, to be recognized by the programmable circuits 332.
• it comprises a data area for specifying a communication protocol between the programmable circuits 332 and the processor 330 as well as a software data area for a computer 35 for processing the data from the receiver 3, as well as data from specification of a transmission protocol, from the receiver 3 to the computer 35, of the broadcast data received.
• the reader 36 makes it possible to transmit the data from the floppy disk 37 to the memory 331, by the link 34 and the receiver 345.
• the microprocessor 330 commands a loading of the registers 333 and 338 by the new pattern 20 and address received from the PC 35 (if the address, changing position, also changes in value and was therefore transmitted by the diskette 37) and further configures the combinational logic circuit 332, dynamically configurable on site.
• the registers 337 and 342 receive from memory 331, under the control of the microprocessor 330, a new value specifying the position of the field 20 or 22 which concerns them, in order to keep the comparators 334 and 339 operational.
• the programmable integrated circuit 332 is very schematically constituted at the input of a column of doors of various types, with several inputs, such as AND, OR, exclusive OR (usable as comparator), inverters and, at output, a line with the same variety of doors. Weights, registers and counters can be provided.
• Each entry door therefore provides a combinational signal of the state of the specific signals applied to its inputs, on an internal "line” link.
• Each exit door entry is connected to an internal "column” link.
• These internal interconnection links can be effected by initially controlling, from the outside, the closing of the row / column crossing points by memorizing an activation bit at the targeted crossings. Two layers (input, output) of combinational logic circuits are thus obtained, the number of layers of which can be increased by looping back into input or by using several such integrated circuits.
• the combinational logic circuit 332 makes it possible to process in parallel a large number of data possibly reacting one on the other and thus forms, by its combinative logic, a set of decision tables with much faster operation (one cycle time) than a sequencer with serial operation (microprocessor 330) controlled by software and processing only one instruction at a time. Because the crossing points are reconfigurable, the circuit 332 has the flexibility of modifying software without being slow.
• the sequencing microprocessor 330 manages the reception and the extraction or reading of the data 23 but the circuit 332 assists it, as a fast coprocessor, for heavy tasks.
• the comparator circuits 334 and 339, processing fields 20, 22 of possibly modifiable size (masking of bits of homologous ranks at the input of the comparators), and the multiplexers 335 and 340, with their control buffers 337 and 342, which point to the desired positions of fields 20 and 22 in the received packet P2, are part of circuit 332, as is gate 343.
• the decryption circuits 348 could have been provided in circuit 332, in order to be able to modify loopback circuits of outputs of a shift register, towards inputs of this one.
• Such a loopback shift register provides a pseudo-random sequence of bits which are combined one by one with the bits received by an exclusive OR gate, to decrypt packets, which have been encrypted in the same way.
• the decryption key makes it possible to determine an initial position in the sequence (forcing the state of the register), while the modification of the loopbacks makes it possible to modify this sequence. It is thus thus, as explained above, to modify, by imported software (37), combinational logic circuits, therefore fast, necessary here for processing high bit rates in real time.
• the gate 343 is validated and it unlocks the gate 344.
• the sequencing microprocessor 330 receiving the output, of validation or unlocking, of the gate 343, then commands, by a read clock signal, the serial emptying of the register 342 on the link 34, for the exploitation of the data of field 23 by the PC 35, if it is INTERNET data by example, or possibly via the PC 35, to a television receiver, not shown, if it is image data.
• the circuit 332 is connected to an input port of the processor 330 and dialogues with it according to the specific protocol mentioned above, loaded from the floppy disk 37 and downloaded into memory 331.
• This protocol between the processor 330 and the programmable circuit 332 protects the certification and metering control link and is managed by a circuit completing gate 343 (not shown, of the UART type) against possible attempts to deactivate metering.
• At least one protocol for transmitting the broadcast data or signaling is modified for good reception and it is introduced, on the occasion of the technical upgrading of the receiver, or of the device 35 data processing, certification software for receiving this data.
• the counter 349 or in fact the counter function "revealed" by the new software in memory 331, is activated in this phase by the validation gate 343 or certification of good reception, the microprocessor 330 cyclically reading the state thereof. to launch a 349 counter management program in time sharing with other tasks.
• the counter 349 operates here as an activation time counter, according to a local clock signal, in order to totalize the data transfer times of the various P2 packets, received and read in order to be used, and therefore to determine the volume thereof. data to be billed, based on the frequency of transfer.
• counting the periods of the clock signal from register 342, in this emptying phase would likewise make it possible to count the bits read in the field 23.
• the microprocessor 330 reads periodically the counter 349 by the multiplexer 350 and transmits this reading to the PC 35 by the link 34 according to the protocol provided, which then retransmits it in deferred time, by telephone link, to a management center associated with the server 1, for charging purposes .
• the 349 counter would allow promptly signal, in return to the server 1 by a link provided for this purpose, that the data have been received.

Landscapes

• Engineering & Computer Science (AREA)
• Databases & Information Systems (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Data Exchanges In Wide-Area Networks (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=9528775

Family Applications (1)

Country Status (4)

Family Cites Families (4)

• 1998
  • 1998-07-20 FR FR9809216A patent/FR2781324B1/fr not_active Expired - Fee Related
• 1999
  • 1999-07-15 AU AU46288/99A patent/AU4628899A/en not_active Abandoned
  • 1999-07-15 EP EP99929487A patent/EP1145523A2/de not_active Withdrawn
  • 1999-07-15 WO PCT/FR1999/001725 patent/WO2000005851A2/fr not_active Application Discontinuation

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events