EP1127318A4 - Method and apparatus for an improved interface between computer components - Google Patents

Method and apparatus for an improved interface between computer components

Info

Publication number
EP1127318A4
EP1127318A4 EP99971542A EP99971542A EP1127318A4 EP 1127318 A4 EP1127318 A4 EP 1127318A4 EP 99971542 A EP99971542 A EP 99971542A EP 99971542 A EP99971542 A EP 99971542A EP 1127318 A4 EP1127318 A4 EP 1127318A4
Authority
EP
European Patent Office
Prior art keywords
computer components
improved interface
interface
improved
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP99971542A
Other languages
German (de)
French (fr)
Other versions
EP1127318A1 (en
EP1127318B1 (en
Inventor
Jasmin Ajanovic
David J Harriman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP1127318A1 publication Critical patent/EP1127318A1/en
Publication of EP1127318A4 publication Critical patent/EP1127318A4/en
Application granted granted Critical
Publication of EP1127318B1 publication Critical patent/EP1127318B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
EP99971542A 1998-11-03 1999-11-01 Method and apparatus for an improved interface between computer components Expired - Lifetime EP1127318B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/186,219 US6145039A (en) 1998-11-03 1998-11-03 Method and apparatus for an improved interface between computer components
US186219 1998-11-03
PCT/US1999/025630 WO2000026798A1 (en) 1998-11-03 1999-11-01 Method and apparatus for an improved interface between computer components

Publications (3)

Publication Number Publication Date
EP1127318A1 EP1127318A1 (en) 2001-08-29
EP1127318A4 true EP1127318A4 (en) 2004-04-14
EP1127318B1 EP1127318B1 (en) 2007-05-09

Family

ID=22684111

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99971542A Expired - Lifetime EP1127318B1 (en) 1998-11-03 1999-11-01 Method and apparatus for an improved interface between computer components

Country Status (9)

Country Link
US (1) US6145039A (en)
EP (1) EP1127318B1 (en)
KR (1) KR100417839B1 (en)
CN (1) CN1253802C (en)
AU (1) AU1461000A (en)
DE (1) DE69936060T2 (en)
HK (1) HK1036853A1 (en)
TW (1) TW476885B (en)
WO (1) WO2000026798A1 (en)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6665807B1 (en) 1998-09-04 2003-12-16 Hitachi, Ltd. Information processing apparatus
JP3592547B2 (en) 1998-09-04 2004-11-24 株式会社ルネサステクノロジ Information processing apparatus and signal transfer method
US20030110317A1 (en) * 1998-11-03 2003-06-12 Jasmin Ajanovic Method and apparatus for an improved interface between a memory control hub and an input/output control hub
US6362826B1 (en) * 1999-01-15 2002-03-26 Intel Corporation Method and apparatus for implementing dynamic display memory
US6345072B1 (en) * 1999-02-22 2002-02-05 Integrated Telecom Express, Inc. Universal DSL link interface between a DSL digital controller and a DSL codec
US6311285B1 (en) * 1999-04-27 2001-10-30 Intel Corporation Method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency
US6792495B1 (en) * 1999-07-27 2004-09-14 Intel Corporation Transaction scheduling for a bus system
US6813251B1 (en) * 1999-07-27 2004-11-02 Intel Corporation Split Transaction protocol for a bus system
US6687240B1 (en) * 1999-08-19 2004-02-03 International Business Machines Corporation Transaction routing system
US6636912B2 (en) * 1999-10-07 2003-10-21 Intel Corporation Method and apparatus for mode selection in a computer system
US6721859B1 (en) * 1999-10-21 2004-04-13 Sony Corporation Multi-protocol media storage device implementing protocols optimized for storing and retrieving both asynchronous and isochronous data
US6496895B1 (en) * 1999-11-01 2002-12-17 Intel Corporation Method and apparatus for intializing a hub interface
US6516375B1 (en) 1999-11-03 2003-02-04 Intel Corporation Peripheral component interconnect (PCI) configuration emulation for hub interface
US6615306B1 (en) * 1999-11-03 2003-09-02 Intel Corporation Method and apparatus for reducing flow control and minimizing interface acquisition latency in a hub interface
US7039047B1 (en) 1999-11-03 2006-05-02 Intel Corporation Virtual wire signaling
US6347351B1 (en) * 1999-11-03 2002-02-12 Intel Corporation Method and apparatus for supporting multi-clock propagation in a computer system having a point to point half duplex interconnect
US6560666B1 (en) * 1999-11-23 2003-05-06 Intel Corporation Hub link mechanism for impedance compensation update
US7512082B1 (en) * 1999-12-14 2009-03-31 Intel Corporation Tracking transaction status for a bus system providing legacy bus compatibility
US6542946B1 (en) * 2000-01-28 2003-04-01 Compaq Information Technologies Group, L.P. Dual mode differential transceiver for a universal serial bus
US6842813B1 (en) * 2000-06-12 2005-01-11 Intel Corporation Method and apparatus for single wire signaling of request types in a computer system having a point to point half duplex interconnect
US7720821B1 (en) 2000-06-30 2010-05-18 Sony Corporation Method of and apparatus for writing and reading time sensitive data within a storage device
EP1179785A1 (en) * 2000-08-07 2002-02-13 STMicroelectronics S.r.l. Bus interconnect system
US6877052B1 (en) 2000-09-29 2005-04-05 Intel Corporation System and method for improved half-duplex bus performance
US6910093B2 (en) * 2000-12-07 2005-06-21 Micron Technology, Inc. Method of pacing and disconnecting transfers on a source strobed bus
US7058823B2 (en) * 2001-02-28 2006-06-06 Advanced Micro Devices, Inc. Integrated circuit having programmable voltage level line drivers and method of operation
US6813673B2 (en) * 2001-04-30 2004-11-02 Advanced Micro Devices, Inc. Bus arbitrator supporting multiple isochronous streams in a split transactional unidirectional bus architecture and method of operation
US6912611B2 (en) * 2001-04-30 2005-06-28 Advanced Micro Devices, Inc. Split transactional unidirectional bus architecture and method of operation
US6785758B1 (en) 2001-06-01 2004-08-31 Advanced Micro Devices, Inc. System and method for machine specific register addressing in a split transactional unidirectional bus architecture
US6763415B1 (en) 2001-06-08 2004-07-13 Advanced Micro Devices, Inc. Speculative bus arbitrator and method of operation
US7028124B2 (en) * 2001-09-26 2006-04-11 Intel Corporation Method and apparatus for dual queue head processing of interrupt endpoints
US6889265B2 (en) 2001-11-05 2005-05-03 Intel Corporation Apparatus and method to allow and synchronize schedule changes in a USB enhanced host controller
US7006533B2 (en) * 2002-02-19 2006-02-28 Intel Corporation Method and apparatus for hublink read return streaming
US7043667B2 (en) * 2002-05-14 2006-05-09 Intel Corporation Debug information provided through tag space
US7120722B2 (en) * 2002-05-14 2006-10-10 Intel Corporation Using information provided through tag space
US20030217301A1 (en) * 2002-05-16 2003-11-20 Levy Paul S. Method and apparatus for transmitting side-band data within a source synchronous clock signal
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7117316B2 (en) 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US6820181B2 (en) 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7330992B2 (en) 2003-12-29 2008-02-12 Micron Technology, Inc. System and method for read synchronization of memory modules
US7210000B2 (en) * 2004-04-27 2007-04-24 Intel Corporation Transmitting peer-to-peer transactions through a coherent interface
US20080005378A1 (en) * 2006-05-19 2008-01-03 Intel Corporation Chipset determinism for improved validation
US7702832B2 (en) * 2006-06-07 2010-04-20 Standard Microsystems Corporation Low power and low pin count bi-directional dual data rate device interconnect interface
US8806093B2 (en) * 2010-04-01 2014-08-12 Intel Corporation Method, apparatus, and system for enabling a deterministic interface
CN102133308A (en) * 2011-03-04 2011-07-27 邹天琼 Capsule for removing toxin and eliminating fat
TWI506443B (en) * 2012-12-27 2015-11-01 Mediatek Inc Media peripheral interface and communication method between processor and peripheral device
US9946683B2 (en) 2014-12-24 2018-04-17 Intel Corporation Reducing precision timing measurement uncertainty
CN117290278A (en) * 2023-10-10 2023-12-26 合芯科技有限公司 Chip hardware interconnection structure, chip, server and method

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4033417A1 (en) * 1990-10-20 1992-04-23 Basf Ag METHOD FOR THE PRODUCTION OF ZINCOXIDE PIGMENTS DOPED WITH METAL OXIDS
US5191649A (en) * 1990-12-21 1993-03-02 Intel Corporation Multiprocessor computer system with data bus and ordered and out-of-order split data transactions
JP3411300B2 (en) * 1992-02-18 2003-05-26 株式会社日立製作所 Information processing device
US5553310A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems
US5590292A (en) * 1992-12-08 1996-12-31 Compaq Computer Corporation Scalable tree structured high speed input/output subsystem architecture
US5687388A (en) * 1992-12-08 1997-11-11 Compaq Computer Corporation Scalable tree structured high speed input/output subsystem architecture
US5469435A (en) * 1994-01-25 1995-11-21 Apple Computer, Inc. Bus deadlock avoidance during master split-transactions
US5533204A (en) * 1994-04-18 1996-07-02 Compaq Computer Corporation Split transaction protocol for the peripheral component interconnect bus
US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
US5621897A (en) * 1995-04-13 1997-04-15 International Business Machines Corporation Method and apparatus for arbitrating for a bus to enable split transaction bus protocols
US5933612A (en) * 1995-05-02 1999-08-03 Apple Computer, Inc. Deadlock avoidance in a split-bus computer system
US5996036A (en) * 1997-01-07 1999-11-30 Apple Computers, Inc. Bus transaction reordering in a computer system having unordered slaves
US5761444A (en) * 1995-09-05 1998-06-02 Intel Corporation Method and apparatus for dynamically deferring transactions
US5911052A (en) * 1996-07-01 1999-06-08 Sun Microsystems, Inc. Split transaction snooping bus protocol
US5978874A (en) * 1996-07-01 1999-11-02 Sun Microsystems, Inc. Implementing snooping on a split-transaction computer system bus
US5802055A (en) * 1996-04-22 1998-09-01 Apple Computer, Inc. Method and apparatus for dynamic buffer allocation in a bus bridge for pipelined reads
US6021456A (en) * 1996-11-12 2000-02-01 Herdeg; Glenn Arthur Method for communicating interrupt data structure in a multi-processor computer system
US6012118A (en) * 1996-12-30 2000-01-04 Intel Corporation Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus
US5832243A (en) * 1996-12-31 1998-11-03 Compaq Computer Corporation Computer system implementing a stop clock acknowledge special cycle
US5918025A (en) * 1996-12-31 1999-06-29 Intel Corporation Method and apparatus for converting a five wire arbitration/buffer management protocol into a two wire protocol
US5870567A (en) * 1996-12-31 1999-02-09 Compaq Computer Corporation Delayed transaction protocol for computer system bus
US5930485A (en) * 1997-01-07 1999-07-27 Apple Computer, Inc. Deadlock avoidance in a computer system having unordered slaves
US5991824A (en) * 1997-02-06 1999-11-23 Silicon Graphics, Inc. Method and system for simultaneous high bandwidth input output
US5909594A (en) * 1997-02-24 1999-06-01 Silicon Graphics, Inc. System for communications where first priority data transfer is not disturbed by second priority data transfer and where allocated bandwidth is removed when process terminates abnormally
US5944805A (en) * 1997-08-21 1999-08-31 Advanced Micro Devices, Inc. System and method for transmitting data upon an address portion of a computer system bus during periods of maximum utilization of a data portion of the bus

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
No further relevant documents disclosed *
See also references of WO0026798A1 *

Also Published As

Publication number Publication date
KR20010092432A (en) 2001-10-24
KR100417839B1 (en) 2004-02-11
DE69936060T2 (en) 2008-01-10
CN1253802C (en) 2006-04-26
US6145039A (en) 2000-11-07
EP1127318A1 (en) 2001-08-29
AU1461000A (en) 2000-05-22
EP1127318B1 (en) 2007-05-09
HK1036853A1 (en) 2002-01-18
TW476885B (en) 2002-02-21
CN1348565A (en) 2002-05-08
DE69936060D1 (en) 2007-06-21
WO2000026798A1 (en) 2000-05-11

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