EP1119916A1 - Systeme de decodeur viterbi a configuration de retra age - Google Patents

Systeme de decodeur viterbi a configuration de retra age

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Publication number
EP1119916A1
EP1119916A1 EP00949426A EP00949426A EP1119916A1 EP 1119916 A1 EP1119916 A1 EP 1119916A1 EP 00949426 A EP00949426 A EP 00949426A EP 00949426 A EP00949426 A EP 00949426A EP 1119916 A1 EP1119916 A1 EP 1119916A1
Authority
EP
European Patent Office
Prior art keywords
state
survivor
decoder system
pointers
trace
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00949426A
Other languages
German (de)
English (en)
Inventor
Abraham J. De Bart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP00949426A priority Critical patent/EP1119916A1/fr
Publication of EP1119916A1 publication Critical patent/EP1119916A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H03M13/6505—Memory efficient implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback

Definitions

  • the invention relates to a Viterbi decoder system as recited in the preamble of Claim 1.
  • Systems based on the Viterbi algorithm are in general usage for solving various maximum likelihood estimation problems. Without restriction, the disclosure hereinafter is directed to their use for decoding error protective convolutional codes in communication systems.
  • a general treatise of the Viterbi algorithm has been presented in G.D. Forney, The Viterbi Algorithm, Proc. IEEE Vol 61 (1973) pp 268-278.
  • the trace-back implementation of the Viterbi decoding approach is used in particular if the truncation length L and the constraint length K relatively large, and if the required processing speed required is relatively high.
  • the decoding is executed on successive intervals that each have the decoding truncation length L, and it will present the best path estimate in a reverse order as compared with the sequence of receiving the encoded data.
  • the procedure will necessitate four random access memories, each with a storage depth that equals the truncation length L, and which memories will collectively occupy a large fraction of the overall decoding chip area, and will in consequence bring about a relatively large part of the chip cost. It would be preferable to diminish this area.
  • Such state pointers for each associated current state indicate with respect to an interval of predetermined length a preceding state to be reached through a trace-back over the interval in question.
  • Figure 1 a top level architecture of a Viterbi decoder
  • Figure 9 an exemplary architecture of a Survivor Memory Unit
  • Figure 10 the functional sequence for the prior art Trace Back operation
  • Figure 1 shows a top level architecture of a Viterbi decoder.
  • the present invention may be applied in various different contexts, but has in particular been conceived for a specific error protective convolutional code for data communication, with a constraint length K, and with a rate R that is less than unity.
  • the code itself has been described in ETSI Digital Broadcasting Systems for Television, Sound and Data Services, Frame Structure, Channel
  • the present invention uses a Viterbi decoder algorithm with a trace-back implementation.
  • Another implementation would have been the so-called Register Exchange Algorithm, which for a great truncation length, and in consequence, many states, would however require too much hardware.
  • the stream of error-protected input data arrives on input 20, in the form of a bit stream that has been subjected to a hard decision or soft decision procedure.
  • the Branch Metric Unit (BMU) 22 computes the distance of the received data on input 20 to the respective edges of the trellis that spans the various states of the receiving system.
  • the Add- Compare-Select (Add-Compare-Select) unit 26 determines for each path the cumulative error or metric, and for each trellis state the associated optimum path. As shown by retrocoupling means 28, this cumulation is a progressive procedure that steps for each data symbol or data unit received.
  • the output of Add-Compare-Select 26 are the 2 K 1 survivors (30) of the trellis at that instant.
  • the Survivor Memory Unit (SMU) 34 uses these survivors to determine the decoded data.
  • the present invention deals with raising the area-efficiency of the SMU 32
  • the survivor bits that arrive from Add-Compare-Select 26 collectively form a survivor word and represent pointers that link each respective state with its associated surviving predecessor state from the previous stage or symbol cell. Searching back from a particular state will let the system retrieve the best path. Note that each current state has its own respective best path. With a high probability, these best paths will merge at a certain depth back in time.
  • the depth that is actually used for the maximum likelihood decoding is called the truncation length L; the value of L will thus be chosen equal to or larger than this "certain depth". At depth L, all oldest survivors will have merged, thereby allowing the system to decode the associated oldest bit.
  • Figure 2 shows this merging of survivor paths in a direction to the left.
  • Figure 3 represents a known Trace Back Algorithm that is based on 64 states, and in consequence, uses a six-bit state pointer that points at one position along the survivor word.
  • the survivor word has been shown as a column consisting of 64 bits. Successive columns have been formed from a sequence of L successive survivor words that had arrived from Add-Compare-Select 30. The actual survivor word is written into a RAM that is part of SMU 32.
  • an arbitrary state pointer such as 000 000 is assumed and loaded in a register, upper row at right in the Figure. For simplicity, data and control path of this register have not been shown in detail. Now, this pointer addresses a bit in the most recent column of survivor bits.
  • this bit has the value "1" as shown, and is shifted into the most significant position of the pointer register that now will read 100 000 as shown, second row at right in the Figure.
  • the state pointer with a digital value of 32, will now address a single bit in the second survivor word column from the right, that has a "1" value.
  • This bit will also shift into the register, third row at right, giving the state pointer a value of 48.
  • the procedure is continued and will next lead to a state pointer of 011 000, and so on, until eventually attaining a depth of L columns. At this truncation depth, the correct path will with a high probability have been reached. This is the pre-race-back procedure.
  • the next bit obtained by accessing the memory at left from this trace-back will therefore be a real decoded bit in the final trace-back procedure, which is invariant under any change in the initial state pointer value.
  • the output of SMU 32 consists of L bits that will be produced in reverse temporal order.
  • the amount of RAM may be reduced through using RAMs that can read and write in one cycle, and/or a larger number of smaller RAMs. The latter however need more overhead area for address generating.
  • the operating as described has been illustrated in Figure 10.
  • Figure 5 shows a Radix-2 Multi-Butterfly embodiment, that is used in the present embodiment.
  • Each of the two states i and (i+2 K"2 ) at left is connected to states 2i and (2i+l) at right, modulo 2 K" ⁇
  • state 0 at left is connected to states 0 and 1 at right, just as is state 4 at left.
  • this single butterfly has been indicated in doubled lines.
  • Such butterfly structure is now used to indicate the interconnection pattern between the states, for conveniently updating the state pointers. In fact, for each current state the state pointer grows incrementally whilst pointing to a state that is 1, 2, ... L stages back.
  • the improved schedule joins combinatorial logic with aspects of the earlier register-exchange structure, that itself could not be used because of its great hardware requirements.
  • the combination can perform the Pre Trace Back operation in parallel to the writing. This distinguishes radically from the earlier setup, wherein the Pre Trace Back could only commence after L columns had been written, due to the mutually inverse directions of the writing versus the traceback. Therefore, the Final Trace Back can start a whole interval of L cycles earlier, and the number of RAMs can be reduced from four to three.
  • the scheduling has been shown in Table 2. As an example, suppose that the write operation in RAM 1 has just finished and the writing into RAM2 is started.
  • Figure 6 shows accordingly an example of the updating of the State Pointers.
  • Figure 6 uses a trellis with eight states only, and shows the updating of the state pointers over only three successive clock cycles. Note that, as opposed to the prior art procedure, the various state pointers will be updated in the forward direction.
  • the first cycle shown is the initialization step, wherein the state pointers are calculated in the same way as according to the state of the art. For clarity, only the updating of the uppermost and lowermost butterflies, respectively, have been shown by indicating the connections between the associated states. The solid lines indicate the survivor paths, whereas the dashed lines indicate paths that will be discarded.
  • the state pointers are updated by copying the state pointer of the previous surviving state to the current state.
  • the known Add-Compare-Select unit has the copying of the path metric of the previous surviving state to the current state.
  • the system determines the respectively associated state that would result from tracing back over t branches, so to the final column of RAM 1. This is advantageously done by for each state copying the state pointer of its surviving predecessor. After L clock cycles, RAM2 will be filled with new data, and we will also have the result of a Pre-Trace-Back from each of the available states to the start of RAM 1. As can be seen from Figure 6, a particular state pointer that has stopped to be a survivor for any of the states, will never reappear in the list again. Hence, the values of all state pointers will eventually merge into a single value when attaining the truncation length.
  • Figures 7A-7C indicate the Pre Trace Back in combinatorial logic, for a logic depth of L. For simplicity, an organization with a relatively reduced number of state pointers has been shown, the actual value of this number being less relevant for the qualitative showing.
  • the Pre-Trace Back starts from the left-hand edge of RAM2 and results in a rather large number of result paths of which a single pair has been shown as actually merging.
  • various ones of the paths have merged already, which has been symbolized by the actual merging inside the RAM in question, so that at the left hand edge of RAM2 only four of these resulting paths are still present, of which one pair has been shown to actually merge at the right hand side of RAM 1.
  • all paths have merged to a single path.
  • Figures 8A-8C show a Pre-Trace-Back in combinatorial logic amended for the usage of RAM modules that have a depth of only L/2, instead of operating on blocks of depth L. We may in this manner even further reduce the amount of memory and silicon area. Inasmuch as the truncation length should remain equal to L, we need to store the results of a Pre Trace Back of depth L/2 until the Pre Trace Back over the next L/2 columns will have finished. Then we may find the starting state for the Final Trace Back as a concatenation of the two Pre Trace Back operations. This has been shown in Figures 8A-8C, that distinguish the span of the Pre Trace Back over a full L columns, combined with the modularization of the RAM in modules of L/2 columns each.
  • the uppermost representation corresponds to that of Figure 7A.
  • the other two representations also have their respective parallels in Figures 7B, 7C, respectively.
  • the heavy vertical lines indicate that the process has actually arrived at the edge of the RAM module in question.
  • FIG. 9 shows an architecture embodiment of a Survivor Memory Unit.
  • the Pre-Trace-Back Unit 56 receives the survivors and contains the recursive computations of the starting state for the Final Trace Back.
  • This unit comprises a first set of 2 K 1 registers of K-l bits each that are updated in each clock cycle through a first control signal "update bank”, and a second set of 2 K_1 registers of K-l bits each that are updated in each clock cycle through a second control signal "storage bank” to store the signals of the previous PTB operation.
  • Each time the "new PTB" signal from the SMU control unit 54 goes high the results of the current PTB operation are shifted to the storage bank, and a new PTB operation is started in the update bank.
  • the result of the concatenation of two PTB results is sent to the control unit 54 as representing the starting for the Final Trace Back. Furthermore, the control unit 54 decides which one of the two RAMs 50, 52 will be read and which one will be written, through the R/W control signal pair.
  • the memory addresses are calculated as starting from the state (FTB) that is being received from the PTB-unit 56, as a starting point for again going backwards as discussed with reference to Figure 3 supra.
  • the decoded data is run through a LIFO memory arrangement not shown for clarity, and outputted on output 60 for further usage.
  • the timing in the SMU-control unit takes into account that one clock cycle is necessary for the sending of the address to memory, and the reception of the associated read data.
  • the new algorithm as presented is useful to reduce the overall chip area that is necessary for implementing the survivor memory of a Viterbi decoder.
  • the algorithm performs the Pre-Trace-Back operation in combinatorial logic, and in parallel with the writing of the survivors. In this manner, the results of the Pre-Trace-Back will be available one time slot earlier than before, and hence the Final Trace Back can also start one time slot earlier. This decreases both the memory size for data storage, and also the overall latency of the decoder.
  • a trade-off may be made between the usage of RAM, and the increased amount of combinatorial logic that is necessary for using smaller RAMs.
  • RAMs circuitry is more dense than combinatorial logic, but on the other hand, logic is more easy to route during the layout process.
  • the use of relatively more combinatorial logic will therefore allow a designer more flexibility in the positioning of the various functional blocks.
  • a size reduction of the SMU unit of about 25% has been obtained. Inasmuch as the SMU unit often consumes the larger part of the decoder overall area, this represents an appreciable gain.
  • the LIFO store that is needed for reordering the decoded bits may be reduced in size by 50%, just as the storage of the number of hard decision bits for a BER estimation.
  • a decoder system with a decreased latency will present smaller memory requirements for the associated delay line.
  • the synchronizing of the next block in the communication system may start earlier along with the decreasing of the Viterbi decoder latency.

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

L'invention concerne un décodeur Viterbi à système générateur de métrique de branche (22) qui, pour chacune des différentes séries de données de branche en treillis reçues, permet de fournir une métrique de branche associée. Le décodeur comprend en outre un système à addition-comparaison-sélection (ACS) (26) qui permet d'ajouter, par chemin, la métrique de branche engendrée à la métrique de chemin, d'associer à chaque état de treillis un chemin optimal, et aussi d'établir une série de chemins survivants en effectuant une sélection parmi les divers chemins optimaux. Le décodeur comprend enfin une mémoire de chemins survivants (32) qui permet de recevoir et d'enregistrer provisoirement la série de chemins survivants. Le décodeur est conçu pour assurer la mise à jour incrémentielle de pointeurs d'état vers l'avant. Pour chaque état effectif courant, ces pointeurs fournissent, par rapport à un intervalle de longueur d'incrémentation prédéterminée allant au maximum jusqu'à une longueur de troncature L, une indication concernant l'état précédent à atteindre par retraçage sur une longueur effective de l'intervalle. La mise à jour est effectuée pour un mot survivant effectif par copie du bit de pointeur d'état associé dans une pluralité de registres de pointeur d'état correspondant respectivement à un pointeur d'état courant.
EP00949426A 1999-08-16 2000-07-31 Systeme de decodeur viterbi a configuration de retra age Withdrawn EP1119916A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP00949426A EP1119916A1 (fr) 1999-08-16 2000-07-31 Systeme de decodeur viterbi a configuration de retra age

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP99202647 1999-08-16
EP99202647 1999-08-16
EP00949426A EP1119916A1 (fr) 1999-08-16 2000-07-31 Systeme de decodeur viterbi a configuration de retra age
PCT/EP2000/007411 WO2001013524A1 (fr) 1999-08-16 2000-07-31 Systeme de decodeur viterbi a configuration de retraçage

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EP1119916A1 true EP1119916A1 (fr) 2001-08-01

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EP (1) EP1119916A1 (fr)
JP (1) JP2003507921A (fr)
WO (1) WO2001013524A1 (fr)

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Publication number Priority date Publication date Assignee Title
US7623598B2 (en) 2002-08-19 2009-11-24 Infineon Technologies Ag Demodulation of a frequency-modulated received signal by means of a Viterbi algorithm

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09191258A (ja) * 1996-01-08 1997-07-22 Matsushita Electric Ind Co Ltd ビタビ復号装置及びその方法

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Publication number Priority date Publication date Assignee Title
JP3269845B2 (ja) * 1992-05-12 2002-04-02 株式会社日立製作所 ヴィタビ復号器
KR0135796B1 (ko) * 1994-11-14 1998-04-27 김광호 비터비복호기에서 트레이스백 수행장치
JP2904271B2 (ja) * 1996-08-09 1999-06-14 日本電気株式会社 ビタビ復号器用パスメモリユニットおよび復号方法
JP3747604B2 (ja) * 1997-12-19 2006-02-22 ソニー株式会社 ビタビ復号装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09191258A (ja) * 1996-01-08 1997-07-22 Matsushita Electric Ind Co Ltd ビタビ復号装置及びその方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO0113524A1 *

Also Published As

Publication number Publication date
WO2001013524A1 (fr) 2001-02-22
JP2003507921A (ja) 2003-02-25

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