EP1105793A4 - Verarbeitungselement mit speziellen anwendungen für zweigfunktionen - Google Patents

Verarbeitungselement mit speziellen anwendungen für zweigfunktionen

Info

Publication number
EP1105793A4
EP1105793A4 EP99943848A EP99943848A EP1105793A4 EP 1105793 A4 EP1105793 A4 EP 1105793A4 EP 99943848 A EP99943848 A EP 99943848A EP 99943848 A EP99943848 A EP 99943848A EP 1105793 A4 EP1105793 A4 EP 1105793A4
Authority
EP
European Patent Office
Prior art keywords
processor
instructions
instruction
branch
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99943848A
Other languages
English (en)
French (fr)
Other versions
EP1105793A1 (de
Inventor
Rajit Manohar
Alain Martin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
California Institute of Technology CalTech
Original Assignee
California Institute of Technology CalTech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by California Institute of Technology CalTech filed Critical California Institute of Technology CalTech
Publication of EP1105793A1 publication Critical patent/EP1105793A1/de
Publication of EP1105793A4 publication Critical patent/EP1105793A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/43—Checking; Contextual analysis
    • G06F8/433—Dependency analysis; Data or control flow analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
EP99943848A 1998-08-21 1999-08-20 Verarbeitungselement mit speziellen anwendungen für zweigfunktionen Withdrawn EP1105793A4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US9751598P 1998-08-21 1998-08-21
US97515P 1998-08-21
PCT/US1999/019197 WO2000011547A1 (en) 1998-08-21 1999-08-20 Processing element with special application for branch functions

Publications (2)

Publication Number Publication Date
EP1105793A1 EP1105793A1 (de) 2001-06-13
EP1105793A4 true EP1105793A4 (de) 2007-07-25

Family

ID=22263771

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99943848A Withdrawn EP1105793A4 (de) 1998-08-21 1999-08-20 Verarbeitungselement mit speziellen anwendungen für zweigfunktionen

Country Status (3)

Country Link
EP (1) EP1105793A4 (de)
AU (1) AU5686599A (de)
WO (1) WO2000011547A1 (de)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0284364A2 (de) * 1987-03-27 1988-09-28 Seiko Instruments Inc. Hochgeschwindigkeitscomputersystem
WO1994016383A1 (en) * 1993-01-06 1994-07-21 The 3Do Company Digital signal processor architecture
EP0660223A2 (de) * 1993-11-30 1995-06-28 Texas Instruments Incorporated Drei-Eingänge-Arithmetik-Logik-Einheit mit Trommel-Rotationsschaltung und Maskengenerator
US5485629A (en) * 1993-01-22 1996-01-16 Intel Corporation Method and apparatus for executing control flow instructions in a control flow pipeline in parallel with arithmetic instructions being executed in arithmetic pipelines

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4338661A (en) * 1979-05-21 1982-07-06 Motorola, Inc. Conditional branch unit for microprogrammed data processor
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5781752A (en) * 1996-12-26 1998-07-14 Wisconsin Alumni Research Foundation Table based data speculation circuit for parallel processing computer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0284364A2 (de) * 1987-03-27 1988-09-28 Seiko Instruments Inc. Hochgeschwindigkeitscomputersystem
WO1994016383A1 (en) * 1993-01-06 1994-07-21 The 3Do Company Digital signal processor architecture
US5485629A (en) * 1993-01-22 1996-01-16 Intel Corporation Method and apparatus for executing control flow instructions in a control flow pipeline in parallel with arithmetic instructions being executed in arithmetic pipelines
EP0660223A2 (de) * 1993-11-30 1995-06-28 Texas Instruments Incorporated Drei-Eingänge-Arithmetik-Logik-Einheit mit Trommel-Rotationsschaltung und Maskengenerator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO0011547A1 *

Also Published As

Publication number Publication date
WO2000011547A9 (en) 2000-08-10
WO2000011547A1 (en) 2000-03-02
EP1105793A1 (de) 2001-06-13
AU5686599A (en) 2000-03-14

Similar Documents

Publication Publication Date Title
US6157988A (en) Method and apparatus for high performance branching in pipelined microsystems
McFarling et al. Reducing the cost of branches
Ditzel et al. Branch folding in the CRISP microprocessor: Reducing branch delay to zero
US6631514B1 (en) Emulation system that uses dynamic binary translation and permits the safe speculation of trapping operations
EP0459232B1 (de) Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür
US6523110B1 (en) Decoupled fetch-execute engine with static branch prediction support
US6928645B2 (en) Software-based speculative pre-computation and multithreading
US5692169A (en) Method and system for deferring exceptions generated during speculative execution
US5421020A (en) Counter register implementation for speculative execution of branch on count instructions
Schlansker et al. EPIC: An architecture for instruction-level parallel processors
US20020087849A1 (en) Full multiprocessor speculation mechanism in a symmetric multiprocessor (smp) System
US20070174555A1 (en) Future execution prefetching technique and architecture
US6687812B1 (en) Parallel processing apparatus
US20100287358A1 (en) Branch Prediction Path Instruction
Nakra et al. Value prediction in VLIW machines
US20020161987A1 (en) System and method including distributed instruction buffers holding a second instruction form
US5737562A (en) CPU pipeline having queuing stage to facilitate branch instructions
EP1105793A1 (de) Verarbeitungselement mit speziellen anwendungen für zweigfunktionen
Steven et al. Using a resource-limited instruction scheduler to evaluate the iHARP processor
Song Demystifying epic and ia-64
Tyagi et al. Dynamic branch decoupled architecture
Thakkar et al. An instruction fetch unit for a graph reduction machine
González A survey of branch techniques in pipelined processors
Matui et al. Gmicro/500 microprocessor: Pipeline structure of superscalar architecture
Hwu et al. Efficient instruction sequencing with inline target insertion

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20010320

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

A4 Supplementary search report drawn up and despatched

Effective date: 20070621

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 9/45 20060101ALI20070615BHEP

Ipc: G06F 9/38 20060101ALI20070615BHEP

Ipc: G06F 9/32 20060101AFI20070615BHEP

17Q First examination report despatched

Effective date: 20071008

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20100302