EP1078388A1

EP1078388A1 - Method and installation for correcting integrated circuit faults with an ion beam

Info

Publication number: EP1078388A1
Application number: EP99918038A
Authority: EP
Inventors: Jamel Benbrik
Original assignee: Centre National dEtudes Spatiales CNES
Current assignee: Centre National dEtudes Spatiales CNES
Priority date: 1998-05-11
Filing date: 1999-05-10
Publication date: 2001-02-28
Also published as: FR2778493A1; WO1999059184A1; FR2778493B1

Abstract

The invention concerns a method and an installation for correcting faults in integrated circuits (14) which consists in using a positive ion beam focused on a surface (23) of the integrated circuit (14) with an incident energy not less than 20 keV for etching and/or depositing without mask, and imaging means (31) by potential contrast from secondary electrons. The invention is characterised in that it consists in generating, directly above the integrated circuit (14) surface (23), a local electric field to prevent cationic species from accumulating on the integrated circuit surface (23) without cancelling the electric field detecting the secondary electrons, and in maintaining said local electric field while the ion beam is being applied on the integrated circuit surface (23).

Description

METHOD AND INSTALLATION FOR CORRECTING FAULTS IN CIRCUITS INTEGRATED BY AN ION BEAM

The invention relates to a method and an installation for correcting faults in integrated circuits using a beam of positive ions focused on the integrated circuit.

Despite the progress made in the design and manufacture of integrated circuits, a large proportion (of the order of 15%) of circuits from the first series of foundry manufacturing (successive deposits using masks) is not functional and has faults. This proportion increases with the complexity of the circuits and their miniaturization. The development of industrial manufacturing of an integrated circuit therefore requires first carrying out a few prototype copies which are then tested to verify their real electrical characteristics. Before launching the production series, it is extremely important to be able to correct any faults detected and to retest the circuit thus corrected. These operations, called debugging operations, can of course be carried out in the foundry using modified masks. However, each foundry manufacturing is expensive and requires a significant time, delaying the industrial mass production of the integrated circuit.

To overcome this drawback, it is sought to correct the defects using technologies which are quick to implement and less costly, which avoid the production of masks. To do this, different manufacturers offer so-called FIB (“focused ion beam”) systems. These systems make it possible to produce etchings and / or deposits without mask using a beam of high energy positive ions (more than 20 keV) focused on the circuit in a localized area where a correction must be made. It is thus possible, for example, to make an opening in the insulating passivation layer formed of oxides, then to cut lines, or to deposit conductive interconnection bridges between lines.

However, the use of these systems is still limited by the fact that the application of a high energy ion beam on a circuit integrated is not free from consequences and generates untimely modifications of its characteristics, or even deterioration.

Indeed, it is found that a large surface charge is created, which can exceed the critical electric field that can be supported by the insulating passivation layer which is then deteriorated (breakdown), causing malfunctions of the integrated circuit. We also observe phenomena of electrostatic discharges generally qualified as ESD ("Electrostatic discharge") establishing conductive wells through the thickness of the circuit. In other cases, electrical charges are trapped in the passivation insulating layer causing a drift in the operating parameters of the circuit.

It should be noted in this respect that, unlike surface analysis systems (microscopic imaging by potential contrast called SEM, secondary ion mass spectroscopy (SIMS), etc.), in which beams with low incident energy can be used (in delayed mode), integrated circuit debugging systems require beams with high energy incident on the circuit to make etchings or deposits.

It is known that an ion beam focused on the surface of a target made of insulating or semiconductor material creates a charge increasing its electrical potential which deflects the beam. One of the techniques (known as "FLOODGUN") used to overcome this problem consists in sending a low energy electron beam to the point of impact of the ion beam. Another technique used consists in previously depositing an antistatic layer on the insulating passivation layer. US-4,639,301 and US-4,874,947 and the publication "Electrical

Biasing and Voltage Constrast Imaging in a Focused Ion Beam System ", AN Campbell et al, ISTFA'95, 21st International Symposium For Testing and Failure Analysis, 6-10 Nov. 1995, Santa Clara, California, describe devices in which a beam Low energy electron is used to neutralize the charge produced by an ion beam focused on an insulating or semiconductor target.

Nevertheless, the incorporation of these devices to generate such a low-energy electron beam in an FIB system for debugging integrated circuits considerably increases the cost of this system and increases its complexity of manufacture and use. In addition, with such an electron beam, a plasma is created above the surface of the integrated circuit, which can also modify its electronic characteristics.

In addition, when using a neutralizing electron beam, it is not possible to detect secondary electrons and it is preferable to use imaging means detecting secondary ions (SIM) much less specific. The deposition of an antistatic layer requires preliminary steps for preparing the circuit and subsequent steps for removing the antistatic layer.

Thus, since 1985, no solution has been found other than “FLOODGUN” and the deposition of an antistatic layer to the problem of the accumulation of charges on the surface.

Furthermore, FIB systems for debugging integrated circuits also come up against the problem of the accuracy of the deposits of materials made on the integrated circuit. In general, these deposits are made in the presence of gaseous organometallic species injected in the vicinity of the integrated circuit. However, it can be seen that the deposit does not remain strictly localized at the point of impact of the focused ion beam, and that a certain amount of material is deposited and spreads around this point of impact, according to a generally qualified phenomenon. "ONERSPRAY" (peripheral deposit), inevitable. However, this phenomenon locally modifies the electrical properties of the circuit and may even be responsible for serious malfunctions, for example when it occurs in the vicinity of the circuit connection pins. Thus, the presence of a metal deposit on the insulating passivation layer between two pins of the circuit can generate a leakage current, or even a short circuit between these pins.

US Pat. No. 5,683,547 describes a FIB system intended to ensure a uniform supply of gases in the vicinity of the surface to be treated and an observation of high contrast by detection of secondary electrons, comprising a plurality of gas injection nozzles, a micro-channel serving as secondary particle detector and one or more secondary electron extraction anodes. This document does not provide a solution to the above problems.

US-5 006 795 describes an electron beam microscope for measuring the dimensions of microscopic patterns of an electronic device. This document does not describe an FIB system, but a microscope of the so-called SEM type, in which the above-mentioned problems do not arise. This document recommends applying a voltage of the order of 4 to 10 V to the support or substrate of the chip, or placing them to ground by placing an electrode above the chip, in order to avoid phenomena. load affecting the accuracy of the measurement. However, this document does not provide any solution to the aforementioned problems of FIB systems whose beam is much more energetic and makes it possible to carry out not only microscopic observations, but also and above all micro-machining. It is indeed well known to those skilled in the art that the solutions adopted in the SEM systems cannot be directly transposed to the FIB systems. These systems differ from each other as much by the nature of the primary beams, by the energy levels implemented, by the conditions of implementation (presence of gas in the FIB systems), as by the problems to be solved. In addition, it should be noted that in a FIB system, the charge of the secondary electrons is opposite to that of the particles of the beam, while in an SEM system these charges are of the same sign. Thus, a polarization of the order of 4 to 10 V as described in this document is not suitable for avoiding the phenomena of accumulation of positive charges in an FIB system. Such polarization, by retaining the secondary electrons on the circuit, is moreover a priori harmful to the detection of the secondary electrons.

The invention therefore aims to overcome the aforementioned drawbacks and to propose a method and an installation for debugging integrated circuits using a beam of positive ions focused at high incident energy, in which all modifications are avoided and / or untimely damage to the integrated circuit.

The invention aims in particular to make it possible to avoid breakdowns or electrostatic discharges through the insulating layer of passivation or through the thickness of the integrated circuit, as well as the drifts of the operating parameters due to the accumulation of charges on the surface of the circuit, without having to use a low energy electron beam ("FLOODGUN" ). The invention further aims to improve the precision of deposits of conductive material assisted by an ion beam focused on an integrated circuit, and in particular to avoid the phenomena of peripheral deposits "OVERSPRAY".

The invention further aims to achieve these goals in a simple and inexpensive manner, and under these conditions compatible with exploitation on an industrial scale in the manufacturing processes of integrated circuits.

To do this, the invention relates to a method for correcting faults in integrated circuits of the type formed from a semiconductor substrate, from a plurality of layers of semiconductor and / or conductive materials suitable for performing electronic functions on pins. of connection of the integrated circuit, and of an insulating passivation layer, in which a positive ion beam is used focused on a surface of the integrated circuit on the side of the insulating passivation layer with an incident energy greater than or equal to 20 keV adapted to be able to perform etching and / or deposition without mask in a localized submicrometric zone (that is to say of average size less than one micron) of the integrated circuit, and in which the surface of the integrated circuit is observed with means potential contrast imaging from secondary electrons comprising a detection anode placed near the surface of circuit i integrated, to create an electric field for the detection of secondary electrons, characterized in that one creates, immediately above the surface of the integrated circuit, a local electric field adapted to oppose the accumulation of cationic species on the surface of the integrated circuit without canceling the electric field of secondary electron detection, and this local electric field is maintained during the application of the ion beam on the surface of the integrated circuit.

The invention also extends to an installation for implementing a method according to the invention. The invention therefore relates to an installation comprising a vacuum chamber comprising a sample holder capable of carrying an integrated circuit whose defects must be corrected, means for forming a beam of positive ions focused on a surface of the integrated circuit on the side of the insulating passivation layer with an incident energy greater than or equal to 20 keV, adapted to allow etching and / or deposition without mask in a localized submicrometric area of the integrated circuit, and imaging means by potential contrast from the secondary electrons comprising a detection anode placed close to the surface of the integrated circuit, to create an electric field for detection of the secondary electrons, characterized in that it comprises means for creating, immediately above from the surface of the integrated circuit, a local electric field adapted to oppose the accumulation of species cationic on the surface of the integrated circuit without canceling the electric field of detection of secondary electrons, and to maintain this local electric field during the application of the ion beam on the surface of the integrated circuit.

The inventor has in fact found that by applying a local electric field during the application of the focused ion beam, it is possible to repel the positive electric charges which do not accumulate on the surface of the integrated circuit. In addition, the inventor has found that it is possible to create this local electric field by applying a high positive electrical potential to the pins of the circuit, without affecting the properties of the integrated circuit, in particular without modifying or deteriorating in any way. untimely electronic functions. Also, it is possible to conserve imaging means by detecting secondary electrons. It suffices to increase the voltage of the secondary electron detection electrode accordingly.

Furthermore, the invention makes it possible to avoid any phenomenon of peripheral deposits ("OVERSPRAY"), the deposits of materials being essentially limited to the zone corresponding to the point of impact of the focused ion beam. It can be seen that these phenomena are completely eliminated, probably because the dispersion of the deposit around the point impact, was due, in the prior art, to positive ions resulting from the interactions between the organometallic species and the surface of the integrated circuit.

Advantageously and according to the invention, said local electric field is oriented at least substantially perpendicular to the surface of the integrated circuit. Advantageously and according to the invention, the amplitude of said fixed local electric field is maintained for at least part - notably the major part - of the duration of application of the ion beam on the surface of the integrated circuit. As a variant or in combination, advantageously and according to the invention, the amplitude of the local electric field is varied over time, in particular according to a predetermined variation profile.

Advantageously, the invention also relates to a method in which a beam of positive ions emitted with an acceleration voltage Uac defined with respect to a ground potential is used, and which is characterized in that it is applied to all the pins for connecting the integrated circuit to the same positive electrical potential Vb of between 0.1 kV and Uac-Ui, where Ui is the electrical voltage corresponding to the incident energy of the beam on the integrated circuit, and the rest of the integrated circuit is isolated from any source of potential, including mass potential.

As a variant or in combination, an negative or zero electrical potential Vc which is between - (Uac-Ui) and the potential is applied to an electrode, called the extraction cathode, placed immediately above the surface of the integrated circuit. massive. Preferably and according to the invention, in this variant, an electrical potential Vb greater (in relative value) than Vc is also applied to all the connection pins of the integrated circuit and the rest of the integrated circuit is isolated from any source of potential, including mass potential.

Throughout the text, the positive, negative or zero potentials are defined with respect to the ground potential with respect to which the acceleration voltage Uac is defined. This mass potential is that of an installation frame.

In a method according to the invention, a local electric field is thus directed above the surface of the integrated circuit so as to to oppose the accumulation of cationic species on the surface of the integrated circuit. This local electric field can be obtained by virtue of a positive electrical potential Vb applied to the pins of the integrated circuit, which causes a polarization of the surface of the insulating layer of the integrated circuit to a positive potential corresponding to Vb. As a variant or in combination, this local electric field is obtained by an extraction cathode.

Similarly, the invention also relates to an installation in which the means for forming the beam of positive ions are adapted to emit this beam with an acceleration voltage Uac defined with respect to a ground potential, and which is characterized in what it includes means for electrically connecting all the connection pins of the integrated circuit to the same positive electrical potential Vb between 0, lkV and Uac-Ui, where Ui is the electrical voltage corresponding to the incident energy of the beam on the integrated circuit, and means for isolating the rest of the integrated circuit from any source of potential, in particular ground potential.

As a variant or in combination, the installation comprises an electrode, called an extraction cathode, placed immediately above the surface of the integrated circuit, and means for applying to this extraction cathode a negative or zero electrical potential Vc included between - (Uac-Ui) and the mass potential. In this variant, advantageously and according to the invention, the installation also includes means for applying an electrical potential Vb greater (in relative value) to Vc, and means for isolating the rest of the integrated circuit from any source of potential, in particular of mass potential.

In the first variant, and according to the invention, the method is characterized in that:

- the positive ion beam is emitted with an acceleration voltage Uac of at least 20.5 kV relative to the ground potential, and the beam is focused on the surface of the integrated circuit with an incident energy greater than or equal to 20 keV , - the same positive electrical potential Vb with a value between 500V and Uac -20kV is applied to all the pins of the integrated circuit, and the rest of the integrated circuit is isolated from any potential source, including mass potential.

In the first variant, advantageously and according to the invention, the installation is characterized in that it comprises:

- means for emitting the positive ion beam with an acceleration voltage Uac of at least 20.5 kV relative to the ground potential of the installation,

means for focusing the beam on the surface of the integrated circuit with an incident energy Ei greater than or equal to 20 keV,

- means for electrically connecting all the pins of the integrated circuit to the same fixed positive electrical potential Eb with a value between 500V and Uac-20kV, and means for isolating the rest of the integrated circuit from any source of fixed potential, in particular potential massive.

In the following, only the characteristics relating to the process are indicated. These characteristics also apply to an installation according to the invention, which comprises means for implementing the characteristics of the method according to the invention.

Advantageously and according to the invention, all the pins of the integrated circuit are connected to the positive terminal of the same source of continuous electrical voltage capable of delivering said electrical potential Vb, and the other terminal of which is connected to the ground potential.

Advantageously and according to the invention, the electrical potential Vb is between lkV and lOkV, and is in particular of the order of 4kV. Advantageously and according to the invention, the electrical potential Vb is fixed for at least part - notably the major part - of the duration of application of the beam on the integrated circuit. As a variant or in combination, and according to the invention, a fluctuating electric potential Vb is applied, that is to say that a variation is made according to a predetermined variation profile.

In addition, the invention simultaneously makes it possible to increase the acceleration voltage Uac of the ions, which is conventionally of the order of 30 kV in known devices, up to values greater than 50 kV, or even even greater than 100 kV. Knowing that the focusing of the ion beam, and therefore the precision of etching and / or deposition, is linked to this voltage, the invention allows also improve this accuracy.

In the second variant and according to the invention, a negative electrical potential Vc is applied to the extraction cathode such that -Vc (or the absolute value of Vc) is less than 10kV. In the case where the two variants are used in combination, and according to the invention, it is ensured that at each instant -Vc <Vb. More particularly and according to the invention, at each instant Vb + Vc≥500V.

Advantageously and according to the invention, the potential Vc is fixed for at least part - notably the major part - of the duration of application of the beam on the integrated circuit. As a variant, and according to the invention, a fluctuating electrical potential Vc is applied to the extraction cathode, that is to say that a variation is made according to a predetermined variation profile.

In addition, advantageously and according to the invention, the extraction cathode is placed between the integrated circuit and the detection anode of the imaging means.

Advantageously and according to the invention, a positive electrical potential Vr is applied to an electrode, called an extraction anode, placed immediately above the surface of the integrated circuit. Advantageously and according to the invention, Vr≤Vb. Advantageously and according to the invention, the extraction anode is in the form of a crown extending in a plane transverse to the beam, the extraction cathode is in the form of a crown extending in a plane transverse to the beam, the cathode extraction and the extraction anode are coaxial co-axial, the extraction cathode having the smallest radial dimensions and being arranged inside the extraction anode. Advantageously and according to the invention, a positive electrical potential Vs, preferably fixed, is applied to the detection anode, such that the difference Vs-Vb is equal to or greater than the nominal operating potential of the detection anode. In this way, there is no harm to the quality of the image formed by detection of the secondary electrons by potential contrast. Advantageously and according to the invention, Vs is chosen such that Vs-Vb> Vb— Vc.

Advantageously, the method according to the invention is also characterized in that the integrated circuit is placed on an isolated sample holder

10 electrically from the ground potential, inside a vacuum chamber, and in that the pins of the integrated circuit are electrically connected to a voltage source situated outside the vacuum chamber, by means of electrical connection passing through a wall of the vacuum chamber, these electrical connection means being electrically isolated from this wall. Thus, advantageously, in an installation according to the invention, the sample holder is carried by a wall of the vacuum chamber from which it is electrically isolated, and comprises electrical connectors receiving the pins of the integrated circuit, these connectors being electrically connected to a voltage source located outside the vacuum chamber by electrical connection means passing through a wall of the vacuum chamber, these electrical connection means being electrically isolated from this wall.

The invention also relates to a method and an installation characterized in combination by all or some of the characteristics mentioned above or below. Other objects, characteristics and advantages of the invention appear from the examples and from the following description which refers to the appended figures in which:

- Figure 1 is a diagram illustrating in axial section the main components of an installation according to the invention, - Figure 2 is a diagram illustrating for comparison the drift of the parameters of a bipolar transistor having undergone a process in accordance with the state of the prior art,

FIG. 3 is a diagram illustrating the absence of drift of the parameters of a bipolar transistor having undergone a method according to the invention,

FIG. 4 is a diagram illustrating an example of a variation profile over time of the electric potential Vb applied to the pins of an integrated circuit in a method according to the invention,

- Figure 5 is a diagram similar to Figure 1 showing another embodiment of the invention.

The installation represented in FIG. 1 is an installation for correcting faults in integrated circuits by a focused ion beam FIB of which

11 the main constituent elements are known in themselves and are therefore neither described nor shown in detail. Such an installation is, for example, an IDS P2X system marketed by the company SCHLUMBERGER (San José, CA 95110-1397, USA). Other similar installations are marketed by the companies FEI Company (Hillsboro, OR 97124-5830, USA) and MICRION Corporation (Peabody, MA 01960-7990, USA).

Such an installation comprises a column 1 for forming a beam of positive ions. This column 1 makes it possible to emit ions, to accelerate them with the appropriate energy and to focus the beam. It comprises a vacuum chamber 2 in the form of a column adapted to delimit a closed enclosure 3 and associated with means for producing a high vacuum (of the order of 10 ^"8 Torr, or 10 ^{" 6} Pa) in this enclosure 3. The walls of the vacuum chamber 2 are conductive (metallic) and define the ground potential of the installation.

Column 1 comprises, at one end, an ion source 4, for example a sample of gallium heated by a direct voltage coming from a generator 5 of a direct electric voltage.

The positive ions are extracted from the source 4 and accelerated by an extractor / accelerator device comprising at least one generator 6 of a continuous electrical voltage of acceleration Uac of fixed value but preferably adjustable, the negative terminal of which is connected to the walls of the vacuum chamber 2 and the positive terminal of which is connected to an acceleration electrode 7. Downstream of the acceleration electrode 7, the beam ions are emitted with an energy corresponding to the acceleration voltage Uac , which is greater than 20.5 keV, for example of the order of 30 keV, or 50 keV, or even more, according to a beam of axis 39.

A device 8, known per se, makes it possible to focus, orient and control the scanning of the ion beam emitted over an area to be treated. It includes one or more condensers and means for transverse deflection of the beam in two orthogonal directions transverse to the axis 39 of the beam (in X and in Y, the axis 39 representing the coordinates in Z). This device 8 is controlled as well as the entire installation by a computer system (not shown).

12 The beam of positive ions arrives at one end of the column 1 which is opposite, along the axis 39, to the ion source 4, and is equipped with a sash window 9, formed by an opening 29 which can leave pass the beam which can be opened or closed and closed in a vacuum-tight manner by a sliding screen 10, movable in translation and controlled by a motorized device 11.

The screen 10 comprises a light 28 which lets the beam pass when it is opposite the opening 29, and a solid shutter portion 30 adapted to close the opening 29 when it is opposite this opening 29 .

The sash window 9 opens into a second vacuum chamber 12 comprising a sample holder 13 capable of carrying an integrated circuit 14 placed on the path of the ion beam emerging from the sash window 9 of the column 1, that is to say say at least substantially centered on the axis 39 of the beam. The second vacuum chamber 12 is adapted to delimit a closed enclosure 15 and is associated with means for producing a secondary vacuum (of the order of 10 ^"6 Torr, or 10 ^{" 4} Pa) in this enclosure 15. The walls of the vacuum chamber 12 are conductive (metallic) and connected to the ground potential, that is to say to the walls of the vacuum chamber 2 of the column 1. The second vacuum chamber 12 comprises a first opening 16 receiving the end of column 1 by means of sealing means 17 preserving the vacuum in the enclosure 15. These sealing means 17 are adapted to allow relative transverse displacements of column 1 (in X and in Y) and possibly tilt (rotation around the transverse directions X and Y), and a micrometric motorized device (not shown) is provided to control the transverse position of the column 1 in the opening 16.

The vacuum chamber 12 comprises a second opening 18, opposite the first opening 16 in the axial direction 39 of the ion beam and of the column 1. This second opening 18 is closed, by means of sealing means 19 , by a plate 20 which is removably mounted relative to the vacuum chamber 12. This plate 20 thus constitutes a

13 removable wall of the vacuum chamber 12. It carries the sample holder 13.

The sample holder 13 is an integrated circuit support, of a type known per se, comprising a generally parallelepipedic insulating plastic body, female electrical connectors 40 adapted to receive pins 22 of the integrated circuit. These female electrical connectors 40 are extended by pins 21 for electrical connection. These pins

21 pass through the thickness of the plate 20 while being electrically insulated from this plate 20. To do this, the plate 20 is provided with bores passing through its thickness, filled with an insulating and leaktight material resistant to vacuum in the enclosure 15 Each hole is traversed by one of the pins 21 of the sample holder 13. The pins 21 project from the holes, outside the plate 20 and the enclosure 15 so as to be able to be electrically connected to suitable devices. as described below.

Thus, the sample holder 13 is carried by the plate 20 from which it is electrically isolated. The integrated circuit 14 is placed on this sample holder 13 and is disposed in the enclosure 15 with its free surface 23 on the side of its passivation insulating layer 24 oriented at least substantially in the transverse plane XY to receive the ion beam from column 1. The pins

22 for connection to the integrated circuit 14 are engaged in female connectors 40 of the sample holder 13 and electrically connected via these female connectors 40 to the corresponding pins 21 of the sample holder 13 which open and are accessible from outside the chamber. empty 12.

A DC voltage generator 25, placed outside the enclosure 15 of the vacuum chamber 12, has its negative terminal (cathode) electrically connected to the ground potential, that is to say to a wall of the vacuum chamber 12, and its positive terminal (anode) electrically connected to all the pins 21, in short circuit, which are connected to the connection pins 22 of the integrated circuit 14. This generator 25 is a voltage source capable of delivering a fixed or variable direct voltage, preferably adjustable, between 0.1 kV and Uac-Ui, where Ui is the electric voltage corresponding to the incident energy Ei of the ion beam on the integrated circuit 14, which is suitable for ability to perform etching and / or deposition without mask in a localized submicrometric area of the

14 integrated circuit 14.

Advantageously and according to the invention, Ei is greater than or equal to 20keV, Ui is greater than or equal to 20kV, Uac is greater than or equal to

20.5kV, and the direct voltage equal to the positive electrical potential Vb applied to pins 21 and to pins 22 of the integrated circuit, is between

500V and Uac-20kV. It should be noted that the rest of the integrated circuit 14 is isolated from any other source of potential, and in particular is not connected to the ground potential, unlike previous general practice.

The generator 25 is for example an adjustable DC voltage source between 500V and lOkV, so that Vb can be adjusted between lkV and lOkV, for example of the order of 4kV.

Vb is less than Uac. The Uac / Vb ratio is preferably between 3 and 50.

FIG. 4 is a diagram illustrating an example of a profile of variation of the potential Vb over time during the processing of an integrated circuit 14 by the ion beam.

In this figure, t0 is the instant of the start of the application of the beam, that is to say the start of the scanning of the beam over the area to be treated, controlled by the device 8 of column 1, and tfin is the instant of the end of the application of the beam, that is to say the end of the scanning (controlled by a voltage, called "blanking" voltage, of lateral deflection of the beam outside the surface 23 of the integrated circuit 14).

As we can see, we gradually increase the potential

Vb from tO to reach, at the end of a period t2, a maximum value Vbmax which is for example of the order of 4kV. Preferably, t2 is less than half the total duration of the beam processing of the circuit, that is to say at

(tfin-t0) / 2. In the example shown, advantageously and according to the invention, the growth of Vb from 0 to Vbmax is carried out in two successive stages, corresponding to different growth rates. In a first step, of duration tl, Vb is made to grow to a value Vbi with a growth rate adapted to avoid the progressive charge of the integrated circuit 14 under the effect of the ion beam. Through

15 example, tl is between ls and 5s, in particular of the order of 2s, and Vbi is between Vbmax / 2 and 3Vbmax / 4, in particular of the order of 2Vbmax / 3. Preferably, the growth of Vb during this first step is linear, although other types of growth curves can be envisaged. In a second step, of duration t2-tl, one increases Vb from Vbi to Vbmax with a lower growth speed than during the first step, to gradually reach Vbmax. In other words, t2 / tl is greater than Vbmax / Vbi. For example, t2 is between 5s and 15s, in particular of the order of 8s. Preferably, the growth of Vb during this second step is also linear, although other types of growth curves can be envisaged.

After the end of the application of the ion beam on the integrated circuit 14, that is to say from tfin, Vb is made to decrease progressively to 0V, over a duration t3, preferably linear. For example, t3 is between ls and 5s, in particular of the order of 2s.

The values of Vbi, Vbmax, tl, t2, t3 are adapted according to the nature of the integrated circuit 14 to be treated, in particular according to the thickness and the nature of its passivation insulating layer 24.

The installation further comprises immediately above the integrated circuit 14, inside the enclosure 15 of the vacuum chamber 12, at a distance from its free surface 23 which is between 0.5mm and 5mm, in particular of the order of 2 mm, an extraction cathode 26 in the form of a crown, centered on the axial direction 39 of the ion beam pierced in its center for the passage of the ion beam, and extending in the transverse plane XY perpendicular to the axis 39 of the ion beam, at least substantially parallel to the free surface 23 of the integrated circuit 14.

This extraction cathode 26 is electrically connected by a conductor 35 to a female connector 40 of the sample holder 13, itself extended by one of the pins 21 opening out to the outside of the vacuum chamber 12. This pin 21 is connected to the negative terminal of a generator 27 of DC electrical voltage, placed outside the enclosure 15 of the vacuum chamber 12. The positive terminal of this voltage generator 27 is connected to the ground potential,

16 that is to say to a wall of the vacuum chamber 12. In this way, the extraction cathode 27 is placed at a negative or zero electrical potential Vc corresponding to the voltage delivered by this generator 27, which is fixed or variable, preferably adjustable. This negative or zero electrical potential Vc is between -

(Uac-Ui) and the ground potential (OV), fixed or variable, preferably adjustable.

Preferably, and according to the invention, -Vc (absolute value of Vc) is less than 10kV.

In addition, -Vc is less than Uac. When Vc is not zero, the Uac-Vc ratio is preferably between 3 and 100.

Vb and Vc are adapted to create a local electric field immediately above the surface 23, parallel to the axis 39 of the beam and at least substantially perpendicular to the surface 23 of the integrated circuit 14, and capable of opposing the 'accumulation of cationic species on this surface 23. Preferably and according to the invention, to promote the passage and detection of secondary electrons -Vc <Vb. Even more preferably and according to the invention, Vb + Vc≥500V.

The installation also includes a detector 31 of the secondary electrons emitted, making it possible to obtain a microscopic image by potential contrast. The detector 31 comprises a detection anode 32 and a source 33 of fixed positive continuous electric voltage, adapted to apply a positive positive electrical potential Vs to the detection anode 32.

The voltage source 33 is preferably adjustable and is adapted so that Vs-Vb is equal to or greater than the nominal operating potential of the detection anode 32, which is conventionally of the order of

12kV. So, if Vb = 4kV, Vs = 16kV. In this way, the electric field remains of the order of the nominal electric field necessary for the operation of the detector.

31, in particular of the order of 12kV.

Preferably, Vs is chosen so that Vs-Vb> Vb-Vc> 0. In this way, the secondary electrons can pass through the central orifice of the extraction cathode 26 and be picked up by the detection anode 32, which makes it possible to obtain good image quality by the detector 31.

17 Furthermore, there is also provided, advantageously and according to the invention, an extraction anode 34, placed immediately above the surface 23 of the integrated circuit 14, and to which a positive electrical potential Vr is applied. This extraction anode 34 makes it possible to avoid the accumulation of negative charges on the surface 23 and in particular facilitates the extraction of the secondary electrons. The extraction anode 34 can be arranged at the same level and around the extraction cathode 26, which are both in the form of a crown, coplanar, coaxial, concentric. The extraction anode 34 is at the same distance from the surface 23 of the integrated circuit as the extraction cathode 26. The connection of the extraction anode 34 can be similar to that of the extraction cathode 26. The extraction anode 34 is thus connected by a conductor 36 to one of the female connectors 40 of the sample holder 13, itself extended by one of the pins 21 emerging outside the vacuum chamber 12 , which is connected to the positive terminal of a generator 37 of DC electrical voltage, placed outside the enclosure 15 of the vacuum chamber 12. The negative terminal of this generator 37 is connected to the ground potential, c that is to say to a wall of the vacuum chamber 12. In this way, the extraction anode 34 is placed at a positive electrical potential Vr corresponding to the voltage delivered by this generator 37, which is fixed or variable , preferably adjustable. Finally, the installation also includes one or more gas injector (s) 38, electrically connected to the ground potential, which makes it possible, depending on the gas used, to carry out selective deposits or etchings of metal layers or 'oxides. Such a gas injector 38 is movable (for example, parallel to the axis 39 of the beam as shown) to be brought closer to the integrated circuit 14 during the injection of the gas, the movements being controlled by an appropriate motorized device known per se . This gas injector 28 is connected to gas sources, outside the enclosure 15, in a conventional manner.

It should be noted that the extraction cathode 26 and the extraction anode 34 are interposed between the surface 23 of the integrated circuit and the detection anode 32 on the one hand, and the gas injector 38 on the other go.

The central orifice of the extraction cathode 26 is adapted to allow the passage of the ion beam over the area of the circuit to be treated and the

18 passage of the gas injection needle 38. The external diameter of the extraction anode 34 is adapted to cover at least substantially the entire surface 23 of the passivation insulating layer 24 of the integrated circuit 14.

In the embodiment of FIG. 5, the installation also includes the voltage source 25 enabling the positive potential Vb to be applied to all the pins of the circuit, and an electron source 41 placed above and in the immediate vicinity of the surface 23 of the integrated circuit 14. This source of electrons is for example formed of a filament 44 of conductive material such as tungsten placed in a closed chamber 45 with metal walls provided with an orifice 42 for the outlet of the oriented electrons towards the surface 23 of the integrated circuit 14 (more precisely towards the impact zone 43 of the ion beam on the integrated circuit 14). A current source 46 makes it possible to circulate an electric current in the filament 44 to heat it for the emission of electrons. In this embodiment, the potential Vb also serves to attract the electrons coming from the source 41 which at least partially neutralize the surface of the integrated circuit 14. It should be noted that this source of electrons 41 is much simpler than a electron gun such as a "FLOODGUN" but provides similar effects. The current source 46 can be controlled and adjusted from outside the chamber 12 to optimize the quantity of electrons emitted according to the electrical neutralization effect to be obtained on the surface 23 of the integrated circuit.

In this embodiment, the extraction anode 34 is eliminated in order to avoid attracting the neutralizing electrons to this anode. On the other hand, the extraction cathode 26 can be kept.

Examples:

With an installation according to the invention, as shown in FIG. 1, tests are carried out to determine the appearance of the phenomena of peripheral deposits ("OVERSPRAY"), electrostatic discharges (ESD), or parameter drifts. In all the tests, Uac = 30kV and Vs = 12kV were chosen.

For the phenomena of peripheral deposits, we deposit

19 under FIB on an integrated circuit 14 CMOS having an insulating passivation layer 24 of SiO 2 of 1.4 μm thick, a platinum track of 10 μm × 1 μm, (the ion beam being focused and scanned over this area of integrated circuit), the gas being (methylcyclopentadientyl) trimethyl platinum [(MeCp) PtMe ₃ ]. We observe by the means 31 of microscopic imaging (potential contrast from the secondary electrons), the appearance or not of a spot of conductive material around the main deposit of lOμmxlμm.

For the phenomena of electrostatic discharges, a CMOS integrated circuit is used having an insulating passivation layer of SiN ₄ (particularly sensitive to such phenomena) of 1.4 μm in thickness. An ion beam emitted with an intensity current of lOOpA is applied to an area of 25 μmx25 μm. Four successive scans are carried out, each scan having a duration of 25 ms, and being followed by a complete suppression of the beam by application of a "blanking" voltage deflecting the beams out of the integrated circuit.

The appearance or not of electrostatic discharge wells is observed by the means 31 of microscopic imaging.

Parameter drift is studied in CMOS technology and in bipolar technology. For CMOS technology, a CMOS transistor with a floating gate is used by establishing the characteristic curve Id = f (vg) (Id drain current; Vg gate voltage) before and after the application of an ion beam. For bipolar technology, a bipolar transistor is used and the short characteristic of the gain β is established: Ic = f (IB) (the collector current; IB basic current) before and after the application of a beam d 'ions with an emission current of 50pA, which is scanned over the entire surface of the transistor (150μm x 150μm for the bipolar transistor, and 25μm x 25μm for the CMOS transistor) for 5s.

In each test, the quality of the image provided by the means 31 of potential contrast microscopic imaging from the secondary electrons is also assessed. Five different tests are carried out, depending on the values given to Vb, Vc and Vr. In test 1, Vb = 0 and the cathode and the extraction anode 26, 34 are eliminated. This essay is therefore an essay

20 comparative representative of the state of the prior art. Tests 2 to 6 are in accordance with the invention.

The following table summarizes the results obtained.

(Comparative)

Trial 1 2 3 4 5 6

Vb (kV) 0 0.8 0.8 0.8 0.8 0

Vc (kV) - 0 - 0 -0.3 -0.3

Vr (kV) - - - 0 0.8 0.8

Ei (keV) 30 29.2 29.2 29.2 28.9 29.7

Task None None None No task No circular task task task circular task

"Overspray" thin conductive deposit of 20 μm non-conductive device of 2 to 3 μm

ESD Yes No No No No No

Drift Yes No No No No Yes parameters

CMOS

Drift Yes No No No No Yes parameters (figure 2) (figure 3) bipolar

Quality Good Average Average Good Excellent Excellent Image

As can be seen in FIGS. 2 and 3, the invention makes it possible to avoid the drift of the parameters of a bipolar transistor treated by a focused ion beam.

Tests 2 to 5 demonstrate that the invention makes it possible, simply and without "FLOODGUN", to avoid the phenomena of peripheral deposits, electrostatic discharges, and the drift of the parameters.

Tests 5 and 6 also show that the extraction anode 34 also has the effect of improving the quality of the image by promoting the passage of secondary electrons to the detector 31.

21

Claims

CLAIMS 1 / - Method for correcting faults in integrated circuits (14) of the type formed by a semiconductor substrate, a plurality of layers of semiconductor and / or conductive materials adapted to perform electronic functions on pins for connection of the integrated circuit, and an insulating passivation layer (24), in which a beam of positive ions focused on a surface (23) of the integrated circuit (14) is used on the side of the insulating layer (24) passivation with an incident energy greater than or equal to 20 keV suitable for being able to achieve etching and / or deposition without mask in a localized submicrometric area of the integrated circuit (14), and in which the surface (23) of the integrated circuit is observed ( 14) with means (31) of potential contrast imaging from the secondary electrons comprising a detection anode (32) placed near the surface (23) of the integrated circuit (14), for cr er an electric field for the detection of secondary electrons, characterized in that one creates, immediately above the surface (23) of the integrated circuit (14), a local electric field adapted to oppose the accumulation of species cationic on the surface (23) of the integrated circuit without canceling the electric field of detection of secondary electrons, and this local electric field is maintained during the application of the ion beam on the surface (23) of the integrated circuit.

2 / - Method according to claim 1, characterized in that the local electric field is oriented at least substantially perpendicular to the surface (23) of the integrated circuit.

3 / - Method according to one of claims 1 and 2, characterized in that the amplitude of the fixed local electric field is maintained for at least part of the duration of application of the ion beam on the surface (23 ) of the integrated circuit (14).

4 / - Method according to one of claims 1 to 3, characterized in that the amplitude of the local electric field is varied over time. 5 / - Method according to one of claims 1 to 4, wherein one uses a beam of positive ions emitted with an acceleration voltage Uac defined with respect to a ground potential, characterized in that one applies

22 on all the pins (22) for connecting the integrated circuit (14), the same positive electrical potential Vb of between 0.1 kV and Uac-Ui, where Ui is the electrical voltage corresponding to the incident energy of the beam on the integrated circuit (14) and the rest of the integrated circuit (14) is isolated from any potential source, in particular ground potential.

6 / - Method according to one of claims 1 to 5, characterized in that one applies to an electrode, called extraction cathode (26), placed immediately above the surface (23) of the integrated circuit (14 ), a negative or zero electrical potential Vc between - (Uac-Ui) and the ground potential. 11 - Method according to one of claims 5 and 6, characterized in that: the beam of positive ions is emitted with an acceleration voltage Uac of at least 20.5 kV, and the beam is focused on the surface ( 23) of the integrated circuit (14) with an incident energy greater than or equal to 20 keV,

- the same positive electrical potential Vb with a value between 500V and Uac-20kV is applied to all the pins (22) of the integrated circuit (14), and the rest of the integrated circuit is isolated from any potential source, in particular the potential of mass. 8 / - Method according to one of claims 5 to 7, characterized in that all the pins (22) of the integrated circuit (14) are connected to the positive terminal of the same source of electrical voltage (25) suitable for continuous delivering said electrical potential Vb, the other terminal of which is connected to ground potential.

9 / - Method according to one of claims 5 to 8, characterized in that Vb is between lkV and lOkV.

10 / - Method according to claim 9, characterized in that Vb is of the order of 4kV.

11 / - Method according to one of claims 6 to 10, characterized in that -Vc is less than lOkV. 12 / - Method according to one of claims 6 to 11, characterized in that -Vc <Vb.

13 / - Method according to claim 12, characterized in that

23 than Vb + Vc≥500V.

14 / - Method according to one of claims 1 to 13, characterized in that one applies to an electrode, said extraction anode (34), placed immediately above the surface (23) of the integrated circuit (14 ), a positive electrical potential Vr.

15 / - Method according to claim 13, characterized in that Vr≤Vb.

16 / - Method according to claim 6 and one of claims 14 and 15, characterized in that the extraction anode (34) is in the form of a crown extending in a plane transverse to the beam, in that the extraction cathode (26) is in the form of a crown extending in a plane transverse to the beam, and in that the extraction cathode (26) and the extraction anode (34) are coaxial co-axial, the cathode extraction (26) having the smallest radial dimensions and being arranged inside the extraction anode (34).

17 / - Method according to one of claims 5 to 16, characterized in that a positive electrical potential Vs is applied to the detection anode (32) such that the difference Vs-Vb is equal to or greater than the nominal potential of operation of the detection anode (32). 18 / - Method according to claims 5 and 17, characterized in that one chooses Vs such that Vs-Vb> Vb-Vc> 0.

19 / - Method according to one of claims 1 to 18, characterized in that the integrated circuit (14) is placed on a sample holder (13) electrically isolated from ground potential, inside a chamber vacuum (12), and in that the pins (22) of the integrated circuit (14) are electrically connected to a voltage source (25) situated outside the vacuum chamber (12), by means (21) of electrical connection passing through a wall (20) of the vacuum chamber (12) electrically isolated from this wall (20).

20 / - Method according to one of claims 1 to 19, characterized in that there is an electron source (41) above and in the immediate vicinity of the surface (23) of the integrated circuit (14) in view to neutralize it.

24 21 / - Installation for implementing a method according to one of claims 1 to 20, comprising a vacuum chamber (12) comprising a sample holder (13) capable of carrying an integrated circuit (14) the faults must be corrected, means (4, 5, 6, 7, 8) for forming a beam of positive ions focused on a surface (23) of the integrated circuit (14) on the side of the passivation insulating layer (24) with an incident energy greater than or equal to 20 keV, adapted to allow etching and / or deposition without mask in a localized submicrometric area of the integrated circuit (14), and means (31) for imaging by potential contrast from the secondary electrons comprising a detection anode (32) placed near the surface (23) of the integrated circuit, to create an electric field for detection of the secondary electrons, characterized in that it comprises means ( 13, 25, 26, 27) to create, immé diat above the surface (23) of the integrated circuit, a local electric field adapted to oppose the accumulation of cationic species on the surface (23) of the integrated circuit without canceling the electric field of detection of secondary electrons, and to maintain this local electric field during the application of the ion beam on the surface (23) of the integrated circuit.

22 / - Installation according to claim 21, characterized in that the local electric field is oriented at least substantially perpendicular to the surface (23) of the integrated circuit (14).

23 / - Installation according to one of claims 21 and 22, characterized in that the local electric field is of fixed amplitude.

24 / - Installation according to one of claims 21 to 23, characterized in that the local electric field is of amplitude variable over time.

25 / - Installation according to one of claims 21 to 24, wherein the means (4, 5, 6, 7, 8) for forming the beam of positive ions are adapted to emit this beam with an acceleration voltage Uac defined with respect to a ground potential, characterized in that it comprises means (13, 21, 25) for electrically connecting all the pins (22) for connection of the integrated circuit (14) to the same positive electrical potential Vb included Between

25 0, lkV and Uac-Ui, where Ui is the electric voltage corresponding to the incident energy of the beam on the integrated circuit (14), and means (13) for isolating the rest of the integrated circuit (14) from any source of potential, including mass potential. 26 / - Installation according to one of claims 21 to 25, characterized in that it comprises an electrode, called extraction cathode (26), placed immediately above the surface (23) of the integrated circuit, and means (26, 27, 35) for applying to this extraction cathode (26) a negative or zero electrical potential Vc between - (Uac-Ui) and the ground potential.

27 / - Installation according to one of claims 25 and 26, characterized in that it comprises:

- means (4, 5, 6, 7) for emitting the beam of positive ions with an acceleration voltage Uac of at least 20.5 kV relative to a ground potential of the installation,

- means (7, 8) for focusing the beam on the surface (23) of the integrated circuit (14) with an incident energy Ei greater than or equal to 20keV,

- means (13, 21, 25) for electrically connecting all the pins (22) of the integrated circuit (14) to the same positive electrical potential Vb with a value between 500V and Uac-20kV, and means (13) for isolating the rest of the integrated circuit from any potential source, in particular ground potential.

28 / - Installation according to one of claims 25 to 27, characterized in that said means (13, 21, 25) for electrically connecting all the pins (22) of the integrated circuit (14) to the same electrical potential Vb comprise a source (25) of direct electrical voltage whose positive terminal is electrically connected to the pins (22) of the integrated circuit and whose other terminal is connected to ground potential. 29 / - Installation according to one of claims 25 to 28, characterized in that Vb is between lkV and lOkV.

30 / - Installation according to claim 29, characterized in

26 what Vb is around 4kV.

31 / - Installation according to one of claims 26 to 30, characterized in that -Vc is less than lOkV.

32 / - Installation according to one of claims 26 to 31, characterized in that -Vc <Vb.

33 / - Installation according to claim 32, characterized in that Vb + Vc> 500V.

34 / - Installation according to one of claims 21 to 33, characterized in that it comprises an electrode, called extraction anode (34), placed immediately above the surface (23) of the integrated circuit (14) , and means (36, 37) for applying a positive electrical potential Vr to this extraction anode.

35 / - Installation according to claim 34, characterized in that Vr≤Vb. 36 / - Installation according to claim 26 and one of claims 34 and 35, characterized in that the extraction anode (34) is in the form of a crown extending in a plane transverse to the beam, in that the extraction cathode (26) is in the form of a crown extending in a plane transverse to the beam, in that the extraction cathode (26) and the extraction anode (34) are coaxial coplanar, the cathode d extraction (26) having the smallest radial dimensions and being arranged inside the extraction anode (34).

37 / - Installation according to one of claims 21 to 36, characterized in that it comprises means (33) capable of applying to the detection anode (32) a fixed electrical potential Vs such that the difference

Vs-Vb is equal to or greater than the nominal operating potential of the detection anode (32).

38 / - Installation according to claims 25 and 37, characterized in that the means (33) capable of applying to the detection anode the fixed electrical potential Vs are adapted so that Vs-Vb> Vb-Vc> 0.

39 / - Installation according to one of claims 21 to 37, characterized in that the sample holder (13) is carried by a wall (20) of the

27 vacuum chamber (12) from which it is electrically isolated, and comprises electrical connectors receiving the pins (22) of the integrated circuit (14) and electrically connected to a voltage source (25) located outside the vacuum chamber (12) by means (21) of electrical connection passing through a wall (20) of the vacuum chamber electrically isolated from this wall (20).

40 / - Installation according to one of claims 21 to 39, characterized in that it comprises an electron source (41) disposed above and in the immediate vicinity of the surface (23) of the integrated circuit for the purpose of neutralize.

28