EP1057255B1 - Method and circuitry for the transmission of signals - Google Patents
Method and circuitry for the transmission of signals Download PDFInfo
- Publication number
- EP1057255B1 EP1057255B1 EP99907512A EP99907512A EP1057255B1 EP 1057255 B1 EP1057255 B1 EP 1057255B1 EP 99907512 A EP99907512 A EP 99907512A EP 99907512 A EP99907512 A EP 99907512A EP 1057255 B1 EP1057255 B1 EP 1057255B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- circuit
- potential
- transistor
- earth
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01806—Interface arrangements
Definitions
- the invention relates to a method and Circuit arrangement for the transmission of signals from a Output of a first circuit to an input of a second circuit, the circuits of a first and a second operating voltage and a first and are applied to a second ground potential and wherein changeable between the ground potentials Differences in potential can occur.
- the object of the present invention is therefore a Method and a circuit arrangement for the transmission of Specify signals at which occurring variable Potential differences between the circuits do not increase Cause interference.
- the output of the first circuit with a controllable power source is provided, the current in Towards one with another potential charged circuit point flows and one to the Control point connected further current source controls whose flow towards the entrance of the others Circuit flows, and that the further potential is such is chosen between the output of the first circuit and the other potential on the one hand and the other Potential and the input of the second circuit on the other hand in the case of potential differences, one each Current and the further current-enabling voltage is present.
- the difference in potential that can be overcome with the invention is only by the permissible collector-emitter voltage the current sources at least partially forming transistors limited.
- Adequate current flow through the power sources is according to an embodiment of the invention Circuit arrangement ensures that the further Potential at least by the sum of the Emitter-collector voltage of a current source at least partially forming and with its emitter with the first Operating voltage applied transistor and the Base-emitter voltage of another power source at least partially forming transistor lower than that first operating voltage and at least by the sum of Collector-emitter voltage of the further current source forming transistor and the base-emitter voltage of one connected to the input of the second circuit Transistor is lower than the second operating voltage.
- the further potential at least by the sum of the Emitter-collector voltage of a current source at least partially forming and with its emitter with the first Ground potential applied transistor and the Base-emitter voltage of another power source at least partially forming transistor higher than that first ground potential and at least by the sum of the Collector-emitter voltage of the further current source forming transistor and the base-emitter voltage of one connected to the input of the second circuit Transistor is higher than the second ground potential.
- Circuit arrangement for generating the further potential leading the further potential Switching point via a diode with the ground potentials or the operating voltages.
- a preferred application of the invention Circuit arrangement is that the first circuit a control circuit and the second circuit one Power level of an electronic motor vehicle device is.
- FIGS and 2 Circuit arrangements can both be between complete assemblies are inserted, such as for example control units and power amplifiers, as well as parts of the circuits to be connected.
- the execution as additional circuitry is to be provided, for example, if an otherwise finished control unit, for example as integrated circuit is designed, a push-pull output stage having.
- FIGS and 2 the circuit arrangements according to the invention independently represented by the respective circuits to be connected.
- the signal emitted by a first circuit becomes a Input 1 supplied and is related to a ground GND1.
- the first circuit receives this part of the inventive circuit associated with the first circuit Circuit arrangement via a connection 2 a Operating voltage U1, which is also at ground potential GND1 related.
- An output 3 is not on either shown second circuit connectable and introduces Output signal that is at ground potential GND2 of the second Circuit is related.
- the shown Circuit arrangement via a connection 4 with the Operating voltage U2 of the second circuit connected.
- a transistor 9 is then connected, which together with the resistor 13 is a current source for the base current of the Transistor 12 forms.
- a resistor 10 ensures that when transistor 9 is blocked, transistor 12 also Is blocked.
- the transistor 12 forms together with one Resistor 15 is another power source supplied by the Collector current of the transistor 9 is controlled.
- Resistor 14 serves to securely block transistor 16 with non-conductive transistor 12.
- the collector current of the Transistor 16 causes a voltage drop on Load resistor 17, the output 3 can be removed.
- the potential GND3 has a value that indicates a current flow through the Transistors 9 and 12 allows a transmission which are preferably digital signals.
- the potential GND2 must be at least the sum of the Emitter-collector voltage of the transistor 9 and Base-emitter voltage of transistor 12 is lower than that Operating voltage U1 and at least the sum of the Collector-emitter voltage of the transistor 12 and Base-emitter voltage of transistor 16 is lower than that Operating voltage U2.
- the input is 1st via a resistor 21 with a as a current source working npn transistor 9 'connected.
- the voltage drop at its load resistor 10 ' controls the transistor 12 'formed further current source via a resistor 13'.
- the load resistor 14 'of the further current source via a resistor 15 'to ground potential GND2 related signal detachable, which via transistors 16 'and 22, which are provided with resistors 23, 24, 25, the output 3 is fed.
- the further potential GND3 ' is at 11' fed and should be at least around the above Differences over the two ground potentials GND1 and GND2 lie, but preferably at least about as high as that each be the highest operating voltage.
- Circuit arrangement in the motor vehicle can Operating voltage U2 briefly fail. With that at Reinstall the operating voltage power stages that can also be operated with U2 as soon as possible can be controlled is to generate the potential GND3 a circuit according to FIG. 4 is provided. With this one the circuit point 11 on the one hand as in the circuit Fig. 3, the ground potential GND1 supplied via a diode 18 and on the other hand the operating voltage U2 via a diode 26 and a capacitor 27. This causes during exposing U2 GND3 one in capacitor 27 stored negative value so that the power source 12 even if there is no operating voltage U2 signals forwarded, which then immediately after reinstalling the Operating voltage U2 via transistor 16 to output 3 to get redirected.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
- Networks Using Active Elements (AREA)
- Electronic Switches (AREA)
- Dc Digital Transmission (AREA)
Description
Die Erfindung betrifft ein Verfahren und eine Schaltungsanordnung zur Übertragung von Signalen von einem Ausgang einer ersten Schaltung zu einem Eingang einer zweiten Schaltung, wobei die Schaltungen von einer ersten und einer zweiten Betriebsspannung und einem ersten und einem zweiten Massepotential beaufschlagt sind und wobei zwischen den Massepotentialen veränderliche Potentialunterschiede auftreten können.The invention relates to a method and Circuit arrangement for the transmission of signals from a Output of a first circuit to an input of a second circuit, the circuits of a first and a second operating voltage and a first and are applied to a second ground potential and wherein changeable between the ground potentials Differences in potential can occur.
Bei der Übertragung von Signalen zwischen zwei Schaltungen, die zueinander einen Potentialversatz aufweisen, kann es zu Störungen der übertragenen Signale kommen. Ist beispielsweise in einem Kraftfahrzeug ein Steuergerät an einem anderen Massepunkt angeschlossen als die zugehörige Leistungsendstufe, so können erhebliche Potentialdifferenzen auftreten, so daß von dem Steuergerät zur Leistungsendstufe übertragene Signale gestört sein können. Der Potentialversatz kann sogar ein Mehrfaches der Betriebsspannung betragen, so daß selbst digitale Signale nicht mehr zuverlässig ausgewertet werden können.When transmitting signals between two circuits, that have a potential offset to one another, it may be Interferences of the transmitted signals come. Is for example, a control unit in a motor vehicle connected to a different ground point than the associated one Power output stage, so there can be significant potential differences occur so that from the control unit to the power output stage transmitted signals may be disturbed. The Potential offset can even be a multiple of that Operating voltage, so that even digital signals can no longer be reliably evaluated.
Aufgabe der vorliegenden Erfindung ist es daher, ein Verfahren und eine Schaltungsanordnung zur Übertragung von Signalen anzugeben, bei welcher auftretende veränderliche Potentialunterschiede zwischen den Schaltungen nicht zu Störungen führen.The object of the present invention is therefore a Method and a circuit arrangement for the transmission of Specify signals at which occurring variable Potential differences between the circuits do not increase Cause interference.
Diese Aufgabe wird bei dem erfindungsgemäßen Verfahren dadurch gelöst, daß vom Ausgang der ersten Schaltung ein von dem zu übertragenden Signal gesteuerter Strom zu einem mit einem weiteren Potential beaufschlagten Schaltungspunkt fließt und einen von dem Schaltungspunkt ausgehenden weiteren Strom steuert, der dem Eingang der zweiten Schaltung zugeführt wird, und daß das weitere Potential derart gewählt ist, daß zwischen dem Ausgang der ersten Schaltung und dem weiteren Potential einerseits und dem weiteren Potential und dem Eingang der zweiten Schaltung andererseits bei den auftretenden Potentialunterschieden jeweils eine den Strom und den weiteren Strom ermöglichende Spannung anliegt.This object is achieved in the method according to the invention solved in that one of the signal to be transmitted controlled current with one another potential applied circuit point flows and one originating from the node controls further current that the input of the second Circuit is supplied, and that the further potential is chosen such that between the output of the first Circuit and the other potential on the one hand and the further potential and the input of the second circuit on the other hand in the potential differences that occur one each enabling the current and the further current Voltage is present.
Bei der erfindungsgemäßen Schaltungsanordnung ist vorgesehen, daß der Ausgang der ersten Schaltung mit einer steuerbaren Stromquelle versehen ist, deren Strom in Richtung auf einen mit einem weiteren Potential beaufschlagten Schaltungspunkt fließt und eine an den Schaltungspunkt angeschlossene weitere Stromquelle steuert, deren Strom in Richtung auf den Eingang der weiteren Schaltung fließt, und daß das weitere Potential derart gewählt ist, daß zwischen dem Ausgang der ersten Schaltung und dem weiteren Potential einerseits und dem weiteren Potential und dem Eingang der zweiten Schaltung andererseits bei den auftretenden Potentialunterschieden jeweils eine den Strom und den weiteren Strom ermöglichende Spannung anliegt. Der mit der Erfindung überwindbare Potentialunterschied ist lediglich durch die zulässige Kollektor-Emitter-Spannung der die Stromquellen mindestens teilweise bildenden Transistoren begrenzt.In the circuit arrangement according to the invention provided that the output of the first circuit with a controllable power source is provided, the current in Towards one with another potential charged circuit point flows and one to the Control point connected further current source controls whose flow towards the entrance of the others Circuit flows, and that the further potential is such is chosen between the output of the first circuit and the other potential on the one hand and the other Potential and the input of the second circuit on the other hand in the case of potential differences, one each Current and the further current-enabling voltage is present. The difference in potential that can be overcome with the invention is only by the permissible collector-emitter voltage the current sources at least partially forming transistors limited.
Ein ausreichender Stromfluß durch die Stromquellen ist gemäß einer Ausgestaltung der erfindungsgemäßen Schaltungsanordnung dadurch gewährleistet, daß das weitere Potential mindestens um die Summe aus der Emitter-Kollektor-Spannung eines die Stromquelle mindestens teilweise bildenden und mit seinem Emitter mit der ersten Betriebsspannung beaufschlagten Transistors und der Basis-Emitter-Spannung eines die weitere Stromquelle mindestens teilweise bildenden Transistors niedriger als die erste Betriebsspannung und mindestens um die Summe der Kollektor-Emitter-Spannung des die weitere Stromquelle bildenden Transistors und der Basis-Emitter-Spannung eines mit dem Eingang der zweiten Schaltung verbundenden Transistors niedriger als die zweite Betriebsspannung ist.Adequate current flow through the power sources is according to an embodiment of the invention Circuit arrangement ensures that the further Potential at least by the sum of the Emitter-collector voltage of a current source at least partially forming and with its emitter with the first Operating voltage applied transistor and the Base-emitter voltage of another power source at least partially forming transistor lower than that first operating voltage and at least by the sum of Collector-emitter voltage of the further current source forming transistor and the base-emitter voltage of one connected to the input of the second circuit Transistor is lower than the second operating voltage.
Bei der Verwendung von Transistoren mit einem anderen Leitfähigkeitstyp wird dies dadurch erreicht, daß das weitere Potential mindestens um die Summe aus der Emitter-Kollektor-Spannung eines die Stromquelle mindestens teilweise bildenden und mit seinem Emitter mit dem ersten Massepotential beaufschlagten Transistors und der Basis-Emitter-Spannung eines die weitere Stromquelle mindestens teilweise bildenden Transistors höher als das erste Massepotential und mindestens um die Summe der Kollektor-Emitter-Spannung des die weitere Stromquelle bildenden Transistors und der Basis-Emitter-Spannung eines mit dem Eingang der zweiten Schaltung verbundenden Transistors höher als das zweite Massepotential ist. When using transistors with another Conductivity type this is achieved in that the further potential at least by the sum of the Emitter-collector voltage of a current source at least partially forming and with its emitter with the first Ground potential applied transistor and the Base-emitter voltage of another power source at least partially forming transistor higher than that first ground potential and at least by the sum of the Collector-emitter voltage of the further current source forming transistor and the base-emitter voltage of one connected to the input of the second circuit Transistor is higher than the second ground potential.
In weiteren Unteransprüchen aufgeführte vorteilhafte Weiterbildungen der erfindungsgemäßen Schaltungsanordnung sind auf Dimensionierungsangaben für das weitere Potential im Falle von jeweils positiven und negativen Betriebsspannungen der Schaltungen und der Verwendung von pnp- oder npn-Transistoren für die Stromquellen gerichtet.Advantageous mentioned in further subclaims Developments of the circuit arrangement according to the invention are on dimensioning information for further potential in the case of positive and negative Operating voltages of the circuits and the use of pnp or npn transistors directed for the current sources.
Bei einer Weiterbildung der erfindungsgemäßen Schaltungsanordnung ist vorgesehen, daß zur Erzeugung des weiteren Potentials ein das weitere Potential führender Schaltungspunkt über je eine Diode mit den Massepotentialen bzw. den Betriebsspannungen beaufschlagt ist.In a further development of the invention Circuit arrangement is provided that for generating the further potential leading the further potential Switching point via a diode with the ground potentials or the operating voltages.
Bei einer Anwendung der erfindungsgemäßen Schaltungsanordnung im Kraftfahrzeug kann die Betriebsspannung der Leistungsendstufen enthaltenden zweiten Schaltung kurzzeitig ausfallen. Damit beim Wiedereinsetzen der Betriebsspannung die Leistungsendstufen möglichst schnell wieder angesteuert werden können, ist bei einer anderen Weiterbildung der erfindungsgemäßen Schaltungsanordnung vorgesehen, daß zur Erzeugung des weiteren Potentials ein das weitere Potential führender Schaltungspunkt über einen Kondensator und eine erste Diode mit der Betriebsspannung einer der Schaltungen und über eine zweite Diode mit dem Massepotential der anderen Schaltung verbunden ist.When using the invention Circuit arrangement in the motor vehicle can Operating voltage of the second output stages containing power Circuit fail briefly. So when reinstalling the operating voltage, the power amplifiers if possible can be controlled quickly, is one other development of the invention Circuit arrangement provided that for generating the further potential leading the further potential Switching point via a capacitor and a first diode with the operating voltage of one of the circuits and over a second diode with the ground potential of the other circuit connected is.
Eine bevorzugte Anwendung der erfindungsgemäßen Schaltungsanordnung besteht darin, daß die erste Schaltung eine Steuerschaltung und die zweite Schaltung eine Leistungsstufe einer elektronischen Kraftfahrzeugeinrichtung ist.A preferred application of the invention Circuit arrangement is that the first circuit a control circuit and the second circuit one Power level of an electronic motor vehicle device is.
Die Erfindung läßt zahlreiche Ausführungsformen zu. Eine davon ist schematisch in der Zeichnung anhand mehrerer Figuren dargestellt und nachfolgend beschrieben. Es zeigt:
- Fig. 1
- ein erstes Ausführungsbeispiel mit einem pnp-Transistor als Stromquelle,
- Fig. 2
- ein zweites Ausführungsbeispiel mit einem npn-Transistor als Stromquelle,
- Fig. 3
- eine erste Schaltungsanordnung zur Erzeugung des weiteren Potentials und
- Fig. 4
- eine zweite Schaltungsanordnung zur Erzeugung des weiteren Potentials.
- Fig. 1
- a first embodiment with a pnp transistor as a current source,
- Fig. 2
- a second exemplary embodiment with an npn transistor as current source,
- Fig. 3
- a first circuit arrangement for generating the further potential and
- Fig. 4
- a second circuit arrangement for generating the further potential.
Gleiche Teile sind in den Figuren mit gleichen Bezugszeichen versehen.Identical parts are given the same reference symbols in the figures Mistake.
Die in den Figuren 1 und 2 dargestellten Schaltungsanordnungen können sowohl zusätzlich zwischen an sich vollständige Baugruppen eingefügt werden, wie beispielsweise Steuergeräte und Endstufen, als auch Teile der zu verbindenden Schaltungen sein. Die Ausführung als zusätzliche Schaltung ist beispielsweise vorzusehen, wenn ein ansonsten fertiges Steuergerät, das beispielsweise als integrierte Schaltung ausgeführt ist, eine Gegentaktendstufe aufweist. Der Übersichtlichkeit halber sind in den Figuren 1 und 2 die erfindungsgemäßen Schaltungsanordnungen unabhängig von den jeweils zu verbindenden Schaltungen dargestellt.The shown in Figures 1 and 2 Circuit arrangements can both be between complete assemblies are inserted, such as for example control units and power amplifiers, as well as parts of the circuits to be connected. The execution as additional circuitry is to be provided, for example, if an otherwise finished control unit, for example as integrated circuit is designed, a push-pull output stage having. For the sake of clarity, FIGS and 2 the circuit arrangements according to the invention independently represented by the respective circuits to be connected.
Das von einer ersten Schaltung abgegebene Signal wird einem Eingang 1 zugeführt und ist auf eine Masse GND1 bezogen. Wie die erste nicht dargestellte Schaltung erhält der dieser ersten Schaltung zugeordnete Teil der erfindungsgemäßen Schaltungsanordnung über einen Anschluß 2 eine Betriebsspannung U1, die ebenfalls auf das Massepotential GND1 bezogen ist. Ein Ausgang 3 ist an die ebenfalls nicht dargestellte zweite Schaltung anschließbar und führt ein Ausgangssignal, das auf Massepotential GND2 der zweiten Schaltung bezogen ist. Ferner ist die dargestellte Schaltungsanordnung über einen Anschluß 4 mit der Betriebsspannung U2 der zweiten Schaltung verbunden.The signal emitted by a first circuit becomes a Input 1 supplied and is related to a ground GND1. How the first circuit, not shown, receives this part of the inventive circuit associated with the first circuit Circuit arrangement via a connection 2 a Operating voltage U1, which is also at ground potential GND1 related. An output 3 is not on either shown second circuit connectable and introduces Output signal that is at ground potential GND2 of the second Circuit is related. Furthermore, the shown Circuit arrangement via a connection 4 with the Operating voltage U2 of the second circuit connected.
Bei dem Ausführungsbeispiel nach Fig. 1 gelangt das bei 1
zugeführte Signal über einen Widerstand 5 zu einem
Transistor 6, an dessen Arbeitswiderstand 7 das Signal in
invertierter Form ansteht. Über einen weiteren Widerstand 8
ist dann ein Transistor 9 angeschlossen, der zusammen mit
dem Widerstand 13 eine Stromquelle für den Basisstrom des
Transistors 12 bildet. Ein Widerstand 10 stellt sicher, daß
bei Sperrung des Transistors 9 der Transistor 12 ebenfalls
gesperrt ist. Der Transistor 12 bildet zusammen mit einem
Widerstand 15 eine weitere Stromquelle, die von dem
Kollektorstrom des Transistors 9 gesteuert wird. Ein
Widerstand 14 dient zur sicheren Sperrung des Transistors 16
bei nichtleitendem Transistor 12. Der Kollektorstrom des
Transistors 16 bewirkt einen Spannungsabfall am
Arbeitswiderstand 17, der als Ausgangssignal dem Ausgang 3
entnommen werden kann.In the exemplary embodiment according to FIG. 1, this occurs at 1
supplied signal via a
Wird nun sichergestellt, daß für jeden auftretenden
Potentialunterschied zwischen GND1 und GND2 das Potential
GND3 einen Wert aufweist, der einen Stromfluß durch die
Transistoren 9 und 12 ermöglicht, kann auch eine Übertragung
der vorzugsweise digitalen Signale erfolgen. Insbesondere
muß das Potential GND2 mindestens um die Summe aus der
Emitter-Kollektor-Spannung des Transistors 9 und der
Basis-Emitter-Spannung des Transistors 12 niedriger als die
Betriebsspannung U1 und mindestens um die Summe der
Kollektor-Emitter-Spannung des Transistors 12 und der
Basis-Emitter-Spannung des Transistors 16 niedriger als die
Betriebsspannung U2 sein. It is now ensured that for everyone occurring
Potential difference between GND1 and GND2 the potential
GND3 has a value that indicates a current flow through the
Um eine Übertragung mit der an sich gewünschten Amplitude
der digitalen Signale sicherzustellen, die weitgehend der
Betriebsspannung entspricht, ist jedoch ein Potential GND3
erforderlich, das im wesentlichen nicht oberhalb des jeweils
niedrigsten der Massepotentiale GND1 und GND2 liegt. Ein
solches Potential kann mit der Schaltungsanordnung nach Fig.
3 erzeugt werden, die von zwei Dioden 18, 19 gebildet wird,
die jeweils zwischen GND1 bzw. GND2 und dem Schaltungspunkt
11 angeordnet sind.To transmit with the desired amplitude
to ensure the digital signals, which largely the
Operating voltage corresponds, but is a potential GND3
required, which is essentially not above each
lowest of the ground potentials GND1 and GND2. On
Such potential can be achieved with the circuit arrangement according to FIG.
3 are generated, which is formed by two
Bei der Schaltungsanordnung nach Fig. 2 ist der Eingang 1
über einen Widerstand 21 mit einem als Stromquelle
arbeitenden npn-Transistor 9' verbunden. Der Spannungsabfall
an dessen Arbeitswiderstand 10' steuert die vom Transistor
12' gebildete weitere Stromquelle über einen Widerstand 13'.
Am Arbeitswiderstand 14' der weiteren Stromquelle ist dann
über einen Widerstand 15' das auf das Massepotential GND2
bezogene Signal abnehmbar, das über Transistoren 16' und 22,
die mit Widerständen 23, 24, 25 versehen sind, dem Ausgang 3
zugeführt wird. Das weitere Potential GND3' wird bei 11'
zugeführt und soll mindestens um die oben angegebenen
Unterschiede über den beiden Massepotentialen GND1 und GND2
liegen, vorzugsweise jedoch mindestens etwa so hoch wie die
jeweils höchste Betriebsspannung sein.2, the input is 1st
via a resistor 21 with a as a current source
working npn transistor 9 'connected. The voltage drop
at its load resistor 10 'controls the transistor
12 'formed further current source via a resistor 13'.
Then at the load resistor 14 'of the further current source
via a resistor 15 'to ground potential GND2
related signal detachable, which via
Bei einer Anwendung der erfindungsgemäßen
Schaltungsanordnung im Kraftfahrzeug kann die
Betriebsspannung U2 kurzzeitig ausfallen. Damit beim
Wiedereinsetzen der Betriebsspannung Leistungsendstufen, die
ebenfalls mit U2 betrieben werden, möglichst schnell wieder
angesteuert werden können, ist zur Erzeugung des Potentials
GND3 eine Schaltung gemäß Fig. 4 vorgesehen. Bei dieser wird
dem Schaltungspunkt 11 einerseits wie bei der Schaltung nach
Fig. 3 das Massepotential GND1 über eine Diode 18 zugeführt
und andererseits die Betriebsspannung U2 über eine Diode 26
und einen Kondensator 27. Dadurch wird bewirkt, daß während
des Aussetzens von U2 GND3 einen im Kondensator 27
gespeicherten negativen Wert annimmt, so daß die Stromquelle
12 auch bei fehlender Betriebsspannung U2 Signale
weiterleitet, die dann sofort nach Wiedereinsetzen der
Betriebsspannung U2 über den Transistor 16 zum Ausgang 3
weitergeleitet werden.When using the invention
Circuit arrangement in the motor vehicle can
Operating voltage U2 briefly fail. With that at
Reinstall the operating voltage power stages that
can also be operated with U2 as soon as possible
can be controlled is to generate the potential
GND3 a circuit according to FIG. 4 is provided. With this one
the
Claims (11)
- Method for transmitting signals from an output of a first circuit to an input of a second circuit, the circuits having a first and a second operating voltage and a first and a second earth potential applied to them, and it being possible for variable potential differences to occur between the earth potentials, characterized in that a current controlled by the signal which is to be transmitted flows from the output of the first circuit to a circuit point having a further potential applied to it and controls a further current which starts from the circuit point and is supplied to the input of the second circuit, and in that the further potential is chosen in such a way that a voltage enabling the current and the further current is in each case, present between the output of the first circuit and the further potential, on the one hand, and between the further potential and the input of the second circuit, on the other, for the potential differences that occur.
- Circuit arrangement for transmitting signals from an output of a first circuit to an input of a second circuit, the circuits having a first and a second operating voltage and a first and a second earth potential applied to them, and it being possible for variable potential differences to occur between the earth potentials, characterized in that the output of the first circuit is provided with a controllable current source (9, 13; 9', 13') whose current flows in the direction of a circuit point having a further potential applied to it and controls a further current source (12, 15; 12', 15') which is connected to the circuit point (11, 11') and whose current flows in the direction of the input of the further circuit, and in that the further potential is chosen in such a way that a voltage enabling the current and the further current is in each case present between the output of the first circuit and the further potential, on the one hand, and between the further potential and the input of the second circuit, on the other, for the potential differences that occur.
- Circuit arrangement according to Claim 2, characterized in that the further potential (GND3) is lower than the first operating voltage at least by the sum of the emitter/collector voltage of a transistor (9) which at least partly forms the current source and whose emitter has the first operating voltage applied to it, and the base/emitter voltage of a transistor (12) which at least partly forms the further current source, and is lower than the second operating voltage at least by the sum of the collector/emitter voltage of the transistor (12) which forms the further current source, and the base/emitter voltage of a transistor (16) which is connected to the input of the second circuit.
- Circuit arrangement according to Claim 2, characterized in that the further potential (GND3) is higher than the first earth potential at least by the sum of the emitter/collector voltage of a transistor (9') which at least partly forms the current source and whose emitter has the first earth potential applied to it, and the base/emitter voltage of a transistor (12') which at least partly forms the further current source, and is higher than the second earth potential at least by the sum of the collector/emitter voltage of the transistor (12') which forms the further current source, and the base/emitter voltage of a transistor (16') which is connected to the input of the second circuit.
- Circuit arrangement according to Claim 2, characterized in that the operating voltages are positive with respect to the earth potentials, in that the current source for the first circuit has a pnp-transistor (9) and has the first operating voltage applied to it, in that the input of the second circuit has a resistor (14) which has the second operating voltage applied to it, and in that the further potential essentially corresponds to the most negative of the earth potentials.
- Circuit arrangement according to Claim 2, characterized in that the operating voltages are positive with respect to the earth potentials, in that the current source for the first circuit has an npn-transistor (9') and has the first earth potential applied to it, in that the input of the second circuit has a resistor (14') which has the second earth potential applied to it, and in that the further potential essentially corresponds to the most positive of the operating voltages.
- Circuit arrangement according to Claim 2, characterized in that the operating voltages are negative with respect to the earth potentials, in that the current source for the first circuit has an npn-transistor and has the first operating voltage applied to it, in that the input of the second circuit has a resistor which has the second operating voltage applied to it, and in that the further potential essentially corresponds to the most positive of the earth potentials.
- Circuit arrangement according to Claim 2, characterized in that the operating voltages are negative with respect to the earth potentials, in that the current source for the first circuit has a pnp-transistor and has the first earth potential applied to it, in that the input of the second circuit has a resistor which has the second earth potential applied to it, and in that the further potential essentially corresponds to the most negative of the operating voltages.
- Circuit arrangement according to one of Claims 2 to 8, characterized in that, in order to produce the further potential, a circuit point (11) which carries the further potential has the earth potentials (GND1, GND2) or the operating voltages applied to it via a respective diode (18, 19).
- Circuit arrangement according to one of Claims 2 to 8, characterized in that, in order to produce the further potential, a circuit point (11) which carries the further potential is connected to the operating voltage of one of the circuits via a capacitor (27) and a first diode (26), and to the earth potential of the other circuit via a second diode (18).
- Circuit arrangement according to one of Claims 2 to 10, characterized in that the first circuit is a control circuit and the second circuit is a power stage in an electronic motor vehicle device.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19807393A DE19807393C1 (en) | 1998-02-21 | 1998-02-21 | Signal transmission method between circuits with different operating potentials |
| DE19807393 | 1998-02-21 | ||
| PCT/EP1999/000789 WO1999043082A1 (en) | 1998-02-21 | 1999-02-05 | Method and circuitry for the transmission of signals |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP1057255A1 EP1057255A1 (en) | 2000-12-06 |
| EP1057255B1 true EP1057255B1 (en) | 2001-07-18 |
Family
ID=7858545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP99907512A Expired - Lifetime EP1057255B1 (en) | 1998-02-21 | 1999-02-05 | Method and circuitry for the transmission of signals |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6400181B1 (en) |
| EP (1) | EP1057255B1 (en) |
| KR (1) | KR20010041161A (en) |
| DE (2) | DE19807393C1 (en) |
| ES (1) | ES2161092T3 (en) |
| MY (1) | MY133020A (en) |
| WO (1) | WO1999043082A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10359236B3 (en) * | 2003-12-17 | 2005-05-25 | Siemens Ag | Arrangement for testing power end stage switches semiconductor switch(es) to conducting state according to predefined program to test whether end stage output voltages are in defined tolerance range for respective switch states |
| DE112006003744T5 (en) | 2006-02-17 | 2009-01-02 | Mitsubishi Electric Corp. | Device for a vehicle and a communication interface circuit for use in this device |
| EP4002692A1 (en) * | 2020-11-11 | 2022-05-25 | Aptiv Technologies Limited | Communication circuit and method of transferring a data signal |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3370244A (en) | 1963-05-15 | 1968-02-20 | Martin Marietta Corp | Transistor amplifier temperature stabilization circuits |
| US3649851A (en) * | 1970-02-25 | 1972-03-14 | Gen Instrument Corp | High capacitance driving circuit |
| GB1460569A (en) | 1972-11-13 | 1977-01-06 | Rca Corp | Amplifier having constant current consumption |
| US3959666A (en) * | 1974-07-01 | 1976-05-25 | Honeywell Information Systems, Inc. | Logic level translator |
| US4764733A (en) | 1987-04-10 | 1988-08-16 | Cross Technology, Inc. | Asymmetrical dual input amplifier |
| DE8912984U1 (en) * | 1989-11-02 | 1990-03-29 | Siemens AG, 1000 Berlin und 8000 München | Interface circuit between two electrical circuits operated at different operating voltages |
| JPH077407A (en) * | 1993-02-08 | 1995-01-10 | Fujitsu Ltd | Semiconductor integrated circuit device |
-
1998
- 1998-02-21 DE DE19807393A patent/DE19807393C1/en not_active Expired - Fee Related
-
1999
- 1999-02-05 KR KR1020007009211A patent/KR20010041161A/en not_active Application Discontinuation
- 1999-02-05 EP EP99907512A patent/EP1057255B1/en not_active Expired - Lifetime
- 1999-02-05 DE DE59900162T patent/DE59900162D1/en not_active Expired - Fee Related
- 1999-02-05 US US09/622,683 patent/US6400181B1/en not_active Expired - Fee Related
- 1999-02-05 ES ES99907512T patent/ES2161092T3/en not_active Expired - Lifetime
- 1999-02-05 WO PCT/EP1999/000789 patent/WO1999043082A1/en not_active Application Discontinuation
- 1999-02-12 MY MYPI99000508A patent/MY133020A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| US6400181B1 (en) | 2002-06-04 |
| DE19807393C1 (en) | 1999-06-02 |
| DE59900162D1 (en) | 2001-08-23 |
| ES2161092T3 (en) | 2001-11-16 |
| MY133020A (en) | 2007-10-31 |
| WO1999043082A1 (en) | 1999-08-26 |
| EP1057255A1 (en) | 2000-12-06 |
| KR20010041161A (en) | 2001-05-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE10020933B4 (en) | ASK modulator and communication device with an ASK modulator | |
| DE3100297C2 (en) | ||
| EP0093996B1 (en) | Level conversion circuitry | |
| DE2702022A1 (en) | AMPLIFIER CIRCUIT | |
| EP1057255B1 (en) | Method and circuitry for the transmission of signals | |
| DE3784310T2 (en) | BOOTSTRAP DRIVER CONTROL WITH HIGH SWITCHING SPEED. | |
| EP0334447B1 (en) | Schmitt-trigger circuit | |
| EP0698794A1 (en) | Under voltage detection circuit | |
| DE2524044C3 (en) | Universal link for the subnanosecond range | |
| EP0171125B1 (en) | Circuit arrangement for transmitting binary signals | |
| DE69003128T2 (en) | Drive circuit for semiconductor lasers. | |
| DE8912984U1 (en) | Interface circuit between two electrical circuits operated at different operating voltages | |
| DE3832378C1 (en) | ||
| DE2925040C2 (en) | Level shifter for binary logic signals | |
| EP0432280A1 (en) | Interface between two electrical circuits operating under different supply voltages | |
| EP0171468A2 (en) | Sending circuit for signal transmission systems | |
| EP0978025B1 (en) | Electronic circuit | |
| EP0632595A1 (en) | Line-driver-stage in current switch technology | |
| EP0093899B1 (en) | Circuit for matching test equipment with a test piece | |
| DE3437873C2 (en) | ||
| DE4410211B4 (en) | Circuit arrangement for the switchable control of a load | |
| EP0029480A1 (en) | Emitter follower logic circuit | |
| DE3021892C2 (en) | ||
| DE19535807C1 (en) | Bias potential generating circuit for bipolar circuit | |
| DE4112310C2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| 17P | Request for examination filed |
Effective date: 20000715 |
|
| AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE ES FR GB SE |
|
| GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
| GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
| GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
| 17Q | First examination report despatched |
Effective date: 20001227 |
|
| GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
| GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
| AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE ES FR GB SE |
|
| REF | Corresponds to: |
Ref document number: 59900162 Country of ref document: DE Date of ref document: 20010823 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20011018 |
|
| GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20011003 |
|
| REG | Reference to a national code |
Ref country code: ES Ref legal event code: FG2A Ref document number: 2161092 Country of ref document: ES Kind code of ref document: T3 |
|
| ET | Fr: translation filed | ||
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: IF02 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20020422 Year of fee payment: 4 |
|
| PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
| 26N | No opposition filed | ||
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20030206 Year of fee payment: 5 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: ES Payment date: 20030214 Year of fee payment: 5 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20030227 Year of fee payment: 5 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20030902 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20040205 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20040206 |
|
| GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20040205 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20041029 |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST |
|
| REG | Reference to a national code |
Ref country code: ES Ref legal event code: FD2A Effective date: 20040206 |