EP1042812A2 - Semiconductor substrate with embedded isolating layer for integrated circuits - Google Patents
Semiconductor substrate with embedded isolating layer for integrated circuitsInfo
- Publication number
- EP1042812A2 EP1042812A2 EP98966585A EP98966585A EP1042812A2 EP 1042812 A2 EP1042812 A2 EP 1042812A2 EP 98966585 A EP98966585 A EP 98966585A EP 98966585 A EP98966585 A EP 98966585A EP 1042812 A2 EP1042812 A2 EP 1042812A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- silicon
- integrated circuit
- trenches
- oxidation
- cmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 50
- 230000008569 process Effects 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 230000003071 parasitic effect Effects 0.000 claims abstract description 16
- 230000002829 reductive effect Effects 0.000 claims abstract description 15
- 230000036961 partial effect Effects 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims description 20
- 238000007254 oxidation reaction Methods 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 19
- 229910021426 porous silicon Inorganic materials 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 7
- 230000000873 masking effect Effects 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 8
- 230000002411 adverse Effects 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- -1 Polymers Chemical compound 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- the invention relates to an integrated circuit with reduced parasitic
- Bipolar technologies can be realized by using high impedance or
- Si substrates typically 1-10 ⁇ cm do not have the desired high inductance qualities
- CMOS complementary metal-oxide-semiconductor
- Dielectric constant than of silicon dioxide e.g. Polymers, as well as realization of the
- Bond islands which are also subject to parasitic capacitive influences, can be used.
- the object of the invention is to propose an integrated circuit with reduced parasitic capacitive influences and a method for its production, in which the
- This task is accomplished by a partial, at least 5 ⁇ m thick insulating layer
- Thickness of the buried insulation layer by approx. 40% and beyond that of planar ones
- An integrated circuit according to the invention takes place through the method steps
- circuit elements with reduced parasitic influences are generated above the region of the buried thick oxide.
- an integrated circuit according to the invention can also be implemented by the
- Fig. 1 shows a schematic structure of an inductor in plan view
- Fig. 2 shows a schematic section of an inductor
- Fig. 1 shows the schematic structure of an inductor as part of an inventive
- Integrated circuit in plan view, in Fig. 2 is a sectional view of the inductance
- the integrated inductor consists of an upper metal level 1 for implementation
- Channel stopper layer 6 a buried, thick local insulation layer 7 and the
- the field oxide layer 5 and the channel stop layer 6 are only located
- Insulation layer 7 is arranged only in the area of the inductance below the metal layers 1, 3.
- an etching mask is placed in a silicon wafer
- Range of integrated inductance to be realized in the subsequent process with one anisotropic etching process Trenches of about 10 ⁇ m depth are etched in such a way that trenches alternate
- the width of the webs and trenches is chosen so that one
- Insulation layer 7 the thickness of which is defined by the depth of the etched trenches.
- the CMOS process used in each case follows.
- the etching mask can already be used
- the porous silicon layer is set via the current strength-time product.
- the porosity is determined by the concentration of the
- the concentration of hydrofluoric acid is
- porous silicon layer will be based on the mass fractions, between 40% and 50%.
- Isolating layer that is limited to the area of the elements of the integrated circuit and local
- Resistors and capacitors but also for conductor tracks and bond islands.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19758349 | 1997-12-22 | ||
DE19758349 | 1997-12-22 | ||
DE19847440 | 1998-10-08 | ||
DE19847440A DE19847440A1 (en) | 1997-12-22 | 1998-10-08 | IC has a local, buried, thick insulation layer region for reducing parasitic capacitance effects |
PCT/DE1998/003794 WO1999033114A2 (en) | 1997-12-22 | 1998-12-18 | Semiconductor substrate with embedded isolating layer for integrated circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1042812A2 true EP1042812A2 (en) | 2000-10-11 |
EP1042812B1 EP1042812B1 (en) | 2007-05-09 |
Family
ID=26042909
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP98966585A Expired - Lifetime EP1042812B1 (en) | 1997-12-22 | 1998-12-18 | Method of making a semiconductor substrate with embedded isolating layer for integrated circuits |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1042812B1 (en) |
JP (1) | JP2001527292A (en) |
AT (1) | ATE362199T1 (en) |
DE (1) | DE59814004D1 (en) |
WO (1) | WO1999033114A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69936175T2 (en) * | 1998-11-04 | 2008-01-24 | Lucent Technologies Inc. | Inductance or low-loss trace in an integrated circuit |
JP4969715B2 (en) * | 2000-06-06 | 2012-07-04 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4910165A (en) * | 1988-11-04 | 1990-03-20 | Ncr Corporation | Method for forming epitaxial silicon on insulator structures using oxidized porous silicon |
US5548150A (en) * | 1993-03-10 | 1996-08-20 | Kabushiki Kaisha Toshiba | Field effect transistor |
JP3302228B2 (en) * | 1995-09-12 | 2002-07-15 | 株式会社東芝 | Method for manufacturing SOI substrate |
US5736749A (en) * | 1996-11-19 | 1998-04-07 | Lucent Technologies Inc. | Integrated circuit device with inductor incorporated therein |
-
1998
- 1998-12-18 AT AT98966585T patent/ATE362199T1/en not_active IP Right Cessation
- 1998-12-18 EP EP98966585A patent/EP1042812B1/en not_active Expired - Lifetime
- 1998-12-18 WO PCT/DE1998/003794 patent/WO1999033114A2/en active IP Right Grant
- 1998-12-18 JP JP2000525928A patent/JP2001527292A/en active Pending
- 1998-12-18 DE DE59814004T patent/DE59814004D1/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
---|
See references of WO9933114A3 * |
Also Published As
Publication number | Publication date |
---|---|
ATE362199T1 (en) | 2007-06-15 |
WO1999033114A3 (en) | 1999-08-19 |
DE59814004D1 (en) | 2007-06-21 |
WO1999033114A2 (en) | 1999-07-01 |
JP2001527292A (en) | 2001-12-25 |
EP1042812B1 (en) | 2007-05-09 |
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Free format text: METHOD OF MAKING A SEMICONDUCTOR SUBSTRATE WITH EMBEDDED ISOLATING LAYER FOR INTEGRATED CIRCUITS |
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