EP1025678A2 - Dispositif de consultation et procede de classement et d'acheminement de paquets - Google Patents

Dispositif de consultation et procede de classement et d'acheminement de paquets

Info

Publication number
EP1025678A2
EP1025678A2 EP98943155A EP98943155A EP1025678A2 EP 1025678 A2 EP1025678 A2 EP 1025678A2 EP 98943155 A EP98943155 A EP 98943155A EP 98943155 A EP98943155 A EP 98943155A EP 1025678 A2 EP1025678 A2 EP 1025678A2
Authority
EP
European Patent Office
Prior art keywords
output
stage
memory means
pointer
entry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98943155A
Other languages
German (de)
English (en)
Inventor
Peter SJÖDIN
Andreas Moestedt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sics Swedish Institute Of Computer Science AB
Original Assignee
SICS SWEDISH INST OF COMPUTER
SICS Swedish Institute of Computer Science
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SICS SWEDISH INST OF COMPUTER, SICS Swedish Institute of Computer Science filed Critical SICS SWEDISH INST OF COMPUTER
Publication of EP1025678A2 publication Critical patent/EP1025678A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/742—Route cache; Operation thereof

Definitions

  • the present invention relates to a lookup device and a method for classification and forwarding of packets.
  • IP router One of the main limiting factors for performance in an IP router, compared to a switch is often claimed to be the processing of incoming packets.
  • the packet classification operation consists of analysing information in the packet header (at least the destination address needs to be examined) , and performing a lookup operation to obtain the information required to forward the packet to its next hop.
  • the same kind of classification needs to be performed by a switch, but the operation is generally thought to be more complicated for an IP packet than for an ATM cell or an Ethernet frame.
  • the lookup operation consists of searching a database for an entry matching the packet.
  • the efficiency of a lookup operation depends on tne data structure used for the database. Data structures such as simple tables and linked lists are easy to implement, but have the drawback that they are difficult to search efficiently.
  • An interesting compromise between a simple table and a linked list is a trie.
  • the address is partitioned into a number of sections, and each section is used to address a different level of a search tree. At 5 each level, a number of small tables are used to store pointers to the appropriate tables on the next level. There is still wasted space within each of the tables, but only a partial tree need be created, covering the portions of the address space that are in use at any one time.
  • the 10 trie is most efficient when the utilized addresses are clustered in the address space.
  • Binary tries have also been used for variable length addresses, for example the commonly used Patricia trie, which is a refinement of a binary trie. But since IP 0 addresses are 32 bits long, a fast hardware implementation of Patricia tries is expensive and complex.
  • CAM Content Addressable Memory
  • the object of the present invention is to solve the above mentioned problems and to provide a lookup device
  • the input to the lookup device is a destination address of an incoming packet and the destination address comprises n bits, wherein n is an integer.
  • the lookup device comprises 1 stages, wherein each stage represents a predetermined prefix length and a prefix represents a group of addresses, wherein the first stage represents the shortest prefix length and the 1 : th stage represents the longest prefix length with n bits.
  • the lookup device also comprises a routing memory means connected to said ⁇ :th stage, wherein each stage comprises a memory means for storing a table of entries, wherein each entry comprises a pointer field which either comprises a pointer to the memory means in the next stage, or a pointer to the routing memory means storing the forwarding information, wherein a first number of bits corresponding to the shortest prefix length of the destination address are searched for in the first memory means, and if the entry in the first memory means wherein a match is found comprises a pointer to the second memory means, then a second number of bits corresponding to the next shortest prefix length of the destination address are searched for in the second memory means, and so on until a longest matching prefix has been found, wherein the pointer to the routing memory means gives the forwarding information for forwarding of said incoming packet.
  • this design is that it is capable of performing one lookup per memory cycle. Furthermore the design is simple and fast, and it is therefore suitable for a high-end IP router. This solution also works
  • the first stage comprises only saio first memory means, and all the other stages comprise eacn a logic means, wherein the (q-1) : th logic means is connected to both the (q+1) :th memory means and the q:th memory means, wherein q is an integer and l ⁇ q ⁇ -l.
  • each entry in the first (l-l) memory means also comprises a part bit and a valid bit
  • each entry in the ⁇ :th memory means also comprises a valid bit
  • a set valid bit in an entry represents a valid prefix and the pointer field for that entry comprises a pointer to the routing memory means
  • a set part bit in an entry in the q:th memory means means that the prefix matches an entry in the routing memory means, but is shorter than that entry, and the pointer field for that entry m the q:th memory means comprises a pointer to the (q+1) : th memory means.
  • each of the first (l-l) memory means has a pointer output, a valid bit output and a part bit output
  • the 1 : th memory means has a pointer output and a valid bit output
  • the pointer output of the q:th memory means is connected to the (q+1) : th memory means, and to the logic means of the (q+1) : th stage, and wherein the valid bit output and the part bit output of the q:th memory means are connected to the logic means of the (q+1 ) : th stage .
  • the logic means in the i : th stage comprises a multiplexer, an OR-gate, and an AND-gate, and each logic means in all the other stages but the first stage comprises a multiplexer, an OR-gate, a first AND- gate, and a second AND-gate, wherein the inputs of the multiplexer in the second stage are connected to the pointer outputs of the first and second memory means, and the inputs of the first AND-gate in the second stage are connected to the valid bit output of the second memory means and to the part bit output of the first memory means, and the inputs of the second AND-gate in the second stage are connected to the part bit outputs of the fist and second memory means, and the inputs of the OR-gate m the second stage are connected to an output from the first AND-gate in the second stage and to the valid bit output of the first memory means, wherein the inputs to the multiplexer in the p:th stage, wherein p is an integer and 3 ⁇ p ⁇ -l, are connected to the pointer output
  • each stage also comprises a decompression logic means, wherein the ⁇ :th decompression logic means is connected to the multiplexer in the ⁇ :th stage, and the q:th decompression logic means is connected to both the q:th memory means and to the (q+l):th memory means.
  • ⁇ :th decompression logic means is connected to the multiplexer in the ⁇ :th stage
  • q:th decompression logic means is connected to both the q:th memory means and to the (q+l):th memory means.
  • each entry in each memory means also comprises a mask field, an address tag field, and a compress flag bit, wherein a set compress flag bit indicates that compression is used, and in that each of the memory means also has a mask field output, an address tag field output, and a compress flag bit output, wherein the mask field output, the address tag field output, the compress flag bit output, and the pointer output of the r:th memory means is connected to the r:th decompression logic means, wherein r is an integer and l ⁇ r ⁇ i, and wherein each decompression logic means outputs a new pointer, wherein the new pointer output from the q:th decompression logic means is connected to the (q+l):th memory means and the new pointer output from the 1 : th decompression logic means is connected to the multiplexer of the l : th stage.
  • each decompression logic means comprises an AND-gate, a comparator, a first multiplexer, and a second multiplexer, wherein the inputs of the AND-gate in the r:th decompression logic means is connected to the mask field output of the r:th memory means and to the r:th prefix length of the destination address, and the inputs of the comparator in the r:th decompression logic means is connected to the address tag field output of the r:th memory means and to an output from the AND-gate in the r:th decompression logic means, and the inputs of the first multiplexer m the r:th decompression logic means is connected to the pointer output of the r:th memory means and to a logically 0-s ⁇ gnal, and the inputs of the second multiplexer in the r:th decompression logic means is connected to the output from the AND-gate in the r:th decompression logic means, and to an output from the comparator in the r:th decompression logic
  • Another object of the invention is to provide a method for classification and forwarding of packets, wherein a destination address of an incoming packet comprises bits, wherein n is an integer. This object is achieved by providing the method defined m the introductory part of Claim 10 with the advantageous features of the characterizing part of said Claim.
  • the method accordirg to the present invention comprises I stages, wherein each stage represents a predetermined prefix length and a prefix represents a group of addresses, wherein the first stage represents the shortest prefix length and the ⁇ :th stage represents the longest prefix length with n bits, wherein each stage comprises a table of entries, wherein each entry comprises a pointer field which either comprises a pointer to the table in the next stage, or a pointer to a routing table storing the forwarding information, wherein the method comprises the steps: to search for a first number of bits corrrespondmg to the shortest prefix length of the destination address in the first table; if the entry in the first table wherein a match is found comprises a pointer to the second table, to search for a second number of bits corresponding to the next shortest prefix length of the destination address in the second table; and so on until a longest matching prefix has been found, wherein the pointer to the routing table gives the forwarding information for forwarding of said incoming packet.
  • each entry in the first (i-l) tables also comprises a part bit and a valid bit
  • each entry in the l : th table also comprises a valid bit
  • a set valid bit in an entry represents a valid prefix
  • the pointer field for that entry comprises a pointer to the routing table
  • a set part bit in an entry in the q:th table means that the prefix matches an entry in the routing table, but is shorter than that entry
  • the pointer field for the entry in the q:th table comprises a pointer to the (q+1) :th table, wherein 1 is an integer and l ⁇ q ⁇ -l.
  • an entry in the first (i-l) tables is not allowed to both have a set valid bit and a set part bit.
  • a match is found when an entry in one stage comprises a set valid bit and all the matching entries of shorter prefix lengths are set part bits.
  • each entry in each table also comprises a mask field, an address tag field, and a compress flag bit, wherein a set compress flag bit indicates that compression is used
  • the method for the r:th table wherein r is an integer and l ⁇ r ⁇ i, also comprises the following steps : - to AND-process the mask field and the destination address bits corresponding to the r:th prefix length, giving masked destination address bits as output; if the compress flag bit is not set, to output a new pointer which is input to the q:th table, and which is input to the routing table for the l : th table, wherein the new pointer is formed by using the pointer from the (q- l):th table unchanged, with the destination address bits corresponding to the r:th prefix length as low order bits; or - if the compress flag bit is set, to output a new pointer which is input to the q:th table, and which is input to the routing table for the ⁇ :th table, wherein the new
  • Figure 1 shows a schematic diagram of the fields in an IP packet header
  • Figure 2 shows a schematic diagram of a prefix tree with 6-bit addresses using three prefix lengths according to the principle of the present invention
  • Figure 3 shows a block diagram of a lookup device according to the present invention
  • Figure 4 shows a block diagram of a decompression logic means forming part of the lookup device according to the present invention.
  • Figure 5 is a flow chart of the method according to the present invention. Detailed Description of Embodiments
  • FIG 1 there is disclosed a schematic diagram of the fields in an IP packet header.
  • the IP packet header comprises 12 different fields. As is disclosed in figure 1 these fields are: Version, IP Header Length, Type of Service, Total Length, Identification, Flags, Fragment Offset, Time to Live, Protocol, Header Checksum, Source Address, and Destination Address. It can also contain an Options field.
  • IP address lookup which is used for forwarding of unicast packets based on their destination address
  • identifier lookup which is intended to be used for, for example, forwarding of multicast packets and flows of packets.
  • the present invention is based on the IP address lookup .
  • a routing table entry for IP addresses has two fields; a prefix and a next hop address.
  • a prefix represents a group of addresses, and is given as an IP address prefix and a prefix length.
  • the IP prefix 193.10.66/234 represents all IP addresses whose 24 first bits are equal to 193.10.66. So a routing table entry for a given prefix applies to all addresses which are in the group covered by the prefix.
  • the principle for an address lookup is based on the longest matching prefix; with the destination address of an incoming IP packet as key, the routing table is searched for entries with matching prefixes. If there are more than one matching entry, the one with the longest prefix is chosen. By using this principle, it is always the most specific routing table entry that is picked. For example, consider a routing table with the following three entries : Prefix Next hop
  • FIG. 2 there is disclosed a schematic diagram of a prefix tree with 6-bit addresses using three prefix lengths according to the principle of the present invention.
  • the address space can be thought of as a tree, where the nodes represent prefixes. Each level in the tree represents a specific prefix length. Prefixes with other lengths than the ones used in the tree, have to be extended to several longer prefixes.
  • each node has one of two attributes, the first indicates if the node represents a valid prefix, corresponding to an entry in the routing table, the second indicates if it is part of a valid prefix, being a part means that the prefix matches an entry in the routing table, but is shorter than that entry (a prefix of a prefix), a node is not allowed to be both valid and part. If it is, the valid route has to be extended to the next length, marking all nodes of this length as valid. If none of the attributes are set, the node is said to be invalid. To find a matching route, the tree is searched from the shortest prefix until the first valid or invalid note is encountered. In this way the longest match is guaranteed to be found.
  • the three prefix lengths are 2, 4, and 6.
  • the matching entry is a part, resulting in a second lookup, "0101". This entry is also a part.
  • a last lookup "010110” is then performed, resulting in a valid entry.
  • This entry points into the routing table where the forwarding information is stored .
  • fewer prefix levels are used in the data structure, more memory is needed to store it. This is due to the bit extension up to a valid prefix length, and the need for all entries in a prefix group to be present.
  • every node that is the part attribute set will have 256 child nodes in its prefix group. But with fewer levels, a prefix is found with fewer memory accesses, making the lookup faster. The ideal choice of levels and the distance between, depends on what performance is needed, and how much memory can be used.
  • FIG 3 there is disclosed a block diagram of a lookup device according to the present invention.
  • the lookup device 30 is based on IP address lookup, which is used for forwarding of unicast packet based on their destination address.
  • the lookup device 30 comprises I stages 32 ⁇ , 322, ...32i. In this figure I is 4.
  • the first stage 32 ⁇ represents the shortest prefix length and the 4 : th stage 32 4 represents the longest prefix length with n bits.
  • the lookup device 30 also comprises a routing memory means connected to said 4 : th stage 32 4 .
  • Each stage 32 ⁇ , 32 2 , 32 3 , 32 4 comprises a memory means 36 ⁇ , 36 2 , 36 3 , 36 4 for storing a table of entries, wherein each entry comprises a pointer field which either comprises a pointer to the memory means in the next stage, or a pointer to the routing memory means 34 which stores the forwarding information.
  • the destination address is input to the lookup device 30 via a line 38.
  • a first number of bits corresponding to the shortest prefix length of the destination address are searched for in the first memory means 36 ⁇ , and if the entry in the first memory means 36 ⁇ wherein a match is foun ⁇ comprises a pointer to the second memory means 36 2 , then a second number of bits corresponding to the next shortest prefix length of the destination address are searched for in the second memory means 36 2 , and so on until a longest matching prefix has been found, wherein the pointer to the routing memory means 34 gives the forwarding information for forwarding of said incoming packet.
  • the first 32 2 , 32 , 32 4 each comprises a logic means 40 2 , 40 3 , 40 4 , wherein the ⁇ :th logic means is connected to both the 1 : th memory means and the (i-l) : th memory means.
  • Each entry in the 4 : th memory means 36 4 also comprises a valid bit
  • each entry in the 3 first memory means 36 x , 36 2 , 36 3 also comprises a part bit and a valid bit.
  • a set valid bit in an entry represents a valid prefix, and the pointer field for that entry comprises a pointer to the routing memory means 34.
  • Each of the three first memory means 36 ⁇ , 36 2 , 36 3 has a pointer output, a valid bit output and a part bit output.
  • the 4 : th memory means 36 4 has only a pointer output and a valid bit output.
  • the 4 : th logic means 40 4 comprises a multiplexer 42 4 , an OR-gate 44 4 and an AND-gate 46 4 .
  • Each logic means in all the other stages but the first stage (40 2 , 40 3 ) comprises a multiplexer 42 2 ; 42 3 , and an OR-gate 44 2 ; 44 3 , a first AND- gate 46 2 ; 46 3 and a second AND-gate 48 2 ; 48 3 .
  • the inputs of the multiplexer 42 2 are connected to the pointer outputs of the first and second memory means 36 x , 36 2 .
  • the inputs of the first AND-gate 46 2 are connected to the valid bit output of the second memory means 36 2 and to the part bit output of the first memory means 36 ⁇ .
  • the inputs of the second AND-gate 48 2 are connected to the part bit output of the first and second memory means 36 ⁇ , 36 2 .
  • the inputs of the OR-gate 44 2 are connected to an output of the first AND-gate 46 2 and to the valid bit output of the first memory means 36 ⁇ .
  • the inputs to the multiplexer in the p:th stage, wherein p is an integer and 3 ⁇ p ⁇ -l, are connected to the pointer output of the p:th memory means and to an output of the multiplexer of the (p-l):th stage.
  • the inputs of the first AND-gate in the p:th stage are connected to the valid bit output of the p:th memory means and to an output of the second AND-gate in the (p-1) : th stage.
  • the inputs of the second AND-gate in the p:th stage are connected to the partbit output of the p:th memory means and to the output of the second AND-gate in the (p- 1) : th stage.
  • the inputs of the OR-gate in the p:th stage are connected to the output of the first AND-gate in the (p-1) : th stage and to an output of the OR-gate in the (p- l):th stage.
  • the inputs of the multiplexer 42 4 are connected to the pointer output of the memory means 36 4 and to an output of the multiplexer 42 3 .
  • the inputs of the AND-gate 46 4 are connected to the valid bit output of the memory means 36 4 and to the output of the second AND-gate 48 3 .
  • the inputs of the OR-gate 44 4 are connected to the output of the AND-gate 46 4 and to the output of the OR- gate 44 3 .
  • the routing memory means 34 are connected to the outputs from the multiplexer 42 4 and the OR-gate 44 4
  • the part bit and the valid bit are used to determine when the longest match is found. In short, a match is found if an entry in one stage is valid and all the matching entries of shorter lengths are parts.
  • the pointer and the part and valid bits are sent from one stage to the next until all lengths have been examined.
  • the resulting router table pointer flows through the following stages, without being changed.
  • the multiplexer selects the pointer of its stage if the valid bit of that stage is set, and the part bit of all previous stages are set. If this is not true the multiplexer selects the output from the previous stage, i.e. sends the results on from an earlier hit.
  • FIG 4 there is disclosed a block diagram of a decompression logic means included in the lookup device according to the present invention.
  • decompression logic means 50 ⁇ each stage in the lookup device 30 (see figure 3) comprises a decompression logic means.
  • each decompression logic means 50 . ⁇ comprises an AND-gate 52 ⁇ , a comparator 54 ⁇ , a first multiplexer 56 ⁇ and a second multiplexer 58 ⁇ .
  • Each entry in each memory means 36 ⁇ , 36 2 , 36 3 , 36 4 also comprises a mask field, and address tag field, and a compress flag bit, wherein a set compress flag bit indicates that compression is used.
  • Each of the memory means 36 ⁇ , 36 2 , 36 3 , 36 4 also has a mask field output, an address tag field output, and a compress flag bit output.
  • the decompression logic means 50 ⁇ for the first stage.
  • the decompression logic means for the other stages are constructed in the same way and are not disclosed.
  • the inputs to the AND-gate 52 ⁇ are the mask field output and the first prefix length of the destination address.
  • the inputs to the comparator 54 ⁇ are the address tag field output and an output from the AND- gate 52 ⁇ .
  • the inputs to the first multiplexer 56 are the pointer output and a logically 0-s ⁇ gnal.
  • the inputs to the second multiplexer are the output from the AND-gate 52 ⁇ and an output from the comparator 54 ⁇ .
  • the decompression logic means 50 ⁇ outputs a new pointer, which is input to the second memory means 36 2 (see figure 3) .
  • the background to the design according to figure 4 is that a common case in sparse routing tables is that a prefix group only contains two different kinds of entries.
  • the first kind is one or several consecutive valid entries, all identical.
  • the second kind consists of all other entries in the group and are either invalid or valid. If they are valid, it is due to the extension of a shorter matching route, that the first kind of entries overlap.
  • Also needed is one bit to flag that the compression is to be done. Bits in the entries are saved by placing all the compressed tables in the low address range of the memory. By doing this, the high order address bits can instead be used as low order bits when addressing among the compressed tables.
  • the method begins at block 60.
  • the method comprises I stages, wherein each stage represents a predetermined prefix length and a prefix represents a group of addresses, wherein the first stage represents the shortest prefix length and the ⁇ :th stage represents the longest prefix length with n bits, wherein each stage comprises a table of entries, wherein each entry comprises a pointer field which either comprises a pointer to the table in the next stage, or a pointer to a routing table storing the forwarding information.
  • the method continues to search for a first number of bits corresponding to the shortest prefix length of the destination address in the first table.
  • the question is asked whether the entry in the first table wherein a match is found comprises a pointer to the second table. If the answer is affirmative the method continues with block 66, wherein a search is performed for a second number of bits corresponding to the next shortest prefix length of the destination address in the second table. Thereafter, at block 68, the question is asked whether the entry in the second table wherein a match is found comprises a pointer to the third table. If the answer is affirmative the method continues until a longest matching prefix has been found, wherein the pointer to the routing table, at block 70, gives the forwarding information for forwarding of said incoming packet. Then the method is completed at block 72. If the answer at block 64 or 68 is negative the method continues with block 70.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

La présente invention concerne un dispositif de consultation (30) et un procédé de classement et d'acheminement de paquets. Le dispositif de consultation (30) comporte un nombre i d'étages (321, 322, 323, 324), chaque étage (321, 322, 323, 324) représentant une longueur définie de préfixe, le préfixe représentant un groupe d'adresses. Le dispositif de consultation (30) comporte également un organe mémoire d'acheminement (34) connecté au ième étage (32¿4?), chaque étage (321, 322, 323, 324) comportant un organe mémoire (361, 362, 363, 364) permettant de stocker une table de rubriques. Chaque rubrique comporte une zone pointeur qui contient, soit un pointeur désignant l'organe mémoire de l'étage suivant, soit un pointeur désignant l'organe de mémoire d'acheminement (34) conservant les informations d'acheminement.
EP98943155A 1997-09-09 1998-09-07 Dispositif de consultation et procede de classement et d'acheminement de paquets Withdrawn EP1025678A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9703292A SE511972C2 (sv) 1997-09-09 1997-09-09 Uppslagningsanordning och förfarande för att klassificera och vidarebefordra datapaket
SE9703292 1997-09-09
PCT/SE1998/001584 WO1999013619A2 (fr) 1997-09-09 1998-09-07 Dispositif de consultation et procede de classement et d'acheminement de paquets

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EP1025678A2 true EP1025678A2 (fr) 2000-08-09

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EP98943155A Withdrawn EP1025678A2 (fr) 1997-09-09 1998-09-07 Dispositif de consultation et procede de classement et d'acheminement de paquets

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EP (1) EP1025678A2 (fr)
AU (1) AU9100898A (fr)
CA (1) CA2302744A1 (fr)
SE (1) SE511972C2 (fr)
WO (1) WO1999013619A2 (fr)

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US6975631B1 (en) * 1998-06-19 2005-12-13 Juniper Networks, Inc. Network packet forwarding lookup with a reduced number of memory accesses
GB9912129D0 (en) * 1999-05-26 1999-07-28 3Com Corp Communication device with forwarding database having having a trie search facility
SE9903460L (sv) * 1999-09-22 2001-03-23 Effnet Group Ab Metod och system för snabba routinguppslag
US6799202B1 (en) 1999-12-16 2004-09-28 Hachiro Kawaii Federated operating system for a server
GB2359693B (en) * 2000-02-26 2003-07-16 3Com Corp Network switch with truncated trie look-up facility
AU4737200A (en) * 2000-05-11 2001-11-20 Solidum Systems Corp. Packet classification state machine
JP2001326679A (ja) * 2000-05-15 2001-11-22 Fujitsu Ltd 情報装置、テーブル検索装置、テーブル検索方法、及び記録媒体
US6880064B1 (en) 2000-06-21 2005-04-12 Mosaid Technologies, Inc. Method and apparatus for physical width expansion of a longest prefix match lookup table
US6917954B2 (en) * 2001-05-30 2005-07-12 Mosaid Technologies, Inc. Load balancing in IP address lookup
GB2378622A (en) * 2001-08-11 2003-02-12 Zarlink Semiconductor Ltd Updating a lookup table used in mapping between TDM channels and packets
SE521907C2 (sv) * 2002-01-21 2003-12-16 Rockstorm Technologies Ab Metod och system för snabb IP-vägvalssökning för att fastställa vart ett IP-datagram med en given destinationsadress ska vidarebefordras

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US5206856A (en) * 1989-12-27 1993-04-27 Bell Communications Research, Inc. Routing of network traffic
US5365520A (en) * 1992-03-27 1994-11-15 Motorola, Inc. Dynamic signal routing

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Publication number Publication date
SE9703292L (sv) 1999-03-10
WO1999013619A3 (fr) 1999-06-03
AU9100898A (en) 1999-03-29
SE511972C2 (sv) 2000-01-10
CA2302744A1 (fr) 1999-03-18
SE9703292D0 (sv) 1997-09-09
WO1999013619A2 (fr) 1999-03-18

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