EP1019958A1 - Method for making a groove structure with a silicium substrate - Google Patents

Method for making a groove structure with a silicium substrate

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Publication number
EP1019958A1
EP1019958A1 EP98958161A EP98958161A EP1019958A1 EP 1019958 A1 EP1019958 A1 EP 1019958A1 EP 98958161 A EP98958161 A EP 98958161A EP 98958161 A EP98958161 A EP 98958161A EP 1019958 A1 EP1019958 A1 EP 1019958A1
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EP
European Patent Office
Prior art keywords
layer
oxide layer
substrate
oxide
polysilicon
Prior art date
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Granted
Application number
EP98958161A
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German (de)
French (fr)
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EP1019958B1 (en
Inventor
Stephan Bradl
Olaf Heitzsch
Michael Schmidt
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Infineon Technologies AG
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Infineon Technologies AG
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions

Definitions

  • the invention relates to a method for forming a trench structure in a silicon substrate according to the features of the preamble of claim 1.
  • Trench isolation technology (STI: Shallow Trench Isolation) has been proposed as an alternative to LOCOS technology.
  • trench isolation technology narrow trenches are etched into the monocrystalline silicon substrate and then filled with an insulating material. The filled trenches then act as space-saving electrical insulation barriers between active areas.
  • This technology is highly suitable for the electrical isolation of closely adjacent bipolar transistors as well as for p- and n-channel MOS transistors in CMOS circuits. Disadvantageous is, however, that the use of this technology requires a high level of process complexity and is therefore associated with high costs.
  • the high process expenditure is essentially due to the fact that after the trench has been filled with silicon dioxide, the trench course is transferred into the silicon dioxide layer and therefore a further leveling layer, for example a photoresist or a polysilicon layer, must be applied to the silicon dioxide layer, as a result of which the following planar removal of the layer results in flatness problems due to the different layer materials. These then have to be compensated for by additional processes in order to again obtain a planar substrate surface after removal of the silicon dioxide layer.
  • a further leveling layer for example a photoresist or a polysilicon layer
  • the present invention is based on the object of specifying a method with which a trench structure in a silicon substrate can be produced in the simplest and cheapest possible way.
  • the non-selectivity of the etching step defined in feature g) ensures that the flatness created in the previous chemical-mechanical polishing step (CMP: Chemical-Mechanical-Polishing) according to feature f) is maintained when the polysilicon material and oxide material are etched together until all polysilicon material is removed.
  • CMP Chemical-Mechanical-Polishing
  • a further polishing step is usually no longer required.
  • This procedure also allows the setting of a defined one Residual oxide layer thickness over the silicon, provided that the thickness of the previously deposited cover oxide layer was greater than the depth of the trench by more than the desired residual layer thickness.
  • the non-selective etching step is preferably a plasma etching step, NF 3 / N 2 / CHF 3 gases preferably being used as the etching gases.
  • a selective etching step for removing oxide material can advantageously be carried out. This makes it possible to set a predetermined distance between the surface of the silicon substrate and the surface of the trench oxide by etching the oxide deposited in the trench. This selective etch step can also be used to remove oxide material outside the trench.
  • 1 shows the sequence of process steps of a special method according to the prior art
  • 2 shows the sequence of process steps that occur in a first embodiment of the method according to the invention
  • FIG. 4 shows a scanning electron micrograph of a trench profile formed according to the invention after a selective wet oxide etching.
  • a thin thermal oxide layer (Si0 2 layer) 2 and an overlying, thicker nitride layer (Si 3 N) 3 are grown on a silicon substrate 1 (step 1).
  • a thin thermal oxide layer (Si0 2 layer) 2 and an overlying, thicker nitride layer (Si 3 N) 3 are grown on a silicon substrate 1 (step 1).
  • trenches 4, 5 of defined depth are introduced into the silicon substrate 1 by an etching process (step 2).
  • An intermediate oxide layer (not shown in FIG. 1) is then grown on the entire substrate 1, which serves as a base for an undoped TEOS oxide layer 6 (TEOS: tetraethyl-ortho-silicate) subsequently applied by means of gas phase deposition (step 3 ).
  • TEOS undoped TEOS oxide layer 6
  • Step 4 comprises the deposition of undoped polysilicon on the TEOS oxide layer 6 and a subsequent chemical mechanical polishing process (poly-CMP) to achieve a planar layer surface.
  • the polysilicon islands 7, 8 shown in FIG. 1 remain from the polysilicon layer. These islands 7, 8 are used as masks in a subsequent plasma etching step in order to selectively etch the unmasked TEOS layer regions 9, 10, 11 of the TEOS oxide layer 6 apart from a residual oxide layer 12 over the nitride layer 3. Then by another selective plasma etching step, the polysilicon islands 7, 8 are removed from the remaining structures 13, 14 of the TEOS oxide layer 6 (step 5).
  • oxide CMP chemical mechanical polishing process
  • Process (selectivity ⁇ 1: 4) must have a relatively large thickness (about 150 nm) (step 6).
  • the residual nitride layer 3 X is then selectively completely removed by a further etching step, so that the thin oxide layer 2 is exposed on the surface of the substrate 1. (Step 7).
  • FIG. 2 shows a first exemplary embodiment of the method according to the invention, the same elements as in FIG. 1 being provided with identical reference numbers.
  • the silicon substrate 1 is provided with a thin thermal silicon dioxide layer 2 and an overlying, thicker nitride layer 3 (step 1). Thereafter, the oxide layer 2, the nitride layer 3 and optionally also a further resist layer applied above and serving as a mask layer are patterned in a manner not shown, and a plasma etching is carried out with a defined depth into the silicon substrate 1 (step 2 X ).
  • a TEOS silicon dioxide layer 6 is then applied in step 3, a thin intermediate oxide layer possibly being applied beforehand in accordance with the description of step 3 in FIG. 1.
  • the deposited TEOS oxide layer 6 has an essentially conformal thickness, which means that even in narrow trench areas a layer thickness approximately according to the layer thickness over non-etched
  • a layer of undoped polysilicon is deposited on the TEOS oxide layer 6 and removed by chemical-mechanical polishing of the polysilicon (poly-CMP) down to the underlying TEOS oxide layer 6.
  • poly-CMP chemical-mechanical polishing of the polysilicon
  • the very good selectivity of the poly-CMP process between polysilicon and silicon dioxide, which is approximately 100: 1, is used.
  • the polishing step therefore stops exactly on the oxide and leaves a planar surface. All protruding polysilicon is removed, so that only the polysilicon islands 7, 8 remain (step 4 ⁇ ).
  • the depth of the trenches 4, 5 in the substrate is approximately 400 nm and the thickness of the nitride layer 3 is approximately 150 nm, so that a trench depth (defined as the distance between the trench bottom and the surface of the nitride layer 3) is approximately 550 nm results.
  • the thickness of the deposited TEOS oxide layer 6, measured over the non-etched, active substrate areas, can be greater than the trench depth (for example approximately 120% of the trench depth) if an “overfill” of the trenches is desired. Due to the conformity of the deposited TEOS oxide layer 6, however, a TEOS oxide layer thickness corresponding to the trench depth is generally sufficient.
  • a non-selective NF 3 / N 2 / CHF 3 plasma etching step is then carried out with almost the same etching rates for oxide and polysilicon.
  • the etching process is carried out at a high-frequency power of 800 watts without additional magnetic field and at a temperature of 20 ° C.
  • the recipient pressure is about 6 Pa and an etching gas with a composition (data in volume%) of 89.5% N 2;
  • the invention is not limited to a plasma etching step, but any etching process can be used as long as it has a selectivity that is sufficiently low to ensure that a planar surface is maintained during the removal of the layer.
  • Other components and compositions of the etching gas to be used are also possible.
  • the non-selective etching step can be carried out exactly until all the oxide material above the nitride layer 3 has been removed and a common planar one
  • Oxide / nitride surface 15, 16; 3 over the substrate 1 - as shown in FIG. 2 at step 5 ⁇ - is present.
  • a residual oxide layer with a planar surface and a defined thickness can be set over the active areas of the silicon substrate 1.
  • Another variant is to use a selective etching step to remove oxide after the non-selective plasma etching step.
  • This selective etching step makes it possible, on the one hand, to remove the addressed, if present, residual oxide layer above the silicon substrate 1 and, on the other hand, to further selectively etch the trench oxide 15, 16 to set a defined distance between the surface 17 of the substrate 1 """",
  • Trench oxide 15, 16 Because of the good selectivity, the low damage to the etched surface and the high uniformity, a wet etching step is particularly suitable for this.
  • Fig. 3 shows process steps l ⁇ to 5 ⁇ of a second embodiment of the method according to the invention. As was also the case with the first exemplary embodiment according to FIG. 2
  • the second exemplary embodiment essentially differs from the first exemplary embodiment only in that the nitride layer 3 is dispensed with. This is possible because (step 5 ⁇ and 5, respectively) is not taken the required in the known process according to Fig.l stop function of the nitride layer relative to the oxide polishing process (step 6) benö- in the present invention provided non-selective plasma etching.
  • the second exemplary embodiment offers the advantages that, by dispensing with the nitride layer 3, the layer deposition and layer removal steps required for this are omitted and the aspect ratio (ratio of trench depth to trench width) is reduced during trench etching and the required TEOS oxide layer thickness can be reduced.
  • the last-mentioned advantages can also be achieved in the first embodiment with nitride layer 3 if the Thickness of the nitride layer 3 is reduced in a suitable manner.
  • Table 1 shows typical values for the selectivities (S) and surface uniformity (GM) achieved with the polishing process (Poly-CMP) and with the non-selective plasma etching process.
  • the values for the selectivities in the non-selective plasma etching process are approximately 1 and are completely sufficient for uniform layer removal while maintaining flatness.
  • FIG. 4 shows a scanning electron microscope cross-sectional view of a trench in a substrate 1 with a thin thermal oxide layer 2 and CVD nitride layer 3 after the non-selective oxide-polysilicon plasma etching according to the invention.
  • the total thickness of the two layers is approximately 37 nm, the thickness of the nitride layer being approximately 32 nm.
  • the substrate was exposed to the selective wet oxide etching already described, as a result of which the surface level of the trench oxide is below the surface level of the substrate. covering nitride layer 3 was lowered. Accordingly, the G is 696 nm deep raven, while the distance between trench ⁇ ground and surface temperature is of the moat oxide 644 nm.

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Abstract

The invention relates to a method for making a groove structure in a silicium substrate in such a way that it can be used as an electric insulation of a first substrate area relative to a second substrate area. The method consists in vapour deposition of the thermal oxide layer on the substrate surface, followed by the application and structuration of a masking layer on said thermal oxide layer. The structured masking layer digs by corrosion a groove of a prescribed depth in the silicium substrate. Said groove is filled by precipitating a standard overall oxide layer on the substrate, the thickess of said oxide layer being virtually homogeneous and sufficient to fill the groove entirely. A polycrystalline silicone layer is then precipitated on the overall oxide layer, and a high-selective chemo-mechanical planarization is carried out between the polycrystalline silicone material and the oxide material so as to produce a flat surface. Another step aims to remove the layer by a joint, practically non selective corrosion of the polycrystalline silicone and the oxide, while maintaining the surface as flat as it was after the planarization process. The corrosion process is applied until total elimination of the polycrystalline silicone from the groove area.

Description

Beschreibungdescription
Verfahren zur Ausbildung einer Grabenstruktur in einem SiliziumsubstratMethod for forming a trench structure in a silicon substrate
Die Erfindung betrifft ein Verfahren zur Ausbildung einer Grabenstruktur in einem Siliziumsubstrat nach den Merkmalen des Oberbegriffs des Anspruchs 1.The invention relates to a method for forming a trench structure in a silicon substrate according to the features of the preamble of claim 1.
Durch die steigende Integrationsdichte bei Halbleiterbauelementen werden die Anforderungen an die elektrische Isolation von benachbarten aktiven Gebieten auf einem Halbleitersubstrat ständig höher. Bei der gegenwärtig zur Herstellung von integrierten Schaltungen in großem Umfang eingesetzten LOCOS-Technik (Local Oxidation of Silicon) wird die elektrische Isolation benachbarter MOS-Transistoren durch die lokalisierte Ausbildung eines Feldoxids erreicht. Bei diesem Verfahren kommt es im Übergangsbereich zwischen dem Feldoxid und dem Gateoxid zu der Ausbildung eines sogenannten Vogel- schnabels (bird beak) . Nachteilig an diesem Vogelschnabel ist, daß er aufgrund seiner lateralen Ausdehnung die für aktive Bereiche zur Verfügung stehende Halbleitersubstratfläche reduziert und somit bei Strukturen im Bereich von 0,35 μm oder darunter zu signifikanten Schwierigkeiten führt.Due to the increasing integration density in semiconductor components, the requirements for the electrical insulation of adjacent active areas on a semiconductor substrate are constantly increasing. In the LOCOS technology (Local Oxidation of Silicon) currently used extensively for the production of integrated circuits, the electrical isolation of adjacent MOS transistors is achieved by the localized formation of a field oxide. With this method, a so-called bird beak is formed in the transition area between the field oxide and the gate oxide. A disadvantage of this bird's beak is that, due to its lateral extension, it reduces the semiconductor substrate area available for active areas and thus leads to significant difficulties with structures in the range of 0.35 μm or less.
Als Alternative zur LOCOS-Technik ist die Grabenisolationstechnik (STI: Shallow Trench Isolation) vorgeschlagen worden. Bei der Grabenisolationstechnik werden schmale Gräben in das monokristalline Siliziumsubstrat geätzt und an- schließend mit einem isolierenden Material ausgefüllt. Die gefüllten Gräben wirken dann als platzsparende elektrische Isolationsbarrieren zwischen aktiven Bereichen. Diese Technik ist sowohl für die elektrische Isolation eng benachbarter Bipolartransistoren als auch von p- und n-Kanal-MOS-Transisto- ren in CMOS-Schaltungen in hohem Maße geeignet. Nachteilig ist jedoch, daß der Einsatz dieser Technik einen hohen Prozeßaufwand erforderlich macht und daher mit hohen Kosten verbunden ist.Trench isolation technology (STI: Shallow Trench Isolation) has been proposed as an alternative to LOCOS technology. In trench isolation technology, narrow trenches are etched into the monocrystalline silicon substrate and then filled with an insulating material. The filled trenches then act as space-saving electrical insulation barriers between active areas. This technology is highly suitable for the electrical isolation of closely adjacent bipolar transistors as well as for p- and n-channel MOS transistors in CMOS circuits. Disadvantageous is, however, that the use of this technology requires a high level of process complexity and is therefore associated with high costs.
Der hohe Prozeßaufwand ist im wesentlichen darauf zurückzuführen, daß nach dem Auffüllen des Grabens mit Siliziumdioxid der Grabenverlauf in die Siliziumdioxidschicht transferiert ist und daher eine weitere, einebnende Schicht, beispielsweise ein Photoresist oder eine Polysiliziumschicht, auf die Siliziumdioxidschicht aufgebracht werden muß, wodurch sich beim nachfolgenden planaren Abtragen der Schicht Ebenheitsprobleme aufgrund der unterschiedlichen Schichtmaterialien ergeben. Diese müssen dann durch zusätzliche Prozesse ausgeglichen werden, um nach Entfernung der Siliziumdioxidschicht wiederum eine planare Substratoberfläche zu erhalten.The high process expenditure is essentially due to the fact that after the trench has been filled with silicon dioxide, the trench course is transferred into the silicon dioxide layer and therefore a further leveling layer, for example a photoresist or a polysilicon layer, must be applied to the silicon dioxide layer, as a result of which the following planar removal of the layer results in flatness problems due to the different layer materials. These then have to be compensated for by additional processes in order to again obtain a planar substrate surface after removal of the silicon dioxide layer.
Der vorliegenden Erfindung liegt die Aufgabe zugrunde, ein Verfahren anzugeben, mit dem eine Grabenstruktur in einem Siliziumsubstrat auf möglichst einfachem und kostengünstigem Wege hergestellt werden kann.The present invention is based on the object of specifying a method with which a trench structure in a silicon substrate can be produced in the simplest and cheapest possible way.
Zur Lösung dieser Aufgabe sind die Merkmale des Anspruchs 1 vorgesehen.The features of claim 1 are provided to achieve this object.
Durch die Nichtselektivität des im Merkmal g) definierten Ätzschrittes wird erreicht, daß die in dem vorhergehenden chemisch-mechanischen Polierschritt (CMP: Chemical-Mechani- cal-Polishing) gemäß Merkmal f) geschaffene Ebenheit beim gemeinsamen Ätzen des Polysiliziummaterials und Oxidmaterials aufrechterhalten wird, bis sämtliches Polysiliziummaterial entfernt ist. Dadurch wird die gemeinsame Abtragung des Po- lysilizium- und Oxidmaterials durch einen einzigen, kostengünstigen Ätzschritt ermöglicht. Ein weiterer Polierschritt wird in der Regel nicht mehr benötigt. Ferner gestattet diese Vorgehensweise auch die Einstellung einer definierten Oxid-Restschichtdicke über dem Silizium, sofern die Dicke der zuvor abgeschiedenen Deckoxidschicht um mehr als die gewünschte Restschichtdicke größer als die Tiefe des Grabens war.The non-selectivity of the etching step defined in feature g) ensures that the flatness created in the previous chemical-mechanical polishing step (CMP: Chemical-Mechanical-Polishing) according to feature f) is maintained when the polysilicon material and oxide material are etched together until all polysilicon material is removed. This enables the polysilicon and oxide material to be removed together by a single, inexpensive etching step. A further polishing step is usually no longer required. This procedure also allows the setting of a defined one Residual oxide layer thickness over the silicon, provided that the thickness of the previously deposited cover oxide layer was greater than the depth of the trench by more than the desired residual layer thickness.
Vorzugsweise handelt es sich bei dem nichtselektiven Ätzschritt um einen Plasmaätzschritt, wobei als Ätzgase vorzugsweise NF3/N2/CHF3-Gase verwendet werden.The non-selective etching step is preferably a plasma etching step, NF 3 / N 2 / CHF 3 gases preferably being used as the etching gases.
In vorteilhafter Weise kann nach dem nichtselektiven Ätzschritt ein selektiver Ätzschritt zur Entfernung von Oxidmaterial durchgeführt werden. Dies gestattet es, durch Ätzung des im Graben deponierten Oxids einen vorgegebenen Abstand zwischen der Oberfläche des Siliziumsubstrats und der Ober- fläche des Grabenoxids einzustellen. Außerdem kann dieser selektive Ätzschritt zur Entfernung von Oxidmaterial außerhalb des Grabens verwendet werden.After the non-selective etching step, a selective etching step for removing oxide material can advantageously be carried out. This makes it possible to set a predetermined distance between the surface of the silicon substrate and the surface of the trench oxide by etching the oxide deposited in the trench. This selective etch step can also be used to remove oxide material outside the trench.
Grundsätzlich ist es bei dem erfindungsgemäßen Verfahren nicht erforderlich, eine Siliziumnitridschicht auf die thermische Oxidschicht aufzubringen, da die im Stand der Technik bei einem CMP-Schritt ausgenutzte Stoppwirkung der Siliziumnitridschicht hier nicht benötigt wird. Es kann jedoch aus anderen Gründen weiterhin zweckmäßig sein, eine Siliziumni- tridschicht vorzusehen, beispielsweise um diese als Maskenschicht für die Grabenätzung einzusetzen.In principle, it is not necessary in the method according to the invention to apply a silicon nitride layer to the thermal oxide layer, since the stop effect of the silicon nitride layer used in the prior art in a CMP step is not required here. However, for other reasons it can also be expedient to provide a silicon nitride layer, for example in order to use this as a mask layer for the trench etching.
Weitere bevorzugte Ausführungsvarianten der Erfindung sind in den Unteransprüchen angegeben.Further preferred embodiments of the invention are specified in the subclaims.
Die Erfindung wird nachfolgend in beispielhafter Weise anhand der Zeichnung beschrieben; in dieser zeigt:The invention is described below by way of example with reference to the drawing; in this shows:
Fig. 1 eine Darstellung der Abfolge von Prozeßschritten ei- nes speziellen Verfahrens nach dem Stand der Technik, Fig. 2 eine Darstellung der Abfolge von Prozeßschritten, die bei einem ersten Ausführungsbeispiel des erfindungsgemäßen Verfahrens auftreten,1 shows the sequence of process steps of a special method according to the prior art, 2 shows the sequence of process steps that occur in a first embodiment of the method according to the invention,
Fig. 3 eine Darstellung der Abfolge von Prozeßschritten, die bei einem zweiten Ausführungsbeispiel des erfindungsgemäßen Verfahrens auftreten, und3 shows the sequence of process steps which occur in a second exemplary embodiment of the method according to the invention, and
Fig. 4 eine rasterelektronenmikroskopische Aufnahme eines erfindungsgemäß gebildeten Grabenprofils nach einer selektiven Oxid-Naßätzung.4 shows a scanning electron micrograph of a trench profile formed according to the invention after a selective wet oxide etching.
Fig. 1 zeigt Prozeßschritte eines bekannten Verfahrens zur Erzeugung einer Grabenstruktur. Zunächst wird auf einem Siliziumsubstrat 1 eine dünne thermische Oxidschicht (Si02- Schicht) 2 und eine darüberliegende, dickere Nitridschicht (Si3N) 3 aufgewachsen (Schritt 1) . Nach einer Strukturierung der Oxid- und Nitridschichten 2, 3 werden durch einen Ätzprozeß Gräben 4, 5 definierter Tiefe in das Siliziumsubstrat 1 eingebracht (Schritt 2) . Danach wird auf das gesamte Substrat 1 eine in Fig. 1 nicht dargestellte Zwi- schenoxidschicht aufgewachsen, die als Unterlage für eine anschließend mittels Gasphasenabscheidung aufgebrachte undo- tierte TEOS-Oxidschicht 6 (TEOS: Tetra-Ethyl-Ortho-Silicate) dient (Schritt 3) . Schritt 4 umfaßt die Abscheidung von undotiertem Polysilizium auf der TEOS-Oxidschicht 6 und einen nachfolgenden chemisch-mechanischen Poliervorgang (Poly-CMP) zur Erzielung einer planaren Schichtoberfläche. Von der Po- lysiliziumschicht bleiben die in Fig. 1 dargestellten Polysi- liziuminseln 7, 8 zurück. Diese Inseln 7, 8 werden in einem folgenden Plasmaätzschritt als Masken verwendet, um die nichtmaskierten TEOS-Schichtbereiche 9, 10, 11 der TEOS-Oxidschicht 6 selektiv bis auf eine Restoxidschicht 12 über der Nitridschicht 3 abzuätzen. Dann werden durch einen weiteren selektiven Plasmaätzschritt die Polysiliziuminseln 7, 8 aus den übriggebliebenen Strukturen 13, 14 der TEOS-Oxidschicht 6 entfernt (Schritt 5) . Im weiteren folgt eine Planarisierung der übrig gebliebenen Oxidstrukturen 13, 14 durch einen che- misch-mechanischen Poliervorgang (Oxid-CMP) , bei der die Nitridschicht 3 als Stoppschicht verwendet wird. Bei diesem Schritt muß ein Teil der Nitridschicht 3 abgetragen werden, um sicherzustellen, daß jegliches Oxid vollständig von der Nitridschicht 3 entfernt wurde, wobei die Nitridschicht 3 aufgrund ihrer relativ schwachen Stoppwirkung im Oxid-CMP-1 shows process steps of a known method for producing a trench structure. First, a thin thermal oxide layer (Si0 2 layer) 2 and an overlying, thicker nitride layer (Si 3 N) 3 are grown on a silicon substrate 1 (step 1). After structuring the oxide and nitride layers 2, 3, trenches 4, 5 of defined depth are introduced into the silicon substrate 1 by an etching process (step 2). An intermediate oxide layer (not shown in FIG. 1) is then grown on the entire substrate 1, which serves as a base for an undoped TEOS oxide layer 6 (TEOS: tetraethyl-ortho-silicate) subsequently applied by means of gas phase deposition (step 3 ). Step 4 comprises the deposition of undoped polysilicon on the TEOS oxide layer 6 and a subsequent chemical mechanical polishing process (poly-CMP) to achieve a planar layer surface. The polysilicon islands 7, 8 shown in FIG. 1 remain from the polysilicon layer. These islands 7, 8 are used as masks in a subsequent plasma etching step in order to selectively etch the unmasked TEOS layer regions 9, 10, 11 of the TEOS oxide layer 6 apart from a residual oxide layer 12 over the nitride layer 3. Then by another selective plasma etching step, the polysilicon islands 7, 8 are removed from the remaining structures 13, 14 of the TEOS oxide layer 6 (step 5). Furthermore, the remaining oxide structures 13, 14 are planarized by a chemical mechanical polishing process (oxide CMP), in which the nitride layer 3 is used as a stop layer. In this step, part of the nitride layer 3 must be removed to ensure that any oxide has been completely removed from the nitride layer 3, the nitride layer 3 due to its relatively weak stop effect in the oxide CMP
Prozeß (Selektivität ~ 1:4) eine verhältnismäßig große Dicke (etwa 150 nm) aufweisen muß (Schritt 6) . In einem letzten Schritt wird dann die Restnitridschicht 3X selektiv durch einen weiteren Ätzschritt vollständig entfernt, so daß die dünne Oxidschicht 2 an der Oberfläche des Substrats 1 freiliegt. (Schritt 7) .Process (selectivity ~ 1: 4) must have a relatively large thickness (about 150 nm) (step 6). In a last step, the residual nitride layer 3 X is then selectively completely removed by a further etching step, so that the thin oxide layer 2 is exposed on the surface of the substrate 1. (Step 7).
Fig. 2 zeigt ein erstes Ausführungsbeispiel des erfindungsgemäßen Verfahrens, wobei gleiche Elemente wie in Fig. 1 mit identischen Bezugsziffern versehen sind.FIG. 2 shows a first exemplary embodiment of the method according to the invention, the same elements as in FIG. 1 being provided with identical reference numbers.
Zunächst wird das Siliziumsubstrat 1 mit einer dünnen thermischen Siliziumdioxidschicht 2 und einer darüberliegenden, dickeren Nitridschicht 3 versehen (Schritt l ). Danach werden in nicht dargestellter Weise die Oxidschicht 2, die Nitridschicht 3 und gegebenenfalls auch eine weitere, darüberlie- gend aufgebrachte, als Maskenschicht dienende Resistschicht strukturiert und eine Plasmaätzung mit einer definierten Tiefe in das Siliziumsubstrat 1 durchgeführt (Schritt 2X). Anschließend erfolgt in Schritt 3 das Aufbringen einer TEOS- Siliziumdioxidschicht 6, wobei entsprechend der Beschreibung zu Schritt 3 in Fig. 1 zuvor gegebenenfalls eine dünne Zwi- schenoxidschicht aufgebracht wurde. Die abgeschiedene TEOS- Oxidschicht 6 weist eine im wesentlichen konforme Dicke auf, was bedeutet, daß auch in engen Grabenbereichen eine Schicht- dicke etwa entsprechend der Schichtdicke über nichtgeätztenFirst, the silicon substrate 1 is provided with a thin thermal silicon dioxide layer 2 and an overlying, thicker nitride layer 3 (step 1). Thereafter, the oxide layer 2, the nitride layer 3 and optionally also a further resist layer applied above and serving as a mask layer are patterned in a manner not shown, and a plasma etching is carried out with a defined depth into the silicon substrate 1 (step 2 X ). A TEOS silicon dioxide layer 6 is then applied in step 3, a thin intermediate oxide layer possibly being applied beforehand in accordance with the description of step 3 in FIG. 1. The deposited TEOS oxide layer 6 has an essentially conformal thickness, which means that even in narrow trench areas a layer thickness approximately according to the layer thickness over non-etched
Bereichen des Substrats 1 erreicht wird. Dabei wird die durch die Grabenätzung erzeugte Topographie nach oben transferiert .Areas of the substrate 1 is reached. The topography generated by the trench etching is transferred upwards.
Nachfolgend wird eine Schicht aus undotiertem Polysilizium auf der TEOS-Oxidschicht 6 abgeschieden und durch chemisch- irtechanisches Polieren des Polysiliziums (Poly-CMP) bis auf die darunterliegende TEOS-Oxidschicht 6 abgetragen. Dabei wird die sehr gute Selektivität des Poly-CMP-Prozesses zwischen Polysilizium und Siliziumdioxid ausgenutzt, die etwa 100:1 beträgt. Der Polierschritt stoppt deswegen exakt auf dem Oxid und hinterläßt eine planare Oberfläche. Sämtliches überstehende Polysilizium wird abgetragen, so daß lediglich die Polysiliziuminseln 7, 8 zurückbleiben (Schritt 4λ).Subsequently, a layer of undoped polysilicon is deposited on the TEOS oxide layer 6 and removed by chemical-mechanical polishing of the polysilicon (poly-CMP) down to the underlying TEOS oxide layer 6. The very good selectivity of the poly-CMP process between polysilicon and silicon dioxide, which is approximately 100: 1, is used. The polishing step therefore stops exactly on the oxide and leaves a planar surface. All protruding polysilicon is removed, so that only the polysilicon islands 7, 8 remain (step 4 λ ).
Die Tiefe der Gräben 4, 5 im Substrat beträgt in diesem Beispiel etwa 400 nm und die Dicke der Nitridschicht 3 liegt bei etwa 150 nm, so daß sich eine Grabentiefe (definiert als Ab- stand zwischen Grabenboden und Oberfläche der Nitridschicht 3) von etwa 550 nm ergibt.In this example, the depth of the trenches 4, 5 in the substrate is approximately 400 nm and the thickness of the nitride layer 3 is approximately 150 nm, so that a trench depth (defined as the distance between the trench bottom and the surface of the nitride layer 3) is approximately 550 nm results.
Die Dicke der abgelagerten TEOS-Oxidschicht 6, gemessen über den nichtgeätzten, aktiven Substratbereichen, kann größer als die Grabentiefe (beispielsweise etwa 120% der Grabentiefe) sein, wenn ein „Overfill" der Gräben erwünscht ist. Aufgrund der Konformität der abgeschiedenen TEOS-Oxidschicht 6 ist jedoch grundsätzlich eine TEOS-Oxidschichtdicke entsprechend der Grabentiefe ausreichend.The thickness of the deposited TEOS oxide layer 6, measured over the non-etched, active substrate areas, can be greater than the trench depth (for example approximately 120% of the trench depth) if an “overfill” of the trenches is desired. Due to the conformity of the deposited TEOS oxide layer 6, however, a TEOS oxide layer thickness corresponding to the trench depth is generally sufficient.
Nachfolgend wird beim vorliegenden Ausführungsbeispiel ein nichtselektiver NF3/N2/CHF3-Plasmaätzschritt mit nahezu gleichen Ätzraten für Oxid und Polysilizium durchgeführt . Bei dem hier betrachteten Beispiel wird der Ätzvorgang bei einer Hochfrequenzleistung von 800 Watt ohne zusätzliches Magnet- feld und bei einer Temperatur von 20°C durchgeführt. Der Re- zipientendruck liegt bei etwa 6 Pa und es wird ein Ätzgas mit einer Zusammensetzung (Angaben in Volumen-%) von 89,5 % N2; In the present exemplary embodiment, a non-selective NF 3 / N 2 / CHF 3 plasma etching step is then carried out with almost the same etching rates for oxide and polysilicon. In the example considered here, the etching process is carried out at a high-frequency power of 800 watts without additional magnetic field and at a temperature of 20 ° C. The recipient pressure is about 6 Pa and an etching gas with a composition (data in volume%) of 89.5% N 2;
2,6% CHF3 und 7,9% NF3 verwendet, wobei eine Selektivität zwi- sehen Oxid und Polysilizium von 1,04:1 erreicht wird.2.6% CHF 3 and 7.9% NF 3 are used, a selectivity between oxide and polysilicon of 1.04: 1 being achieved.
Die Erfindung ist nicht auf einen Plasmaätzschritt beschränkt, sondern es kann ein beliebiges Atzverfahren angewendet werden, solange es eine ausreichend geringe Selektivi- tat aufweist, um bei der Schichtabtragung die Aufrechterhaltung einer planaren Oberfläche zu gewährleisten. Auch sind andere Bestandteile und Zusammensetzungen des zu verwendenden Ätzgases möglich.The invention is not limited to a plasma etching step, but any etching process can be used as long as it has a selectivity that is sufficiently low to ensure that a planar surface is maintained during the removal of the layer. Other components and compositions of the etching gas to be used are also possible.
Der nichtselektive Ätzschritt kann exakt solange durchgeführt werden, bis sämtliches Oxidmaterial über der Nitridschicht 3 entfernt ist und eine gemeinsame planareThe non-selective etching step can be carried out exactly until all the oxide material above the nitride layer 3 has been removed and a common planar one
Oxid/Nitridoberfläche 15, 16; 3 über dem Substrat 1 - wie in Fig. 2 bei Schritt 5λ gezeigt - vorliegt. Andererseits ist es in nicht dargestellter Weise auch möglich, den nichtselektiven Ätzschritt bereits vor Erreichen der Nitridschicht 3 abzubrechen, sofern ein vollständiges Entfernen der Polysili- ziuminseln 7, 8 bereits oberhalb der Nitridschicht 3 erfolgt ist. In diesem Fall läßt sich eine Restoxidschicht mit planarer Oberfläche und definierter Dicke über den aktiven Bereichen des Siliziumsubstrats 1 einstellen.Oxide / nitride surface 15, 16; 3 over the substrate 1 - as shown in FIG. 2 at step 5 λ - is present. On the other hand, it is also possible, in a manner not shown, to terminate the non-selective etching step before reaching the nitride layer 3, provided that the polysilicon islands 7, 8 have already been completely removed above the nitride layer 3. In this case, a residual oxide layer with a planar surface and a defined thickness can be set over the active areas of the silicon substrate 1.
Eine weitere Variante besteht darin, im Anschluß an den nichtselektiven Plasmaätzschritt einen selektiven Ätzschritt zum Entfernen von Oxid anzuwenden. Dieser selektive Ätzschritt ermöglicht einerseits die Entfernung der angesprochenen, gegebenenfalls vorhandenen Restoxidschicht über dem Siliziumsubstrat 1 und andererseits eine weitergehende, selektive Ätzung des Grabenoxids 15, 16 zur Einstellung eines de- finierten Abstands zwischen der Oberfläche 17 des Substrats 1 „„„„,Another variant is to use a selective etching step to remove oxide after the non-selective plasma etching step. This selective etching step makes it possible, on the one hand, to remove the addressed, if present, residual oxide layer above the silicon substrate 1 and, on the other hand, to further selectively etch the trench oxide 15, 16 to set a defined distance between the surface 17 of the substrate 1 """",
WO 99/1612WO 99/1612
8 in nichtgeätzten Bereichen und den Oberflächen 18, 19 des8 in non-etched areas and the surfaces 18, 19 of the
Grabenoxids 15, 16. Aufgrund der guten Selektivität, der geringen Schädigung der geätzten Oberfläche und der hohen Gleichmäßigkeit ist hierfür insbesondere ein Naßätzschritt geeignet.Trench oxide 15, 16. Because of the good selectivity, the low damage to the etched surface and the high uniformity, a wet etching step is particularly suitable for this.
Nach einer anschließenden Entfernung der Nitridschicht 3, die in Abhängigkeit von zuvor beschriebenen Varianten auch bereits vor dem selektiven Ätzschritt erfolgen kann, ergibt sich das in Fig. 2 bei Schritt 6λ gezeigte Grabenprofil des Substrats 1 mit insgesamt planarer Substratoberfläche.After subsequent removal of the nitride layer 3 which may also be a function of previously described variants already prior to the selective etching step is 2 6 grave profile shown λ results in Fig. 1, at step of the substrate with a total of planar substrate surface.
Fig. 3 zeigt Prozeßschritte lλ bis 5 Λ eines zweiten Ausführungsbeispiels des erfindungsgemäßen Verfahrens. Wie auch schon beim ersten Ausführungsbeispiel gemäß Fig. 2 wurdenFig. 3 shows process steps l λ to 5 Λ of a second embodiment of the method according to the invention. As was also the case with the first exemplary embodiment according to FIG. 2
Reinigungs- und Vorbereitungsschritte sowie ggfs. weitere zusätzliche Maßnahmen nicht in die Darstellung einbezogen. Das zweite Ausführungsbeispiel unterscheidet sich im wesentlichen lediglich dadurch von dem ersten Ausführungsbeispiel, daß auf die Nitridschicht 3 verzichtet wird. Dies ist möglich, da bei dem erfindungsgemäß vorgesehenen nichtselektiven Plasmaätzschritt (Schritt 5Λ bzw. 5, ) nicht die beim bekannten Verfahren nach Fig.l erforderliche Stoppfunktion der Nitridschicht in bezug auf den Oxid-Polierprozeß (Schritt 6) benö- tigt wird.Cleaning and preparation steps as well as any other additional measures are not included in the presentation. The second exemplary embodiment essentially differs from the first exemplary embodiment only in that the nitride layer 3 is dispensed with. This is possible because (step 5 Λ and 5, respectively) is not taken the required in the known process according to Fig.l stop function of the nitride layer relative to the oxide polishing process (step 6) benö- in the present invention provided non-selective plasma etching.
Das zweite Ausführungsbeispiel bietet die Vorteile, daß durch den Verzicht auf die Nitridschicht 3 die hierfür erforderlichen Schichtabscheidungs- und Schichtentfernungsschritte ent- fallen und das Aspektverhältnis (Verhältnis von Grabentiefe zu Grabenbreite) beim Grabenätzen verkleinert und die erforderliche TEOS-Oxidschichtdicke verringert werden kann. Die letztgenannnten Vorteile lassen sich auch bei dem ersten Ausführungsbeispiel mit Nitridschicht 3 erreichen, wenn die Dicke der Nitridschicht 3 in geeigneter Weise verkleinert wird.The second exemplary embodiment offers the advantages that, by dispensing with the nitride layer 3, the layer deposition and layer removal steps required for this are omitted and the aspect ratio (ratio of trench depth to trench width) is reduced during trench etching and the required TEOS oxide layer thickness can be reduced. The last-mentioned advantages can also be achieved in the first embodiment with nitride layer 3 if the Thickness of the nitride layer 3 is reduced in a suitable manner.
In Tab. 1 sind typische Werte für die beim Polierverfahren (Poly-CMP) und beim nichtselektiven Plasmaätzverfahren erreichten Selektivitäten (S) und Oberflächengleichmäßigkeiten (GM) angegeben.Table 1 shows typical values for the selectivities (S) and surface uniformity (GM) achieved with the polishing process (Poly-CMP) and with the non-selective plasma etching process.
Tab. 1Tab. 1
Die Werte machen deutlich, daß das nichtselektive Plasmaätzverfahren im Vergleich zum Poly-CMP-Verfahren eine bessere Gleichmäßigkeit der bearbeiteten Oberflächen liefert und somit die beim Poly-CMP-Verfahren erreichte Gleichmäßigkeit nicht verschlechtert. Die Werte für die Selektivitäten betragen beim nichtselektiven Plasmaätzverfahren etwa 1 und sind für einen gleichmäßigen Schichtabtrag unter Wahrung der Ebenheit völlig ausreichend.The values make it clear that the non-selective plasma etching process provides a better uniformity of the machined surfaces compared to the poly-CMP process and thus does not impair the uniformity achieved in the poly-CMP process. The values for the selectivities in the non-selective plasma etching process are approximately 1 and are completely sufficient for uniform layer removal while maintaining flatness.
Fig. 4 zeigt eine rasterelektronenmikroskopische Querschnittaufnahme eines Grabens in einem Substrat 1 mit dünner thermischer Oxidschicht 2 und CVD-Nitridschicht 3 nach der erfindungsgemäßen nichtselektiven Oxid-Polysilizium-Plasmaät- zung. Die Gesamtdicke der beiden Schichten beträgt etwa 37 nm, wobei die Dicke der Nitridschicht etwa bei bei 32 nm liegt. Das Substrat wurde nach dem erfindungsgemäßen nichtselektiven Ätzschritt der bereits beschriebenen selektiven Oxid-Naßätzung ausgesetzt, wodurch das Oberflächenniveau des Grabenoxids unter das Oberflächenniveau der das Substrat ab- deckenden Nitridschicht 3 abgesenkt wurde. Demgemäß beträgt die Grabentiefe 696 nm, während der Abstand zwischen Graben¬ boden und Oberfläche des Grabenoxids 644 nm beträgt. FIG. 4 shows a scanning electron microscope cross-sectional view of a trench in a substrate 1 with a thin thermal oxide layer 2 and CVD nitride layer 3 after the non-selective oxide-polysilicon plasma etching according to the invention. The total thickness of the two layers is approximately 37 nm, the thickness of the nitride layer being approximately 32 nm. After the non-selective etching step according to the invention, the substrate was exposed to the selective wet oxide etching already described, as a result of which the surface level of the trench oxide is below the surface level of the substrate. covering nitride layer 3 was lowered. Accordingly, the G is 696 nm deep raven, while the distance between trench ¬ ground and surface temperature is of the moat oxide 644 nm.

Claims

Patentansprüche claims
1. Verfahren zur Ausbildung einer Grabenstruktur in einem Siliziumsubstrat, die einen ersten Bereich des Substrates elektrisch von einem zweiten Bereich des Substrates isoliert, das die folgenden Verfahrensschritte aufweist: a) Aufwachsen einer thermischen Oxidschicht (2) auf die Substratoberfläche, b) Aufbringen und Strukturieren einer Maskenschicht über der thermischen Oxidschicht (2) , c) Ätzen eines Grabens (4, 5) unter Verwendung der strukturierten Maskenschicht bis zu einer vorgegebene Tiefe in das Siliziumsubstrat (1), d) Abscheidung einer im wesentlichen konformen Deckoxidschicht (6) mit einer im wesentlichen gleichmäßigen, zum vollständigen Auffüllen des Grabens (4, 5) ausreichenden Dicke, e) Abscheidung einer Polysiliziumschicht auf der Deckoxid- schicht (6) , wobei die Dicke der Polysiliziumschicht mindestens der Grabentiefe entspricht, f) chemisch-mechanisches Polieren der Polysiliziumschicht bis auf die Höhe der Oberfläche der Deckoxidschicht (6) mit einer hohen Selektivität zwischen dem Polysiliziummaterial (7, 8) der Polysiliziumschicht und dem Oxidmaterial der Deckoxidschicht (6) , und g) im wesentlichen nichtselektives, gemeinsames Atzen des Polysiliziummaterials (7, 8) der Polysiliziumschicht und des Oxidmaterials der Deckoxidschicht (6) unter Beibehaltung einer gemäß Schritt f) erzeugten planaren Oberfläche, wobei dieser Ätzvorgang zumindest solange durchgeführt wird, bis sämtliches Polysiliziummaterial (7, 8) der Polysiliziumschicht im Bereich des Grabens (4, 5) entfernt ist.1. A method for forming a trench structure in a silicon substrate which electrically insulates a first region of the substrate from a second region of the substrate, which has the following method steps: a) growing a thermal oxide layer (2) on the substrate surface, b) applying and structuring a mask layer over the thermal oxide layer (2), c) etching a trench (4, 5) using the structured mask layer to a predetermined depth in the silicon substrate (1), d) depositing a substantially conformal cover oxide layer (6) with a essentially uniform, sufficient to completely fill the trench (4, 5), e) depositing a polysilicon layer on the cover oxide layer (6), the thickness of the polysilicon layer corresponding at least to the trench depth, f) chemical-mechanical polishing of the polysilicon layer to to the level of the surface of the cover oxide layer (6) with a high S selectivity between the polysilicon material (7, 8) of the polysilicon layer and the oxide material of the cover oxide layer (6), and g) essentially non-selective, joint etching of the polysilicon material (7, 8) of the polysilicon layer and the oxide material of the cover oxide layer (6) while maintaining a Step f) generated planar surface, this etching process being carried out at least until all polysilicon material (7, 8) of the polysilicon layer in the region of the trench (4, 5) has been removed.
2. Verfahren nach Anspruch 1, dadurch g e k e n n z e i c h n e t, daß es sich bei dem im wesentlichen nichtselektiven Ätzschritt um einen Plasmaätzschritt, insbesondere Reaktives Ionenätzen2. The method according to claim 1, characterized in that the essentially non-selective etching step is a plasma etching step, in particular reactive ion etching
(RIE), handelt.(RIE).
3. Verfahren nach Anspruch 1 oder 2, dadurch g e k e n n z e i c h n e t, daß bei dem im wesentlichen nichtselektiven Ätzschritt als Ätzgase NF3/N2/CHF3-Gase verwendet werden.3. The method according to claim 1 or 2, characterized in that NF 3 / N 2 / CHF 3 gases are used in the substantially non-selective etching step as etching gases.
4. Verfahren nach einem der vorhergehenden Ansprüchen dadurch g e k e n n z e i c h n e t, daß die Dicke der in Schritt d) abgeschiedenen Deckoxidschicht4. The method according to any one of the preceding claims characterized in that the thickness of the cover oxide layer deposited in step d)
(6) größer als die Grabentiefe ist und der Ätzvorgang des Schritts g) nach Entfernung sämtlichen Polysiliziummaterials(6) is greater than the trench depth and the etching step g) after removal of all polysilicon material
(7, 8) der Polysiliziumschicht solange fortgesetzt wird, bis der restliche Teil der Deckoxidschicht (6) eine vorgegebene Dicke über der nichtgeätzten Substratoberfläche aufweist.(7, 8) of the polysilicon layer is continued until the remaining part of the cover oxide layer (6) has a predetermined thickness above the non-etched substrate surface.
5. Verfahren nach einem der vorhergehenden Ansprüchen, dadurch g e k e n n z e i c h n e t, daß nach Schritt a) eine Siliziumnitridschicht (3) auf die thermische Oxidschicht (2) aufgebracht wird.5. The method according to any one of the preceding claims, characterized in that a silicon nitride layer (3) is applied to the thermal oxide layer (2) after step a).
6. Verfahren nach einem der vorhergehenden Ansprüchen, dadurch g e k e n n z e i c h n e t, daß der im wesentlichen nichtselektive Ätzschritt g) eine Selektivität zwischen Oxid- und Polysiliziummaterial im Bereich von 0,95 bis 1,05 aufweist.6. The method according to any one of the preceding claims, characterized in that the essentially non-selective etching step g) has a selectivity between oxide and polysilicon material in the range from 0.95 to 1.05.
7. Verfahren nach einem der vorhergehenden Ansprüchen, dadurch g e k e n n z e i c h n e t, daß nach Schritt g) ein selektiver Naßätzschritt zur Entfernung von Oxidmaterial durchgeführt wird. 7. The method according to any one of the preceding claims, characterized in that after step g) a selective wet etching step for removing oxide material is carried out.
8. Verfahren nach Anspruch 7, dadurch g e k e n n z e i c h n e t, daß der selektive Naßätzschritt so gesteuert wird, daß zwischen der Oberfläche (18, 19) des Oxidmaterials im Graben (4, 5) und der Oberfläche (17) des Siliziumsubstrats (1) ein vorgegebener Abstand einstellbar ist.8. The method according to claim 7, characterized in that the selective wet etching step is controlled so that between the surface (18, 19) of the oxide material in the trench (4, 5) and the surface (17) of the silicon substrate (1) a predetermined distance is adjustable.
9. Verfahren nach einem der vorhergehenden Ansprüchen, dadurch g e k e n n z e i c h n e t, daß zwischen den Schritten c) und d) eine dünne Oxidunterlage konform auf das Substrat (1) aufgewachsen wird.9. The method according to any one of the preceding claims, characterized in that between the steps c) and d) a thin oxide base is grown conformally on the substrate (1).
10. Verfahren nach einem der vorhergehenden Ansprüchen, dadurch g e k e n n z e i c h n e t, daß die Deckoxidschicht (6) mittels einer TEOS-Gasphasenabschei- düng abgeschieden wird. 10. The method according to any one of the preceding claims, characterized in that the cover oxide layer (6) is deposited by means of a TEOS gas phase deposition.
EP98958161A 1997-09-24 1998-09-22 Method for making a groove structure in a silicon substrate Expired - Lifetime EP1019958B1 (en)

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DE19742174 1997-09-24
DE19742174 1997-09-24
PCT/DE1998/002832 WO1999016125A1 (en) 1997-09-24 1998-09-22 Method for making a groove structure with a silicium substrate

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EP1019958B1 (en) 2003-04-23
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KR100528569B1 (en) 2005-11-15
KR20010024284A (en) 2001-03-26
US6337255B1 (en) 2002-01-08
WO1999016125A1 (en) 1999-04-01
JP3462174B2 (en) 2003-11-05

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