EP1008253B1 - Method for compensating bit duration changes in fibreoptic signal transmission systems and retimer for carrying out said method - Google Patents

Abstract

The invention relates to an amplifier for eliminating time durations deviating from the set course from the logic states of digital signals transmitted by fibreoptics by means of retimers connected to the transmission path. To this end the duration of, for example, a bit of both logic states of the digital signal is measured continuously, stored temporarily and compared with each other. A control signal is then generated from the difference between these durations, which signal influences the input signal of the retimer via a control element connected to the signal circuit in such a way that the time deviation is compensated by time-shifting at least one bit edge. Compared to known methods the method provided for by the invention significantly reduces the time delay of the digital signal passing through the retimer so that it is also suitable for high-speed transmission systems. It also reduces resource requirements because there is no need to set the data rate and telegram. The invention also relates to alternative versions of the method and the retimer for carrying out said method.

Description

The invention is based on a method and a retimer for carrying out the method according to the preamble of claims 1 and 9, respectively.
In fiber-optic transmission systems for digital signals, in addition to attenuation-related level reduction as a result of different switching times, the electro / optical and opto / electrical converters (E / O and O / E converters) also change when changing from light to dark or vice versa that can lead to the elimination of bits and thus to falsification of the message content.
In known transmission lines of this type such. B. Optical fiber bus systems are therefore used in addition to amplifiers to compensate for level damping. Both measures are often carried out simultaneously in so-called repeaters.

Known retimers have a quartz-controlled receiver for analyzing the digital input signal (usually by oversampling) and a likewise quartz-controlled transmitter which generates and transmits a new signal in which the bit duration corresponds to that of the original signal.
Due to the practically unavoidable tolerances of the quartz, which determines the data rate of the original signal and the quartz or quartz in the retimer, there is a frequency difference between the time bases involved. To compensate for this difference, a memory (RAM) is provided between the two devices, which is traversed by the digital signal and has a storage time of at least one bit duration. In transmission systems with several such retimers - in a practical case, this can be the case. B. be twenty - add up their storage times and delay the digital signals so much that, if intolerable signal falsifications are to be avoided, only relatively low baud rates can be transmitted. These retimers are therefore not suitable for fast signal transmission systems of the kind that are increasingly being sought worldwide (time-out problem).

In addition, these devices must have a certain data rate and telegram type (e.g. PROFIBUS telegrams with a data rate of 12 Mbd) specially set are and are therefore complex and expensive.

A retimer according to the preamble of claim 1 is from DE 38 16 973 A1 known. In these devices to correct deviations in pulse widths from The setpoint is determined by means of a duty cycle detector circuit Determines input signal and generates the control signal. I'm trained as an AND circuit Actuator control and input signal are added and the unwanted Pulse width deviation compensated. The actuator has a longitudinal capacity and the duty cycle detector circuit has two low passes, so that this known retimers only for DC-free digital signals, but not for Restoration of digital signals with a DC component such as the common one PROFIBUS signals used is suitable and thus the described signal correction only possible in a limited area of application.

The invention is therefore based on the object of a method and a retimer Implementation of this procedure to create the simplest possible and the bit duration of the two logical states of the output signal in an economical manner are the same size without significant loss of time in the retimer and no adjustment of the Retimers to a certain data rate and / or telegram type is required, and which is particularly suitable for the temporal restoration of any coded digital signals are.

This object is achieved by the characterizing features of claims 1 and 9.
In the retimer according to the invention, the transmitted digital signal is examined for specified high and low bit sequences - because of the least effort, the cheapest for individual high and low states - whose respective duration, for example in the form of voltage values proportional thereto, is determined and in one subsequent control circuit compared. This comparison is only possible if the bits or bit sequences transmitted in succession in the digital signal are available at the same time; they are therefore kept in temporary storage. The control circuit generates a control signal controlling the edge trimmer on the basis of the two input voltages.

The bit duration detection circuits can alternatively be either the output or the Input signal of the actuator are supplied. In the first case there is a compensation device of the retimer from a closed control loop ("feedback regulation") in the second alternative from a so-called feed-forward regulation without Feedback.

In the case of an input signal which is unadulterated with regard to the bit durations, that is to say corresponding to the original signal, the duration of the two individual bits or bit sequences to be compared is the same. The size of the control voltage has a value at which the actuator does not make any signal corrections.
With time-distorted digital input signal with z. B. prolonged duration of the high bits or bit sequences and correspondingly shortened duration of the low bits or bit sequences, on the other hand, the control signal has a voltage value at which the actuator is currently compensating the time storage, so that the duration of the bits or bit sequences of the two logical states is the same as for the original signal.

In contrast to the prior art, in the retimer operating according to the method according to the invention, signal bits are not temporarily stored in the signal branch with the associated considerable time delay. The actuator also requires a certain throughput time, which is, however, much less than the delay mentioned.
As a result, the digital signal experiences a substantially smaller loss of time when passing through the retimer according to the invention, with practically no additional effort, so that even an extensive fiber-optic transmission system with a large number of such retimers ensures rapid signal transmission.
In addition, since only the transitions of the logic states are corrected, no knowledge and therefore no adjustment of the distances between these transitions, that is to say the data rate, is required. The setting of a specific signal telegram necessary in the known retimer is also irrelevant in the correction method according to the invention, as a result of which the overall effort is advantageously further reduced.
Finally, in contrast to the retimer known from DE 38 16 973 A1, the method according to the invention is also suitable for the compensation of bit-length deviations of arbitrarily coded digital signals and is therefore accessible to a much larger area of application.

Advantageous alternatives and further developments of the method according to patent claim 1 as well as refinements or designs of the retimer according to patent claim 9 are specified in the subclaims.
Thus, a method according to claim 2, in which the method steps are implemented by analog circuits, is particularly suitable in economic terms for small and medium quantities.

In the case of large quantities, on the other hand, it is cheaper to choose digital circuits for the method steps, because these can be mass-produced extremely cost-effectively as integrated circuits. Since these IC components are also very small in comparison to circuits with discrete components, retimers with small dimensions and a correspondingly wide range of applications can also be constructed.
Of course, it is also possible to carry out only individual process steps in a time-discrete manner and to implement them by means of integrated circuit modules. In most cases, however, it will be expedient for economic reasons to carry out all relevant process steps in a single IC module.
Processors are often already present in signal transmission systems and can be used for retimer functions in order to further reduce costs.

An uncomplicated, safe and exactly functioning version of the invention The method according to claim 4 is that the starting times for the Rise and fall of the bit sequences in the output signal determined by the times on which the edges of the bit sequences of the input signal a certain Level, hereinafter called the decision value.

There are several claims 6 for the practical implementation of this method up to 8 alternative options are available. Particularly accurate and with These tolerances work fine if the adjustment is not made to the normally very steep bit edges, but on edges with lower ones Pitch. It is therefore particularly advantageous to have the rise and fall times of the Bit sequence edges of the input signal according to claim 5 by means of a delay element to enlarge.

With all three methods for determining the starting times for the increase or the drop in the bits or bit sequences, i.e. for the change from low to high and vice versa, can both the decision value and the slope be of the same or different sizes for the two flanks, so that a total of a large number of setting options is given with which an optimal adaptation to the Conditions of all practical individual cases can be achieved.

In an advantageous embodiment of the retimer specified in claim 9, the Edge trimmer according to claim 10, a comparator whose first input via a delay element with the output of the O / E converter and its second Input is connected to the output of the control circuit. The delay element at the entrance of the flank trimmer, which with a particularly simple training only consists in an RC element (claim 11), causes the already described Increasing the rise and fall duration of the bit or bit sequence edges. The comparator now takes place - in one of the ways specified in claims 6 to 8 an opposing shift in the start time of the two edges of the individual bits or the bit sequence of the input signal, by the duration of that of the original signal equalize. So if, for example, the high bits or bit sequences of the Input signal lengthened compared to the target duration and the low bits or - Bit sequences are shortened accordingly, so the control signal can change the level of the decision value lift, with the opposite course of the flanks of the temporal distance of the edge points corresponding to this level and thus the distance the start times for the edges of the bits or the bit sequences of the output signal be reduced so that their duration corresponds to the setpoint. By this correction is then the duration of the same bits or bit sequences of both logical States again the same.

A digital version according to claim 12 has not only that already mentioned Advantage of an inexpensive integration with large quantities. but also the one that the entire edge trimmer is made up exclusively of delay elements can be and no comparator is required.

The use of delay circuits as well as that at the input of the bit duration detection circuits required RC links with adjustable according to claim 13 Time constant advantageously allows adaptation to different ones Data rates of various digital signals (e.g. 1.5 or 12 Mbit / s at PROFIBUS signals) and thus significantly extends the area of application of the retimer.

Particularly simple and inexpensive designs of the actual value memory and the control circuit in the case of an analog method are given in claims 14 and 15. As already stated, however, these functions can be implemented even more cheaply by integrated circuits in large quantities.
Of course, this also applies to the bit duration detection circuits, the determination of the duration of the bits or bit sequences, for. B. done by digital counters, whose clock frequency is greater than the data rate of the bits or bit sequences.

If the encoding of the digital signal is known, the bit duration detection circuits are particularly simple and inexpensive to carry out. For example, with no DC voltage coded digital signals as in the so-called Manchester code both bit duration detection circuits through a single RC link with a correspondingly long length Time constant can be realized.

Fig. 1 -

ein Prinzipschaltbild eines analog arbeitenden, in einem faseroptischen Bussystem eingeschalteten Retimers.

Fig. 2a -

den Signalverlauf eines unverfälschten (Original-) Digitalsignals

Fig. 2b -

jeweils den Signalverlauf

• eines verfälschten Eingangssignals mit verlängerten High-Bit,
• des gleichen Signals mit symmetrisch zeitverzögerten Flanken,
• des korrigierten Ausgangssignals und

Fig. 2c -

die Signalverläufe wie in Fig. 2b. jedoch mit unsymmetrisch zeitverzögerten Flanken des verfälschten Eingangssignals.

The invention is explained in more detail below using an exemplary embodiment in the figures. Show it:

Fig. 1 -

a schematic diagram of an analog working retimer switched on in a fiber optic bus system.

Fig. 2a -

the waveform of an unadulterated (original) digital signal

Fig. 2b -

each the signal curve

• a corrupted input signal with extended high bit,
• the same signal with symmetrically delayed edges,
• the corrected output signal and

2c -

the waveforms as in Fig. 2b. however, with asymmetrically delayed edges of the corrupted input signal.

2a to 2c, the time course is horizontal Direction and the level curve in the vertical direction.

The retimer 1 consists of an O / E converter 2 supplying a digital electrical input signal E, an output-side E / O converter 4 connected to it via a signal branch 3, and one that is switched into the signal branch 3 between the two converters 2, 4 and corrects this Edge trimmer 5 generating digital output signal A, one bit duration detection circuit 6, 7 driven by output signal A for the two logic states, one capacitor 8, 9, which is connected between the outputs of bit duration detection circuits 6, 7 and ground, and serves as a buffer, and a differential amplifier 10, the latter both inputs are also connected to the outputs of the bit duration detection circuits 6, 7 and the output signal thereof controls the edge trimmer 5 as a control signal.
The latter consists of an RC delay element 11 on the input side and a comparator 12.

In FIG. 1, only one of the two is identical for the sake of a clearer representation constructed bit duration detection circuits 6 shown with circuit components. It has a first switch S 1 on the input side, at one connection thereof a voltage U is present and its second connection on the one hand via an RC element R1, C1 with ground and on the other hand via a buffer amplifier P1 with the first Connection of a second switch S2 is connected. Its second connection is grounded through another capacitor C2 and is at the same time as the first Connection of a third switch connected, the second connection on the one hand to first input of a comparator K and the other via a further buffer amplifier P2 leads to the first connection of a fourth switch S4 which is connected to the output signal of the comparator K is controlled. The switches S1 to S3 are mutually from the output signal or - via an inverter 13 - from the inverted output signal controlled. The second connection of the fourth switch S4 and the second The input of the comparator K form the output of the bit duration detection circuit 6.

Bit duration detection circuits 6, 7, buffers 8, 9, differential amplifier 10 and edge trimmer 5 form a closed control loop (feedback control) to correct falsified time periods of the bits or bit sequences of the digital input signal E.

In the original signal O, all high and low bits have the same duration t ₁ .
In the input signal E, in the present example, compared to the original signal O, all transitions from high to low - compared to the transitions from low to high - are delayed by the time period Δt and, accordingly, the duration t _{2 of} all individual high bits is delayed by Δt (t ₂ = t ₁ + Δt) is too long and the duration t _{3 of} all individual low bits is too short by the same amount of time (t ₃ = t ₁ - Δt).

The edge trimmer 5 now delays the transitions from using the control circuit Low to high, based on the transitions from high to low, also by the Time period Δt, so that the corrected output signal A again the original signal O equivalent. This is accomplished in the following ways:

The output signal A which corresponds to the falsified input signal E before the onset of control is branched off from the signal branch 3 and fed to the two bit duration detection circuits 6, 7. During the high state of the output signal A, the switch S1 is closed, the capacitor C1 is charged to the voltage U. During the following low state, C1 discharges via R1. Its voltage value is transferred to the capacitor C2 via the buffer amplifier P1 and the switch S2 which is closed during this period.
At the end of this low state at the beginning of the next high state, switch S2 opens and switch S1 closes. The capacitor C1 now resumes its starting voltage U, and the discharge voltage of the capacitor C1 which has been reached remains temporarily stored on the capacitor C2. This voltage reaches the buffer amplifier P2 and the comparator K via the now closed switch S3.
In the present exemplary embodiment, the bit duration detection circuit now looks for the shortest, that is to say 1-bit long, low state in the signal, which corresponds to the highest voltage occurring at capacitor C2. For this purpose, the comparator K compares the voltage currently stored in the capacitor C2 with the voltage stored in the actual value memory 8.
If the currently detected voltage on capacitor C2 is higher than the voltage stored in the actual value memory, then comparator K closes switch S4 and the voltage on capacitor C2 is transferred to actual value memory 8, which is designed as a capacitor.

On the other hand, the voltage currently detected at capacitor C2 is lower than that already stored in the actual value memory 8, the switch S4 remains open and that in the actual value memory 8 stored voltage unchanged.

From the actual values present at its inputs, those temporarily stored as voltage values The differential amplifier 10 now generates high and low bit durations a control signal fed to one input of the comparator 12 of the edge trimmer 5, whose DC voltage level as the decision value EW together with the start times for the transitions from low to high in the course of the bit edges and determine from high to low, as shown in FIGS. 2b and 2c.

The rise and fall times of the bit edges of the input signal E are essential shorter than the bit duration and therefore too short for an effective and safe correction of the type mentioned, d. H. enable sufficiently large changes in the time periods. The edge trimmer 5 therefore has a delay element at its input 11, which makes these flanks correspondingly flatter. That changed here Input signal shown in simplified trapezoidal designation is denoted by V.

The comparator 12 of the edge trimmer 5 outputs a high or low at its output at the time of passage of the rising or falling edge through the decision value EW, which results in the output signal A.
In the present example, the edges of the signal V are fixed and the decision value EW is set by the level of the control signal so that the time duration of the individual bits becomes the same and thus the output signal A supplied to the E / O converter 4 corresponds to the original signal O.
The regulation mentioned is particularly effective because, due to the opposite slope of the signal V, large changes in the duration of the bits can be achieved even with small changes in level.

In the signal V shown in FIG. 2b, the bit edges are symmetrical, ie the amount of the slopes is the same in each case. In this embodiment, the edges remain unchanged and the decision value EW is set by the control signal above the average bit level to such an extent that the temporal edge spacing at this level corresponds exactly to the target bit duration t ₁ (see claim 6).

In contrast, in the alternative embodiment according to FIG. 2c, the decision value is EW is set at half the bit level and the desired edge distance at this decision value EW is here by means of the control signal set increase in the slope of the falling bit edge achieved. The in this case, the two bit edges are therefore asymmetrical (see claim 7).

Claims (15)

1. Method of eliminating durations of logic states of fibre-optically transmitted digital signals which deviate from the desired progression by means of at least one re-timer which is connected in the transmission path and comprises an opto-electrical and an electro-optical transducer and an intermediately connected actuator which is controlled by a control signal, characterised in that the duration of a respectively identical number of consecutive bits having the same polarity (bit sequence) of the two logic states High and Low of the digital signal which is branched from the signal branch connecting the two transducers is measured in a continuous manner, is buffered and compared each with the other and that the difference in these durations (time-offset) is used for generating the control signal which influences the input signal, which is provided by the opto-electrical transducer, by way of the actuator in such a manner that the time-offset is compensated by the temporal shift of at least one bit sequence edge and the High and Low bit sequences of the output signal supplied to the electro-optical transducer are the stame length.
2. Method according to claim 1, characterised in that the method steps are performed in a time-continuous manner.
3. Method according to claim 1, characterised in that the method steps are performed in a time-discrete manner.
4. Method according to any one of claims 1 to 3, characterised in that the starting times for the rise and fall of the bit sequences in the output signal are determined by the points in time, at which the edges of the bit sequences of the input signal are at a specific level (decision value).
5. Method according to claim 4, characterised in that the rise and fall duration of the bit sequence edges of the input signal is increased prior to the edge shift.
6. Method according to claim 4 or 5, characterised in that the steepness of the bit sequence edges is kept constant and the decision value is adjusted by the control signal.
7. Method according to claim 4 or 5, characterised in that the decision value is kept constant and the steepness of at least one bit sequence edge is adjusted by the control signal.
8. Method according to claim 4 or 5, characterised in that both the decision value and also the steepness of the bit sequence edges are adjusted by the control signal.
9. Re-timer having an actuator, which is controlled by a control signal, for the purpose of implementing the method according to any one of claims 1 to 8 in fibreoptic signal transmission systems, characterised in that the actuator is an edge trimmer (5), whose input signal (E) or output signal (A) is supplied in each case to a bit duration detection circuit (6, 7) for the bit sequence of the two logic states, whose outputs are connected in each case to an actual value memory (8, 9) for the detected voltage, which is proportional to the duration of the bit sequence, and to an input of a control circuit (10), whose output-side control signal controls the edge trimmer (5) in such a manner that the duration of the compared bit sequences of the two logic states is the same length in the corrected output signal (A).
10. Re-timer according to claim 9, characterised in that the edge trimmer (5) comprises a comparator (12), whose first input is connected via a delay element (11) to the output of the opto-electrical transducer (2) and whose second input is connected to the output of the control circuit (10).
11. Re-timer according to claim 10, characterised in that the delay element is an RC-element (11).
12. Re-timer according to claim 9, characterised in that the edge trimmer consists of digital delay elements.
13. Re-timer according to any one of claims 10 to 12, characterised in that the time constant of the delay circuit (11) of the edge trimmer (5) and of an RC-element (R1, C1) can be adjusted at the input of the bit duration detection circuits (6, 7).
14. Re-timer according to any one of claims 9 to 12, characterised in that the actual value memory is provided in each case in the form of a capacitor (8, 9) which is connected between the output of the bit duration circuits (6, 7) and earth.
15. Re-timer according to any one of claims 9 to 13, characterised in that the control circuit consists of a difference amplifier (10).

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