Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L47/00—Traffic control in data switching networks
  • H04L47/10—Flow control; Congestion control
  • H04L47/28—Flow control; Congestion control in relation to timing considerations
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/64—Hybrid switching systems
  • H04L12/6418—Hybrid transport
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L47/00—Traffic control in data switching networks
  • H04L47/10—Flow control; Congestion control
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L47/00—Traffic control in data switching networks
  • H04L47/10—Flow control; Congestion control
  • H04L47/22—Traffic shaping
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/90—Buffering arrangements
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
  • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
  • H04J2203/0073—Services, e.g. multimedia, GOS, QOS
  • H04J2203/0082—Interaction of SDH with non-ATM protocols
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
  • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
  • H04J2203/0073—Services, e.g. multimedia, GOS, QOS
  • H04J2203/0082—Interaction of SDH with non-ATM protocols
  • H04J2203/0083—Support of the IP protocol
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/06—Synchronising arrangements
  • H04J3/0635—Clock or time synchronisation in a network
  • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
  • H04J3/0644—External master-clock
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/06—Synchronising arrangements
  • H04J3/0635—Clock or time synchronisation in a network
  • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
  • H04L69/28—Timers or timing mechanisms used in protocols

Definitions

• This invention relates generally to a method and apparatus for transmitting of data on a communications network. More specifically, this invention relates to timely forwarding and delivery of data over the network and to their destination nodes.
• the timely forwarding is possible by time information that is globally available from a global positioning system (GPS). Consequently, the end-to-end performance parameters, such as, loss, delay and jitter, have either deterministic or probablistic guarantees.
• GPS global positioning system
• This invention further facilitates a method and apparatus for integrating the transfer of two traffic types over a data packet communications network. More specifically, this invention provides timely forwarding and delivery of data packets from sources with constant bit rate (CBR) and variable bit rate (VBR) over the network and to their destination nodes.
• CBR constant bit rate
• VBR variable bit rate
• This invention further relates a method and apparatus for transmitting of data on a communications network via communication links with variable delays. More specifically, this invention relates to timely forwarding and delivery of data over networks with links with variable delays to their destination nodes, while ensuring the end-to-end performance parameters, such as, loss, delay and jitter, have either deterministic or probablistic guarantees.
• This invention also provides a method and apparatus for monitoring, policing, and billing of the transmission of data packet on a communications network. More specifically, this invention provides the monitoring, policing, and billing in networks with timely forwarding and delivery of data packets to their destination nodes. Consequently, the end-to-end performance parameters, such as, loss, delay and jitter, are predictable, and therefore, it is possible to measure them. Consequently, such measurements are used in the monitoring, policing and billing.
• This invention also provides for a method and apparatus for transmitting of data on an heterogeneous communications network, which has two types of switching nodes: (i) asynchronous and (ii) synchronous with common time reference. More specifically, this invention provides timely forwarding and delivery of data over the network and to their destination nodes. Consequently, the end-to-end performance parameters, such as, loss, delay and jitter, have either deterministic or probablistic guarantees.
• This invention furthermore facilitates a routing decision by using both timing information and position information of packets within time frames.
• there is no need to decode the address in the packet header it is feasible to encrypt the entire data packet (including the header) as it is transferred through a public backbone network, which is an important security feature. Consequendy, over this novel communications network it is possible to transport wide variety of data packets, such as, IP (Internet protocol) and ATM (asynchronous transfer mode).
• IP Internet protocol
• ATM asynchronous transfer mode
• Packet switching networks like LP (Internet Protocol)- based Internet and Intranets [see, for example, ATannebaum, “Computer Networks” (3rd Ed) Prentice Hall, 1996] and ATM (Asynchronous Transfer Mode) [see, for example, Handel et al., “ATM Networks: Concepts, Protocols, and Applications", (2nd Ed.) Addison- Wesley, 1994] handle bursty data more efficiently than circuit switching, due to their statistical multiplexing of the packet streams.
• LP Internet Protocol
• ATM Asynchronous Transfer Mode
• Efforts to define advanced services for both IP and ATM have been conducted in two levels: (1) definition of service, and (2) specification of methods for providing different services to different packet streams.
• the former defines interfaces, data formats, and performance objectives.
• the latter specifies procedures for processing packets by hosts and switches/routers.
• the types of services that defined for ATM include constant bit rate (CBR), variable bit rate (VBR) and available bit rate (ABR).
• CBR constant bit rate
• VBR variable bit rate
• ABR available bit rate
• the defined services include guaranteed performance (bit rate, delay), controlled flow, and best effort [J. Wroclawski, "Specification of the Controlled-Load Network
• SLP Session Initiation Protocol
• IETF auspices “Handley et al., "SIP-Session Initiation Protocol", ⁇ draft-draft-ietf-mmusic-sip-04.ps>, November 1997].
• QoS Quality of Service
• Prior art in QoS can be divided into two parts: (1) traffic shaping with local timing without deadline scheduling, for example [M.G.H. Katevenis, "Fast Switching And Fair Control Of Congested Flow In Broadband Networks", IEEE Journal on Selected Areas in Communications, SAC-
• WFQ Weighted Fair Queuing
• MPLS Packet Control Protocol
• RTP real-time transport protocol
• Protocol for Real-Time Applications IETF Request for Comment RFC 1889, January 1996
• RTP is currently the accepted method for transporting real time streams over IP internetworks and packet audio/video telephony based on ITU-T H.323.
• Optical Hypergraph INFOCOM'88, 1988].
• the forwarding is performed over hyper-edges, which are passive optical stars.
• hyper-edges which are passive optical stars.
• the synchronous optical hypergraph idea was applied to networks with an arbitrary topology and with point-to- point links. The two papers [Li et al., "Pseudo-Isochronous Cell Switching In ATM Networks", IEEE INFOCOM'94, pages 428-437, 1994; Li et al., “Time-Driven Priority: Flow Control For Real-Time Heterogeneous Internetworking", IEEE INFOCOM'96, 1996] the synchronous optical hypergraph idea was applied to networks with an arbitrary topology and with point-to- point links. The two papers [Li et al., "Pseudo-Isochronous Cell Switching In ATM
• Yemini et al. discloses switched network architecture with common time reference.
• the time reference is used in order to determine the time in which multiplicity of nodes can transmit simultaneously over one predefined routing tree to one destination. At every time instance the multiplicity of nodes are transmitting to different single destination node.
• Routing the selection of an output port for an information segment (i.e. data packets) that arrives at an input port of a switch — is a fundamental function of communication networks.
• the unit of switching is a byte, and the switching is made based on the location of the byte in a time frame.
• Establishing a connection in a circuit switching network requires the network to reserve a slot for the connection in every frame.
• the position of the byte in the frame is different from link to link, so each switch maintains a translation table from incoming frame positions on each input port to respective output ports and frame positions therein.
• the sequence of frame positions on the links of the route constitute a circuit that is assigned for the exclusive use of a specific connection, which results in significant inflexibiUty: the connection is limited in traffic intensity by the capacity of the circuit and when the connection does not use the circuit no other is aUowed to use it. This feature is useful for CBR traffic, like PCM telephony, but it results in low utiUzation of the network when the traffic is bursty [C. Huitema, Routing in the Internet,
• a method is disclosed providing virtual pipes that carry real-time traffic over packet switching networks while guaranteeing end- to-end performance.
• the method combines the advantages of both circuit and packet switching. It provides for aUocation for the exclusive use of predefined connections and for those connections it guarantees loss free transport with low delay and jitter.
• predefined connections do not use their aUocated resources, other non-reserved data packets can use them without affecting the performance of the predefined connections.
• the non-reserved data packet traffic is caUed "best effort" traffic.
• This invention further describes a method for transmitting and forwarding packets over a packet switching network where the delay between two switches increases, decreases, or changes arbitrarily over time. Packets are being forwarded over each Unk inside the network in predefined periodic time intervals.
• the switches of the network maintain a common time reference, which is obtained either from an external source (such as GPS - Global Positioning System) or is generated and distributed internaUy.
• the time intervals are arranged with simple periodicity and complex periodicity (like seconds and minutes of a clock).
• the invention provides methods for maintaining timely forwarding within predefined time interval over two types of Unk delay variations: (i) increasing delay and
• (ti) decreasing delay When the delay increases at some point of time a packet may be late for its predefined forwarding time interval. In such case the packet is delayed until the next time interval of its virtual pipe.
• Packets that are forwarded inside the network over the same route and in the same time intervals constitute a virtual pipe and share a pipe-ID.
• the pipe-ID can be either expUcit, such as a tag or a label that is generated inside the network, or impUcit, such as a group of IP addresses.
• a virtual pipe provides deterministic quality of service guarantees. The time interval in which a switch forwards a specific packet is determined by the packet's pipe-ID, the time it reaches the switch, and the current value of the common time reference.
• the bandwidth aUocated to a connection and the delay and jitter inside the network are independent.
• MPLS can be used by the present invention to identify virtual pipes.
• the packet time-stamp that is carried in the RTP header can be used in accordance with the present invention to faciUtate time-based transport.
• the present invention provides real-time services by synchronous methods that utitize a time reference that is common to the switches and end stations comprising a wide area network.
• the common time reference can be reaUzed by using UTC (Coordinated Universal Time), which is globally available via, for example, GPS (Global Positioning System - see, for example: http ⁇ /www.utexas.edu/depts/grg/gcraft/notes/gps/gps.html).
• GPS Global Positioning System
• UTC is the scientific name for what is commonly caUed GMT (Greenwich Mean Time), the time at the 0 (root) line of longitude at Greenwich, England. In 1967, an international agreement estabUshed the length of a second as the duration of 9,192,631,770 oscUlations of the cesium atom. The adoption of the atomic second led to the coordination of clocks around the world and the establishment of UTC in 1972.
• the Time and Frequency Division of the National Institute of Standards and Technologies (NIST) (see http ⁇ /www.boulder.nisLgov/timefreq) is responsible for coordinating with the International Bureau of Weights and Measures (BIPM) in Paris in maintaining UTC.
• UTC timing is readily available to individual PCs through GPS cards.
• TrueTime, Inc.'s (Santa Rosa, CA) PCI-SG provides precise time, with zero latency, to computers that have PCI extension slots.
• Another way by which UTC can be provided over a network is by using the Network Time Protocol (NTP) [D. MiUs, "Network Time Protocol” (version 3) IETF RFC 1305].
• NTP Network Time Protocol
• NTP is not adequate for inter-switch coordination, on which this invention is based.
• the present invention reUes on time to control the flow of packets inside the network in a similar fashion as in circuit switching, there are major differences between the two approaches.
• circuit switching for each data unit (e.g., a byte) at the time it has been transmitted from its source, it is possible to predict deterministicaUy the future times it wiU be transmitted from any switch along its route [Ballart et al., "SONET: Now It's The Standard Optical Network", IEEE Communications Magazine, Vol. 29 No. 3, March 1989, pages 8-15].
• the time resolution of this advanced knowledge is much shorter than the data unit transmission time.
• the time frame which constitutes the accuracy of this advance timing knowledge, is much larger than one data unit transmission time.
• the transmission time of an ATM ceU (53 bytes) over a gigabit per second link is 424 nanoseconds, which is 294 times smaller than a typical time frame of 125 microseconds used in one embodiment of the present invention.
• the use of reserved resources is aUowed by aU packet traffic whenever the reserved resources are not in use.
• the synchronization requirements are independent of the physical Unk transmission speed, whUe in circuit switching the synchronization becomes more and more difficult as the link speed increases.
• timing information is not used for routing, and therefore, as in the Internet, for example, the routing is done using IP addresses or a tag/label.
• the Internet "best effort" packet forwarding strategy can be integrated into the system.
• a method for monitoring and poUcing the packet traffic in a packet switching network where the switches maintain a common time reference.
• a designated points inside the network is enabled to ascertain the level of packet traffic in predefine time intervals, and control the flow of packets and bring it back to predetermined levels in cases where the traffic volume exceeds predetermined levels.
• the information coUected by the designated points facihtates bilUng for Internet services based on network usage, and identification of faulty conditions and maUcious forwarding of packets that cause excessive delay beyond predetermined value.
• a method for exchanging timing messages and data packets between synchronous switches with a common time reference, and between end-stations/gateways and other synchronous switches, over an asynchronous network, i.e., a network with asynchronous switches.
• the method entaUs transmission of messages conveying the common time reference to end-station/gateways that have no direct access to the common time reference, and data packets that are sent responsive to the timing information and predetermined scheduled time intervals.
• methods are provided for mamtaining timely forwarding within predefined time interval over three network configurations: (i) end- station to synchronous switch over asynchronous (LAN) switches, (ii) end-station to gateway over asynchronous (LAN) switches and then to synchronous switch, (iii) synchronous switch to synchronous switch over asynchronous switches.
• FIG. 1 is a schematic illustration of a virtual pipe and its timing relationship with a common time reference (CTR), wherein delay is determined by the number of time frames between the forward time out at Node A and the forward time out at Node D;
• FIG. 2 is a schematic Ulustration of multiple virtual pipes sharing certain ones of the switches;
• FIG. 3 is a schematic block diagram iUustration of a switch that uses a common time reference from the GPS (Global Positioning System) for the timely forwarding of packets disclosed in accordance with the present invention
• FIG. 4 iUustrates the relationship among the local common time reference (CTR) on the switches, and how the multiplicity of local times is projected on the real-time axis, wherein time is divided into time frames of a predefined duration;
• CTR local common time reference
• FIG. 5 is a schematic illustration of how the common time reference is organized into contiguous time-cycles of k time-frames each and contiguous super-cycle of / time- cycles each;
• FIG. 6 is a schematic iUustration of the relationship of the network common time reference and UTC (Coordinated Universal Time), such that, each time-cycle has 100 time-frames, of 125 microseconds each, and 80 time-cycles are grouped into one super- cycle of one second;
• FIG. 7 is a schematic Ulustration of a data packet pipeline as in FIG. 1 , and correlating to data packet movement through the switches 10 versus time for forwarding over a virtual pipe with common time reference (CTR);
• CTR virtual pipe with common time reference
• FIG. 8 iUustrates the mapping of the time frames into and out of a node on a virtual pipe, wherein the mapping repeats itself in every time cycle iUustrating time in versus forwarding time out;
• FIG. 9 is an iUustration of a serial transmitter and a serial receiver
• FIG. 10 is a table of the 4B/5B encoding scheme for data such as is used by the AM7968 - TAXI chip set in accordance with one embodiment of the present invention
• FIG. 11 is a table of the 4B/5B encoding scheme for control signals, such as, the time frame delimiter (TFD) such as is used by the AM7968, in accordance with one embodiment of the present invention
• TFD time frame delimiter
• FIG. 12 is a schematic block diagram of an input port with a routing controller
• FIG. 13 is a schematic diagram of the routing controller which determines to which output port an incoming data packet should be switched to and attaches the time of arrival (ToA) information to the data packet header;
• ToA time of arrival
• FIG. 14 is a flow diagram of the routing controller operation
• FIGS. 15A and 15B iUustrate two generic data packet headers with virtual pipe ID (PID), and priority bit (P), wherein FIG. 15 A iUustrates a packet without time-stamp field, and wherein FIG. 15B Ulustrates a packet with time-stamp field, and also shows how the common time-reference value, time of arrival (ToA), is attached by the routing controUer;
• FIG. 16 is a schematic block diagram of an output port with a scheduling controUer and a serial transmitter;
• FIG. 17 is a schematic block diagram of the double-buffer scheduUng controUer
• FIG. 18 is a flow diagram of the double- buffer scheduling controller 46 operation
• FIG. 19 is a functional block diagram of the general scheduUng controUer with its transmit buffer and select buffer controUer;
• FIG. 20 is a flow diagram describing the packet scheduUng controUer operation for computing the forwarding time of a packet based on the following input parameters: PID 35C, ToA 35T and the CTR 002;
• FIG. 21 is a flow diagram illustrating the operation of the Select Buffer ControUer 45D
• FIG. 22 iUustrates the real-time protocol (RTP) packet header with time-stamp field of 32 bits; and
• FIG. 23 is a flow diagram describing the packet scheduUng controUer operation for computing the dispatching-time of a packet based on the foUowing input parameters: PID, ToA, CTR and the RTP time-stamp.
• RTP real-time protocol
• FIG. 24 is a schematic description of a switch with a common time reference partition into time-frames with predefined positions such that the input port can unambiguously identify the positions;
• FIG. 25 is a description of the timing partition of the common time reference into cycle with k time frames in each, wlender each time frame is further partitioned into four predefined parts: a, b, c and d;
• FIG. 26 is a schematic diagram of the time-based routing controller. This unit determines to which output port a data packet should be switched and attaches the time in and position information to the data packet header;
• FIG. 27 is an example of a routing and scheduling table on one of the incoming input ports using the incoming time or time-frame of arrival (ToA) and the position counter value for determining: (i) the output port, (u) the out-going time-frame, and (Ui) the position of the out-going data packet within the out-going time-frame;
• FIG. 28 is a schematic iUustration of a data packet which is sent across the fabric to the output port;
• FIG. 29 is an example of a routing and scheduling table on one of the incoming input ports using the time stamp and position information for determining: (i) the output port, (u) the out-going time-frame, and (in) the position of the out-going data packet within the out-going time-frame;
• FIG. 30 is a flow diagram of the routing controller operation
• FIG. 31 is a flow diagram of the data packet scheduling controUer 45 A operation
• FIG. 32 is a flow diagram of a different embodiment of the Select Buffer ControUer 45D;
• FIG. 33 is a schematic diagram of another alternate embodiment of the routing controller which determines to which output port an incoming data packet should be switched to and attaches the time of arrival (ToA) information to the data packet header;
• ToA time of arrival
• FIGS. 34A and 34B are schematic Ulustrations of two generic data packet headers with virtual pipe ID (PID) and priority bits (P1/P2): (A) a packet without a time-stamp field and (B) a packet with a time-stamp field. This drawing also shows how the common time-reference value, time of arrival (ToA), is attached by the routing controller;
• PID virtual pipe ID
• P1/P2 priority bits
• FIG. 35 is a table classifying the data packets
• FIG. 36 is a flow diagram of an alternate embodiment of the routing controller operation
• FIG. 37 is a schematic diagram of the scheduUng and congestion controller, where each buffer is divided into two parts, one for constant bit rate (CBR) and the other for variable bit rate (VBR);
• CBR constant bit rate
• VBR variable bit rate
• FIG. 38 is a flow diagram describing an alternate embodiment of the packet scheduUng and rescheduUng controller operation for computing the forwarding time of a packet based on the foUowing input parameters: pipe-ID 35C, Time of arrival 35T and the common time reference 002;
• FIG. 39 is a flow diagram describing an alternate embodiment of the select buffer and congestion controller 45D;
• FIG.40 is a schematic iUustration of a virtual pipe with a delay which varies in time between Node B and Node C;
• FIG. 41 is a timing diagram of a virtual pipe with an increasing delay between Nodes B and C;
• FIG. 42 is a timing diagram of a virtual pipe with a decreasing delay between Nodes B and C;
• FIG. 43 is a schematic iUustration of a virtual pipe, p, with an alternate virtual pipe, /?';
• FIG. 44 describes a node, Node E, in which two virtual pipes, p and p' are converging;
• FIG. 46 is a schematic iUustration of the delay analysis and scheduling controller with its transmit buffer and select buffer controUer;
• FIG. 47 is a flow diagram describing an alternate embodiment of the Select Buffer ControUer
• FIG. 48 is a flow diagram describing the delay analysis and scheduling controUer operation for computing the forwarding time of a data packet
• FIG. 49 specifies a program executed by the delay analysis and scheduler controUer for mobile nodes with increasing and decreasing delays in their incoming tinks
• FIG. 50 specifies a program executed by the delay analysis and scheduler controUer for communication links in which their delay can change instantly, such as it is the case for SONET tinks in a self-heating SONET rings;
• FIG. 51 specifies a program executed by the delay analysis and scheduler controUer for combining two alternate paths p and p' into one path.
• FIG. 52 is a schematic iUustration of the delay monitoring controUer;
• FIG. 53 is a flow chart of the program executed by the delay monitoring controUer
• FIG. 54 is a schematic iUustration of the policing and load controUer
• FIG. 55 is a flow chart of the program executed by the poUcing and load controUer
• FIG. 56 is a schematic iUustration of connection between an end-station and a synchronous virtual pipe switch that are separated by asynchronous LAN switches;
• FIG. 57 is a schematic illustration of connections between end-stations and synchronous virtual pipe switches which are separated by some asynchronous switches and a gateway, which resynchronize the data packets before it is forwarded to the synchronous switch;
• FIG. 58 is a schematic illustration of connection between two segments of virtual pipe switches which are separated by asynchronous switches and routers;
• FIG. 59 is a diagram of the temporal relationship between the common time reference signals from a synchronous switch and the timely forwarding of packets from an end-station;
• FIG. 60 is an Ulustration of the possible time of arrival (ToA) variations to a synchronous switch of data packets, which are forwarded over asynchronous switches;
• FIG. 61 is a schematic Ulustration of a data packet resynchronization mechanism at the input port; and FIG. 62 specifies a program executed by the delay analysis and scheduler controller for the case of finding the schedule exactly on the delay bound by using the time-stamp at the data packet header.
• the present invention relates to a system and method for transmitting and forwarding packets over a packet switching network.
• the switches of the network maintain a common time reference, which is obtained either from an external source (such as GPS - Global Positioning System) or is generated and distributed internaUy.
• the time intervals are arranged in simple periodicity and complex periodicity (like seconds and minutes of a clock).
• a packet that arrives to an input port of a switch is switched to an output port based on specific routing information in the packet's header (e.g., IPv4 destination address in the Internet, VCI/VPI labels in ATM).
• Each switch along a route from a source to a destination forwards packets in periodic time intervals that are predefined using the common time reference.
• the time interval duration can be longer than the time duration required for transmitting a packet, in which case the exact position of a packet in the time interval is not predetermined.
• Packets that are forwarded inside the network over the same route and in the same periodic time intervals constitute a virtual pipe and share the same pipe-ID.
• Pipe- ID can be either expUcit, such as a tag or a label that is generated inside the network, or impUcit such as a group of IP addresses.
• a virtual pipe can be used to transport data packets from multiple sources and to multiple destinations.
• a virtual pipe provides deterministic quality of service guarantees.
• the time interval in which a switch forwards a specific packet is determined by the packet's pipe-ID, the time it reaches the switch, and the current value of the common time reference.
• congestion-free packet switching is provided for pipe-IDs in which capacity in their corresponding forwarding links and time intervals is reserved in advance.
• packets that are transferred over a virtual pipe reach their destination in predefined time intervals, which guarantees that the delay jitter is smaUer than or equal to one time interval.
• Packets that are forwarded from one source to multiple destinations share the same pipe ID and the links and time intervals on which they are forwarded comprise a virtual tree. This faciUtates congestion-free forwarding from one input port to multiple output ports, and consequently, from one source to multipUcity of destinations. Packets that are destined to multiple destinations reach aU of their destinations in predefined time intervals and with delay jitter that is no larger than one time interval.
• a system is provided for managing data transfer of data packets from a source to a destination. The transfer of the data packets is provided during a predefined time interval, comprised of a pluraUty of predefined time frames. The system is further comprised of a pluraUty of switches.
• a virtual pipe is comprised of at least two of the switches interconnected via communication links in a path.
• a common time reference signal is coupled to each of the switches, and a time assignment controller assigns selected predefined time frames for transfer into and out from each of the respective switches responsive to the common time reference signal. For each switch, there is a first predefined time frame within which a respective data packet is transferred into the respective switch, and a second predefined time frame within which the respective data packet is forwarded out of the respective switch.
• the time assignment provides consistent fixed intervals between the time between the input to and output from the virtual pipe.
• Each of the switches is comprised of one or a pluraUty of addressable input and output ports.
• a routing controUer maps each of the data packets that arrives at each one of the input ports of the respective switch to a respective one or more of the output ports of the respective switch.
• the virtual pipes comprised of at least two of the switches interconnected via communication links in a path.
• the communication Unk is a connection between two adjacent switches; and each of the communications tinks can be used simultaneously by at least two of the virtual pipes.
• Multiple data packets can be transferred utiUzing at least two of the virtual pipes.
• there is a fixed time difference which is constant for all switches, between the time frames for the associated time of arrival and forwarding time out for each of the data packets.
• the fixed time difference is a variable time difference for some of the switches.
• a predefined interval is comprised of a fixed number of contiguous time frames comprising a time cycle. Data packets that are forwarded over a given virtual pipe are forwarded from an output port within a predefined subset of time frames in each time cycle. Furthermore, the number of data packets that can be forwarded in each of the predefined subset of time frames for a given virtual pipe is also predefined.
• the time frames associated with a particular one of the switches within the virtual pipe are associated with the same switch for aU the time cycles, and are also associated with one of input into or output from the particular respective switch.
• a fixed number of contiguous time cycles comprise a super cycle, which is periodic.
• Data packets that are forwarded over a given virtual pipe are forwarded from an output port within a predefined subset of time frames in each super cycle.
• the number of data packets that can be forwarded in each of the predefined subset of time frames within a super cycle for a given virtual pipe is also predefined.
• the common time reference signal is coupled from a GPS (Global Positioning System), and is in accordance with the UTC (Coordinated Universal Time) standard.
• the UTC time signal does not have to be received directly from GPS.
• Such signal can be received by using various means, as long as the delay or time uncertainty associated with that UTC time signal does not exceed half a time frame.
• the super cycle duration is equal to one second as measured using the UTC (Coordinated Universal Time) standard.
• the super cycle can also be equal to multiple UTC seconds or a fraction of a UTC second.
• a select buffer controUer maps one of the time frames for output from a first switch to a second time frame for input via the communications Unk to a second switch.
• the select buffer controUer uses the UTC time signal in order to identify the boundaries between two successive time frames.
• the select buffer controUer inserts a time frame delimiter (TFD) signal into the transmission Unk in order to the signal the second switch with the exact boundary between two time frames.
• TFD time frame delimiter
• Each of the data packets is encoded as a stream of data, and a time frame detimiter is inserted into the stream of data responsive to the select buffer controller. This can be implemented by using a redundant serial codewords as it is later explained.
• the communication links can be of fiber optic, copper, and wireless communication tinks for example, between a ground station and a sateltite, and between two sateUites orbiting the earth.
• the communication link between two nodes does not have to be a serial communication link.
• a parallel communication Unk can be used - such Unk can simultaneously carry multiple data bits, associated clock signal, and associated control signals.
• the data packets can be Internet protocol (IP) data packets, and asynchronous transfer mode (ATM) ceUs, and can be forwarded over the same virtual pipe having an associated pipe identification (PID).
• PID can be an Internet protocol (IP) address, Internet protocol group multicast address, an asynchronous transfer mode (ATM), a virtual circuit identifier (VCI), and a virtual path identifier (VPI), or (used in combination as VCI/VPI).
• the routing controUer determines two possible associations of an incoming data packet: (i) the output port, and (U) the time of arrival (ToA).
• the ToA is then used by the scheduUng controUer for determining when a data packet should be forwarded by the select buffer controller to the next switch in the virtual pipe.
• the routing controller utUizes at least one of Internet protocol version 4 (IPv4), Internet protocol version 6 (IPv6) addresses, Internet protocol group multicast address, Internet MPLS (multi protocol label swapping or tag switching) labels, ATM virtual circuit identifier and virtual path identifier (VCI VPI), and IEEE 802 MAC (media access control) addresses, for mapping from an input port to an output port.
• IPv4 Internet protocol version 4
• IPv6 Internet protocol version 6
• IPv6 Internet protocol group multicast address
• Internet MPLS multi protocol label swapping or tag switching
• VCI VPI virtual circuit identifier and virtual path identifier
• IEEE 802 MAC media access control
• Each of the data packets is comprised of a header, which includes an associated time stamp.
• the time stamp can record the time in which a packet was created by its application.
• the time-stamp is generated by an Internet real-time protocol (RTP), and by a predefined one of the switches.
• RTP Internet real-time protocol
• the time-stamp can be used by a scheduling controUer in order to determine the forwarding time of a data packet from an output port.
• Each of the data packets originates from an end station, and the time-stamp is generated at the respective end station for inclusion in the respective originated data packet.
• Such generation of a time-stamp can be derived from UTC either by receiving it directly from GPS or by using the Internet's Network Time Protocol (NTP). 1 Synchronous virtual pipe
• a system for transferring data packets across a data network whUe maintaining for reserved data traffic constant bounded jitter (or delay uncertainty) and no congestion-induced loss of data packets.
• Such properties are essential for many multimedia applications, such as, telephony and video teleconferencing.
• one or a plurality of virtual pipes 25 are provided, as shown in FIGS. 1-2, over a data network with general topology. Such data network can span the globe.
• Each virtual pipe 25 is constructed over one or more switches 10, shown in FIG. 1, which are interconnected via communication links 41 in a path.
• FIG. 1 iUustrates a virtual pipe 25 from the output port 40 of switch A, through switches B and C. This virtual pipe ends at the output port 40 of node D.
• the virtual pipe 25 transfers data packets from at least one source to at least one destination.
• FIG. 2 iUustrates three virtual pipes: virtual pipe 1 from the output of switch A to the output of switch D, virtual pipe 2 from the output of switch B to the output of switch D, and virtual pipe 3 from the output of switch A to the output of switch C.
• the data packet transfers over the virtual pipe 25 via switches 10 are designed to occur during a pluraUty of predefined time intervals, wherein each of the predefined time intervals is comprised of a plurality of predefined time frames.
• the timely transfers of data packets are achieved by coupling a common time reference 002 (CTR) signal to each of the switches 10.
• CTR common time reference 002
• FIG. 3 illustrates the structure of a pipetine switch 10.
• the switch 10 is comprised of one or a plurality of input ports 30, one or a plurality of output ports 40, switching fabric 50, and global positioning system (GPS) time receiver 20 with a GPS antenna 001.
• GPS global positioning system
• the GPS time receiver provides a common time reference signal (CTR)
• the common time reference 002 that is coupled to the switches 10 provides the following property: the local clock ticks 004, shown in FIG. 4, at aU the pipetine switches (e.g., switches A, B, C, and D in FIGS. 1 and 2) when projected on the real-time axis 005 wiU aU occur within predefined synchronization envelopes 003.
• the local clock ticks 004 occur within the synchronization envelopes 003, and therefore, outside relative to the synchronization envelopes aU local clocks have the same clock value.
• Tf time frames
• the time frames are grouped into time cycles. Each time cycle has predefined number of time frames.
• Contiguous time cycles are grouped together into contiguous super cycles, and as shown in FIG. 5, there are / time cycles in each super cycle.
• FIG. 6 Ulustrates how the common time reference can be aligned with the UTC (Coordinated Universal Time) standard.
• the duration of every super cycle is exactly one second as measured by the UTC standard.
• the beginning of each super cycle coincides with the beginning of a UTC second, as shown in FIG. 6. Consequently, when leap seconds are inserted or deleted for UTC corrections (due to changes in the earth rotation period) the cycle and super cycle periodic scheduling wtil not be affected.
• Pipeline forwarding relates to data packets being forwarded across a virtual pipe 25 with a predefined delay in every stage (either across a communication Unk 41 or across a switch 10 from input port 30 to output port 40).
• Data packets enter a virtual pipe 25 from one or more sources and are forwarded to one or more destinations.
• This sort of pipeline forwarding used in accordance with the present invention is iUustrated in FIG. 7.
• Data packet 41A is forwarded out of switch A during time frame t-1.
• This data packet 41 A wiU reach switch B after a delay of T-ab.
• This data packet 41A wUl be forwarded out of switch B as data packet 41B during time frame t+7 and will reach switch C after a delay of T-bc.
• This data packet 41B will be forwarded out of switch C as data packet 41C during time frame t+5.
• Data packet 41C wiU reach switch
• a data packet is received by one of the input ports 30 of switch A at time frame 1, and is forwarded along this virtual pipe 25 in the following manner: (i) the data packet 41A is forwarded from the output port 40 of switch A at time frame 2 of time cycle 1, (ii) the data packet 41B is forwarded from the output port 40 of switch B, after 18 time frames, at time frame 10 of time cycle 2, (iii) the data packet 41C is forwarded from the output port 40 of switch C, after 42 time frames, at time frame 2 of time cycle 7, and (iv) the data packet 41D is forwarded from the output port 40 of switch D, after 19 time frames, at time frame 1 of time cycle 9. As iUustrated in FIG. 1,
• the data packets that enter the virtual pipe 25 can come from one or more sources and can reach switch A over one or more input links 41.
• the data packets that exit the virtual pipe 25 i.e., forwarded out of the output port 40 of switch D
• the data packets that exit the virtual pipe 25 can be forwarded simultaneously to multiple destinations, (i.e., multicast (one-to-many) data packet forwarding).
• the communication link 41 between two adjacent ones of the switches 10 can be used simultaneously by at least two of the virtual pipes.
• the three virtual pipes can multiplex (i.e., mix their traffic) over the same communication links.
• the three virtual pipes can multiplex (i.e., mix their traffic) during the same time frames and in an arbitrary manner.
• the same time frame can be used by multiple data packets from one or more virtual pipes.
• FIG. 8 iUustrates the timing of a switch of a virtual pipe wherein there are a predefined subset of time frames (i, 75, and 80) of every time cycle, during which data packets are transferred into that switch, and wherein for that virtual pipe there are a predefined subset time frames (i+3, 1, and 3) of every time cycle, during which the data packets are transferred out of that switch.
• each of the three data packets has 125 bytes or 1000 bits, and there are 80 time frames of 125 microseconds in each time cycle (i.e., time cycle duration of 10msec), then the bandwidth aUocated to this virtual pipe is 300,000 bits per second.
• the bandwidth or capacity allocated for a virtual pipe is computed by dividing the number of bits transferred during each of the time cycles by the time cycle duration.
• the bandwidth allocated to a virtual pipe is computed by dividing the number of bits transferred during each of the super cycles by the super cycle duration.
• the switch 10 structure can also be referred to as a pipeline switch, since it enables a network comprised of such switches to operate as a large distributed pipetine architecture, as it is commonly found inside digital systems and computer architectures.
• Each pipeline switch 10 is comprised of a pluraUty of addressable input ports 30 and output ports 40.
• the input port 30 is further comprised of a routing controUer 35 for mapping each of the data packets that arrives at each one of the input ports to a respective one of the output ports.
• the output port 40 is further comprised of a scheduUng controUer and transmit buffer 45.
• An output port 40 is connected to an input port 30 via a communication Unk 41, as shown in FIG. 9.
• the communication Unk can be realized using various technologies compatible with the present invention.
• the common time reference 002 is provided to the input ports 30 and output ports 40 from the GPS time receiver 20, which receives its timing signal from the GPS antenna 001.
• GPS time receivers are avaUable from variety of manufacturers, such as, TrueTime, Inc. (Santa Rosa, CA). With such equipment, it is possible to maintain a local clock with accuracy of ⁇ 1 microsecond from the UTC
• the communication links 41 used for the system disclosed is in this invention can be of various types: fiber optic, wireless, etc.
• the wireless Unks can be between at least one of a ground station and a satellite, between two sateUites orbiting the earth, or between two ground stations, as examples.
• serial transmitter 49 and serial receiver 31 are Ulustrated as coupled to each link 41.
• a variety of encoding schemes can be used for a serial line link 41 in the context of this invention, such as, SONET/SDH, 8B/10B Fiber Channel, 4B/5B FDDI (fiber distributed data interface).
• the serial transmitter/receiver (49 in FIG. 12 and 31 in FIG. 16) sends/receives control words for a variety of control purposes, mostly unrelated to the present invention description. However, one control word, time frame delimiter (TFD), is used in accordance with the present invention.
• TDD time frame delimiter
• the TFD marks the boundary between two successive time frames and is sent by a serial transmitter 49 when a CTR 002 clock tick occurs in a way that is described hereafter as part of the output port operation. It is necessary to distinguish in an unambiguous manner between the data words, which carry the information, and the control signal or words (e.g., the TFD is a control signal) over the serial Unk 41. There are many ways to do this. One way is to use the known 4B/5B encoding scheme (used in FDDI). In this scheme, every 8-bit character is divided into two 4-bit parts and then each part is encoded into a 5-bit codeword that is transmitted over the serial Unk 41.
• FIG. 10 iUustrates an encoding table from 4-bit data to 5-bit serial codewords.
• the 4B/5B is a redundant encoding scheme, which means that there are more codewords than data words. Consequently, some of the unused or redundant serial codewords can be used to convey control information.
• FIG. 11 is a table with 15 possible encoded control codewords, which can be used for transferring the time frame delimiter (TFD) over the serial link.
• TFD time frame delimiter
• the time frame delimiter cannot be embedded as redundant serial codewords, since SONET/SDH serial encoding is based on scrambting with no redundancy. Consequently, the TFD is implemented using the SONET/SDH frame control fields: transport overhead (TOH) and path overhead (POH). Note that although SONET/SDH uses a 125 microseconds frame, it cannot be used directly in accordance with the present invention, at the moment, since SONET/SDH frames are not globally aUgned and are also not aligned to UTC.
• SONET/SDH can be used compatibly with the present invention.
• the input port 30 has three parts: serial receiver 31, a routing controller 35 and separate queues to the output ports 36.
• the serial receiver 31 transfers the data packets and the time frame detimiters to the routing controUer 35.
• the routing controller 35 is constructed of a central processing unit (CPU), a random access memory (RAM) for storing the data packet, read only memory (ROM) for storing the routing controUer processing program and the routing table that is used for determining the output port that the incoming data packet should be switched to.
• CPU central processing unit
• RAM random access memory
• ROM read only memory
• the incoming data packet header includes a virtual pipe identification, PID 35C, that is used to lookup in the routing table 35D the address 35E of the queue 36 that the incoming data packet should be transferred into.
• PID 35C virtual pipe identification
• the time of arrival (ToA) 35T is attached to the packet header as Ulustrated in FIGS 15A and 15B.
• the ToA 35T is used by the scheduUng controller 45 of the output port 40 in the computation of the forwarding time out of the output port and shown in FIG. 16.
• the data packet can have various formats, such as, Internet protocol version 4 (IPv4), Internet protocol version 6 (IPv6), asynchronous transfer mode (ATM) cells, etc.
• IPv4 Internet protocol version 4
• IPv6 Internet protocol version 6
• ATM asynchronous transfer mode
• the data packets PID can be determined by one of the following: an Internet protocol (IP) address, an asynchronous transfer mode (ATM) a virtual circuit identifier, a virtual path identifier (VCI/VPI), Internet protocol version 6 (IPv6) addresses, Internet MPLS
• FIG. 14 iUustrates the flow chart for the router controUer 35 processing program executed by the routing controUer 35B.
• the program is responsive to two basic events from the serial receiver 31 of FIG. 12: the received time frame deUmiter TFD at step 35-
• the routing controUer 35 After receiving a TFD, the routing controUer 35 computes the time of arrival (ToA) 35T value at step 35-03 that is attached to the incoming data packets. For this computation it uses a constant, Dcorist, which is the time difference between the common time reference (CTR) 002 tick and the reception of the TFD at time t2 (generated on an adjacent switch by the CTR 002 on that node). This time difference is caused by the fact that the delay from the serial transmitter 49 to the serial receiver 31 is not an integer number of time frames.
• the routing controUer 35B executes three operations as set forth in step 35-04: attach the ToA, lookup the address of the queue 36 using the PID, and storing the data packet in that queue 36.
• the switching fabric is peripheral to the present invention, and so it wiU be described only briefly.
• the main property that the switching fabric should ensure is that packets for which the priority bit P (35P in FIGS. 15A and 15B) is set to high, then priority (i.e., reserved traffic) wUl be switched into the output port in a constant bounded delay - measured in time frames.
• the delay can be bounded by two time frames, one time frame at the input port and one time frame to get across the switching fabric.
• Other implementations can be used, such as based on shared bus with round robin service of the high priority data packets, or on a crossbar switch.
• shared memory Another possible switch design is shared memory, which ensures a deterministic delay bound from an input port to an output port.
• Shared memory packet switches are commerciaUy avaUable from various vendors, for example, MMC Networks Inc. (Santa).
• FIGS. 15A and 15B illustrate data packets without and with a time stamp attached, respectively.
• the output port 40 is iUustrated in FIG. 16, comprised of a scheduUng controller with a transmit buffer 45, and serial transmitter 49 (as previously described herein).
• the scheduUng controller 45 performs a mapping of each of the data packets between the associated respective time of arrival (ToA) and an associated forwarding time out of the output port via the serial transmitter 49.
• the forwarding time is determined relative to the common time reference (CTR) 002.
• CTR common time reference
• Three output port configurations are Ulustrated herein: a double-buffer scheduUng controUer, as shown in FIGS. 17 and 18, a general scheduling controller, as shown in FIGS. 19, 20, and 21, and a general scheduUng controller with time-stamp, as shown in FIGS. 22 and 23.
• the double-buffer scheduUng controUer 46 as iUustrated in the block diagram of
• FIG. 17 and flow chart of FIG. 18, is constructed of a central processing unit (CPU), a random access memory (RAM) for storing the data packet, and read only memory (ROM) for storing the controUer processing program.
• Each time frame as specified by the common time reference 002 is considered to be one of an even tick or an odd tick.
• the determination of even tick vs. odd tick is made relative to the beginning of a time cycle.
• the first time frame of a time cycle is determined to be an odd tick
• the second time frame of the time cycle is determined to be an even tick
• the third time frame of the time cycle is determined to be an odd tick
• so forth where the determination of even tick vs. odd tick alternates as shown for the duration of the time cycle.
• the first time frame of a time cycle is determined to be an even tick
• the second time frame of the time cycle is determined to be an odd tick
• the third time frame of the time cycle is determined to be an even tick
• the determination of even tick vs. odd tick alternates as shown for the duration of the time cycle.
• the actual sequence of even ticks vs. odd ticks of time frames within a time cycle may be arbitrarily started with no loss in generality.
• the double-buffer scheduUng controUer 46 operates in the following manner.
• Data packets arrive from the switching fabric 50 via link 51.
• the priority bit 35P is asserted (i.e., reserved traffic)
• the packet is switched through the packet DMUX (demultiplexer) 51S (during odd ticks of the common time reference) to buffer Ba via Unk 51-1, and during even ticks of the common time reference to buffer Bb, via link 51- 2.
• Data packets in which the priority bit 35P is not asserted i.e., non-reserved traffic
• the transmit buffer selection operation is controlled by the select signal 46A, which connects the double-buffer scheduUng controller with the packet DMUX (demultiplexer) 51S.
• Data packets are forwarded to the serial transmitter 49 through the packet MUX (multiplexer) 47S, and link 47C in FIG. 17, during odd ticks of the common time reference from buffer Bb via link 46-2, and during even ticks of the common time reference from buffer Ba via link 46-1. If during odd ticks of the common time reference buffer Bb is empty, data packets from the "best effort" buffer Be are forwarded to the serial transmitter. If during even ticks of the common time reference buffer Ba is empty, data packets from the "best effort" buffer Be are forwarded to the serial transmitter.
• the transmit buffer selection operation is controUed by the select signal 46B, which connects the double-buffer scheduling controller 46 with the packet MUX (multiplexer) 47S.
• a more general scheduling controller 45 operation is described in FIGS. 19, 20, and 21, which includes a transmit buffer 45C and a select buffer controller 45D.
• the data packet scheduling controUer 45A together with the select buffer controUer 45D, perform the mapping, using the PID 35C and the data packet time of arrival (ToA) 35T in order to determine the respective time frame a respective packet should be forwarded out of the output port.
• Both controllers 45A and 45D are constructed of a central processing unit (CPU), a random access memory (RAM) for storing the data, and read only memory (ROM) for storing the controUer processing program.
• CPU central processing unit
• RAM random access memory
• ROM read only memory
• Data packets arrive from the switching fabric 50 via Unk 51.
• Data packets which have the priority bit 35P asserted are switched by the scheduling controller 45A to one of the k transmit buffers 45C (B-1, B-2, ...., E-k).
• Each of the it buffers is designated to store packets that wUl be forwarded in each of the k time frames in every time cycle, as shown in FIG. 5.
• the flow chart for the program executed by the scheduling controUer is Ulustrated in FIG. 20.
• the PID 35C in the data packet header is used to look-up the forward parameter 45F in the forwarding table (45B of FIG. 19), as specified in step 45-04.
• the index of the transmit buffer, between B-1 and B-k is computed in step 45-05 by subtracting the time of arrival ToA 35T from the common time reference CTR 002 and by adding the forward parameter 45F, and then switching the incoming data packet to transmit buffer B- , as specified in step 45-06.
• Incoming data packets in which the priority bit 35P is not asserted are switched by the scheduUng controUer to the transmit "best effort" buffer B-E via Unk 45-be.
• FIG. 21 Ulustrates the flow chart for the select buffer controller 45D operation.
• CTR common time reference
• FIGS. 22 and 23 tilustrate a system with a scheduling controUer, wherein each of the data packets is comprised of a header, including an associated time stamp.
• the time- stamp is generated by an Internet real-time protocol (RTP) in which its data packet format is Ulustrated in FIG. 22.
• RTP Internet real-time protocol
• the time-stamp can be generated by a predefined one of the switches 10 in the system, or the time stamp can be generated at a respective end station for inclusion in the respective originated data packet
• FIG. 23 iUustrates the operation of the scheduling controUer for the case where the packet header contains a time-stamp 35TS. Data packets arrive from the switching fabric 50 via Unk 51.
• Data packets in which the priority bit 35P is set are switched by the scheduling controUer to one of the k transmit buffers 45C (B-1, B-2,..., B-k).
• Each of the k buffers is designated to store packets that wiU be forwarded in each of the k time frames in every time cycle, as shown in FIG. 5.
• the flow chart for the program executed by the scheduUng controUer is Ulustrated in FIG. 23.
• step 45-23 the index i of the transmit buffer, between B-1 and B-k, is computed in step 45-23 by subtracting the time of arrival ToA 35T from the common time reference CTR 002 and by adding the forward parameter 45F, and then switching the incoming data packet to transmit buffer B-i, as specified in step 45-24. 2 Time-based routing
• a packet that arrives to an input port of a switch is switched to an output port based on (i) its position within the predefined time interval and (u) the unique address of the incoming input port.
• Each switch along a route from a source to a destination forwards packets in periodic time intervals that are predefined using the common time reference.
• the time interval duration can be longer than the time duration required for transmitting a packet.
• FIG. 24 depicts a schematic description of a switch 10.
• the switch 10 is constructed of four components: a plurality of uniquely addressable input ports 30 (in FIG. 24 there are N such ports), a pluraUty of uniquely addressable output ports 40 (in
• FIG. 24 there are N such ports), a switching fabric 50, and a global positioning system
• GPS time receiver 20 with a GPS antenna 001.
• the GPS time receiver provides a common time reference (CTR) 002 to aU input and output ports.
• CTR common time reference
• the common time reference is partitioned into time frames. Each of the time frames is further comprised of predefined positions such that the input port can unambiguously identify the positions.
• the time and position that a data packet arrives into the input port are used by the routing controller 35 in FIG. 12 for determining the output port that incoming data packet should be switched to.
• one data packet can be stored.
• the positions can be marked explicitly with position delimiters (PDs) between the variable size data packets, as it wtil be explained below, or implicitly.
• Implicit position within a time frame can be achieved by either measuring time delays - this is suitable for sending a fixed size ATM (asynchronous transfer mode) ceUs, or by placing data packets of variable size in the predefined positions within each of the time frames - if the output port 40 does not have a data packet to transmit in a predefine position an empty or nuU data packet should be sent.
• FIG. 25 depicts a common time reference (CTR) 002 axis that is divided into time cycles. Each time cycle is divided into predefined frames. Each of the time frame has predefined positions: a, b, c, and d of either fixed size (in time duration) or variable size (in time duration), consequently, the predefined position can have ether fixed size data packets or variable size data packets, respectively.
• CTR common time reference
• the input port 30, shown in FIG. 12, has three parts: serial receiver 31, time- based routing controUer 35 and separate queues 36 to the plurality of output ports 40.
• the serial receiver 31 transfers to the time-based routing controUer 35 data packets, time frame delimiters (TFD) and position delimiters (PD).
• TFD time frame delimiters
• PD position delimiters
• the routing controUer is constructed of a central processing unit (CPU), a random access memory (RAM) for storing the data packets, read only memory (ROM) for storing the time-based routing controller processing program, and a time-based routing table is used for determining the foUowing parameters (see 35D in FIGS. 26, 27, and 29): 1. Parameter 35- 1 in table 35D (FIGS. 27 and 29) - the output port 40 that the incoming data packet should be switched to - this parameter is used for switching the data packet to the queue 36 that is leading to the corresponding output port;
• Parameter 35-3 in table 35D (FIGS. 27 and 29) - the position within the out-going time frame in which the data packet wtil be forwarded out of the output port - this parameter is attached to the data packet header in FIG. 28.
• the time-based routing controUer 35B determines the entry to the time-based routing table 35D, in FIGS. 27 and 29, in various ways, such as:
• Time stamp 35TS and position 35PC by using (1) the time stamp 35TS in the data packet header in FIG. 28B, and (2) the position value 35P within that time frame as measured by the position counter 35PC.
• Time stamp, PID shown in the packet headers in FIG. 28
• position 35PC by (1) the time stamp 35TS in the data packet header in FIG. 28B, (2) the virtual pipe ID (PID) 35C in the data packet header in FIG. 28B (the virtual pipe is discussed in details at the end of this description), and (3) the position value 35P within that time frame as measured by the position counter 35PC. This is depicted in FIG. 29.
• the data packets can have various formats, such as, Internet protocol version 4 (IPv4), Internet protocol version 6 (IPv6), asynchronous transfer mode (ATM) ceUs.
• IPv4 Internet protocol version 4
• IPv6 Internet protocol version 6
• ATM asynchronous transfer mode
• VCI VPI virtual path identifier
• IPv6 Internet protocol version 6 addresses
• MPLS multi protocol label swapping or tag switching
• IEEE 802 MAC media access control
• the time stamp 35TS in the packet header in FIG. 28B can be generated by an application using Internet real-time protocol (RTP) and is used also in the TTU-T H.323 standard. Such data packets use the format depicted in FIG. 22. Alternatively the time- stamp can be generated by a predefined one of the switches in the system, or alternatively the time stamp is generated at the respective end node for inclusion in the respective originated data packet.
• FIG. 30 is a detatied description of the program executed by the time-based routing controUer 35B. The program is responsive to three events from the serial receiver 31 and the position value 35P within that time frame as measured by the position counter 35PC.
• the time-based routing controller program FIG. 30 using the three parameters in table 35D in FIGS. 27 and 29 that is associated with this incoming packet operates as foUows:
• Receive data packet 135-03 -responsive to this event three operations are performed as shown in 135-06 of FIG. 30: (1) the out-going time frame parameter 35-2 is attached to the packet header, (2) the position within the out-going time frame parameter 35-3 is attached to the packet header, and (3) the data packet is stored in the queue 36 using the output port parameter 35-1 in table 35D in FIGS. 27 and 29. 2.2 The time-based output port
• the output is depicted in FIG. 16, it has two parts a scheduUng controller with a transmit buffer 45, and serial transmitter 49, which was described before.
• the data packet scheduUng controller 45A in FIG. 19, transfers the data packet the transmit buffer which is a random access memory (RAM) 45C, as described below.
• RAM random access memory
• the data packet scheduling controUer 45 operation is described in FIGS. 19, 31, and 32, which includes a transmit buffer 45C and a select buffer controller 45D.
• the scheduling controUer 45A together with the select buffer controller 45D perform the mapping, using the two parameters, 35-2 and 35-3, that were attached to the data packet by the routing controller 35B.
• Both controUers are constructed of a central processing unit (CPU), a random access memory (RAM) for storing the data, and read only memory (ROM) for storing the controUer processing program.
• Data packets that arrive from the switching fabric 50 via link 51 in which their priority bit 35P is asserted (i.e., reserved traffic) wtil be switched by the data packet scheduling controUer 45A to one of the k' transmit buffers 45C: B-1, B-2, ..., B-k' (one special case is when k' k, where k is the time cycle size measured in time frames).
• Each of the k' buffers is designated to store packet that wtil be forwarded in a cycUcaUy recurring order in each of the it time frames in every time cycle, as shown in FIGS. 5 and 6.
• the actual program executed by the data packet scheduling controUer is described in FIG. 31.
• the two parameters, 35-2 and 35-3, in the data packet header are used to determine in which of the transmit buffer, between B-1 and B-k', to store that data packet and in what position, as specified in 145-02 in FIG. 31.
• CTR common time reference
• transmit buffer B- i is not empty 145-13, it wtil send a data packets from transmit buffer B- i, as specified in 145-14, 145-15 and 145-16, else if the transmit buffer B- is empty, it wtil send "best effort" data packets from the "best effort" buffer B-be, as specified in 145-17, until the end of the time frame (the next CTR 002 tick) or until buffer B-E becomes empty.
• the select buffer controUer sends data packets from aU of the non-empty predefined positions in that buffer, as specified in 145-14.
• PD position delimiter
• the input port 30, shown in FIG. 12 has three parts: serial receiver 31, routing controller 35 and separate queues to the output ports 36.
• the serial receiver 31 transfers to the routing controller 35 the data packets and the time frame delimiters.
• the routing controUer is constructed of a central processing unit (CPU), a random access memory (RAM) for storing the data packet, read only memory (ROM) for storing the routing controller processing program, and routing table is used for determining the output port that the incoming data packet should be switched to.
• the incoming data packet header includes a virtual pipe identification - PID 35C in FIG. 34, that is used to lookup in the routing table 35D the address 35E of the queue the incoming data packet should be transferred into its queue 36.
• the time of arrival (ToA) 35T in FIG. 34 is attached to the packet header.
• the ToA 35T wiU be used by the scheduUng controUer 45 in FIG. 16 in the computation of the forwarding time out of the output port.
• the data packet can have various formats, such as, internet protocol version 4 (IPv4), Internet protocol version 6 (IPv6), asynchronous transfer mode (ATM) cells.
• IPv4 internet protocol version 4
• IPv6 Internet protocol version 6
• ATM asynchronous transfer mode
• the data packets PID can be determined by one of the following: an Internet protocol (IP) address, an asynchronous transfer mode (ATM) a virtual circuit identifier, and a virtual path identifier (VCI/VPI), Internet protocol version 6 (IPv6) addresses, Internet MPLS (multi protocol label swapping or tag switching) labels, and IEEE 802 MAC (media access control) address.
• IP Internet protocol
• ATM asynchronous transfer mode
• VCI/VPI virtual path identifier
• IPv6 Internet protocol version 6 addresses
• MPLS multi protocol label swapping or tag switching
• IEEE 802 MAC media access control
• FIG. 35 is a table for defining two bits, PI and P2, in the packet headers in FIG. 34.
• the two bits classify three types of data packets: P1/P2 are "00" constant bit rate (CBR) data traffic; PI, P2 are 01 variable bit rate (VBR) data traffic; and PI, P2 are "10" "best effort” data traffic.
• CBR constant bit rate
• VBR variable bit rate
• PI, P2 are "10" "best effort” data traffic.
• the above classification is used by the program executed by the routing controUer 35B, as shown in FIG. 36, in order to determine into which of the three parts of the queue to the output port 36, shown in FIG. 33, the data packet should be switched into.
• FIG. 36 is a detailed description of the program executed by the routing controller 35B.
• the program is responsive to two basic events from the serial receiver 31: receive time frame delimiter TFD 235-01, and receive data packet 235-02.
• receive time frame delimiter TFD 235-01 receive time frame delimiter
• the routing controUer computes the time of arrival (ToA) 35T value 235-03 in FIG. 34, that is attached to the incoming data packets. For this computation it uses a constant, Dconst which is the time difference between the common time reference (CTR) 002 tick and the reception of the TFD at time t2 (note that the TFD was generated on an adjacent switch by the CTR 002 on that node).
• CTR common time reference
• This time difference is caused by the fact that the delay from the serial transmitter 49 to the serial receiver 31 is not an integer number of time frames.
• the routing controller 35B executes three operations 235-04 in FIG. 36: attach the ToA, lookup the address of the queue 36 using the PID, and storing the data packet in the queue 36 to the output port 37, while using P1/P2 in the header, in FIG. 34, in order to determine in what part, CBR/VBR/Best effort, of that queue to store the incoming data packet.
• FIGS. 37-39 A more general scheduling controUer 45 operation is described in FIGS. 37-39, which includes a scheduling and rescheduling controUer 145A, a transmit buffer 145C, and a select buffer and congestion controller 145D, as shown in FIG. 37.
• the scheduling and rescheduUng controller 145A together with the select buffer controller 145D perform the mapping of the data packet into the time frame.
• the mapping is done on the scheduUng and rescheduUng controUer using the PID 35C and the data packet time of arrival (ToA) 35T in order to determine the respective time frame in which the respective packet should be forwarded out of the output port.
• Both controUers, 145A and 145D are constructed of a central processing unit (CPU), a random access memory (RAM) for storing the data, and read only memory
• ROM for storing the controUer processing program.
• Each of the k buffers is designated to store packet that wtil be forwarded in each of the k time frames in every time cycle, that where defined in FIGS. 5 and 6.
• Another possible operation is to map the incoming packets separately to each of the time frames of a super-cycle.
• k*l transmit buffers in 145C: B-1, B-2, ..., B-it*/ i.e., k buffers to each of the / cycles of a super-cycle.
• the actual program executed by the scheduling and rescheduling controller is described in FIG. 38.
• a data packet is received from either the fabric via link 51 or from the select buffer and congestion controUer 145D via link 45R, as specified in 145-03
• the 35C, 35T and 35P in the data packet header are used to look-up the forward parameter 45F in the forwarding table 145B, as specified in 145-04.
• the index i of the transmit buffer, between B-1 and B-k is computed in 145-05 by subtracting the time of arrival ToA 35T from the common time reference CTR 002 and by adding the forward parameter 45F, and then switching the incoming data packet to transmit buffer B-i, as specified in 145-05.
• Incoming data packets in which their priority bits 35P, P1/P2, are either "10"
• FIG. 39 depicts the operation of the select buffer and congestion controUer 145D operation, which is responsive to the common time reference (CTR) tick 002.
• CTR common time reference
• the present invention further relates to a system and method for transmitting and forwarding packets over a packet switching network in which some of its communication tinks have dynamically varying delays.
• Such variations in the link delay can be the consequence of having mobile switching node (e.g., satellites).
• FIG. 40 Ulustrates a virtual pipe 25 from the output port 40 of switch A, through switches B and C. This virtual pipe ends at the output port 40 of node D.
• the virtual pipe 25 transfers data packets from at least one source to at least one destination.
• the communication link that connects switch B to switch C may have a delay that varies in time with a defined delay bound.
• Such communication links are found in various network architectures, such as, mobile wireless networks, satellite networks, and self-healing SONET rings.
• satellite networks the delay between a sateUite in space and a base-station on earth changes in the foUowing manner. First the delay decreases, as the sateUite appears above the horizon and is moving towards the base-station, and then the delay increases as the satellite is moving away from the base-station until it disappears below the horizon.
• FIGS. 41 and 42 describe the delay changes on the link between Nodes B and C as it is projected on a common time reference (CTR), which is discussed in details in FIGS. 4, 5, and 6 above.
• CTR common time reference
• FIG. 41 the delay of data packet 0a is longer than data packet lb, the delay of data packet lb is longer than data packet 2c, and so on.
• FIG. 42 describes a communication link between Nodes B and C, where the time of arrival to Node C increases, i.e., the delay between Nodes B and C gets longer.
• the delay of data packet 0a is shorter than data packet lb, the delay of data packet lb is shorter than data packet 2c, and so on.
• a complete description of the above ⁇ synchronization operation is part of the output operation described below in FIGS. 46, 47, 48, 50, and 51.
• FIGS. 43, 44, and 45 describe a delay variations that are due to the forwarding of successive data packets on alternate paths or routes in the network.
• FIG. 43 shows two virtual pipes (defined below), p (from Node A to B to C to D and to E) and p' (from
• FIG. 44 shows the scenario in which the data packets on virtual pipe/?' arrive to Node E before the time they would have arrived to Node E on virtual pipe p. Consequently, the data packets on path /?' should be delayed, as shown in FIG.
• FIG. 45 shows how such resynchronization can be achieved by using a resynchronization buffer on node E.
• a data packet from virtual pipe/?', 1 /?' enters a resynchronization buffer 10R, such that, when this data packet exits this buffer, 2/?', it wtil be forwarded from the output of Node E as if this packet was forwarded on virtual pipe /?.
• FIGS. 16, 46, 47, 48, 49, 50, and 51 A complete description of the above resynchronization operation is part of the output port operation is described below in FIGS. 16, 46, 47, 48, 49, 50, and 51.
• the output port 40 is iUustrated in FIG. 16, comprised of a scheduling controller with a transmit buffer 45, and serial transmitter 49 (as previously described herein).
• the scheduUng controller 45 performs a mapping of each of the data packets between the associated respective time of arrival (ToA) and an associated forwarding time out of the output port via the serial transmitter 49.
• the forwarding time is determined relative to the common time reference (CTR) 002.
• the scheduling controller and transmit buffer 45 has various modes of operation which are described in FIGS. 46, 47, 48, 49, 50, and 51.
• the different operation modes correspond to some of the possible variations in the communications Unk delay as was discussed in FIGS. 40-45.
• the scheduUng controller and transmit buffer 45 in FIG. 46 includes three parts:
• a delay analysis and scheduUng controller 245A which further comprises a forwarding table 245B,
• a transmit buffer 245C which is typicaUy realized as a random access memory (RAM)
• RAM random access memory
• a select buffer controUer 245D which forward data packets to the serial transmitter.
• the delay analysis and scheduling controUer 245A together with the select buffer controller 245D, perform the mapping, using the PID 35C, the time-stamp 35TS and the data packet time of arrival (ToA) 35T in order to determine the respective time frame a respective packet should be forwarded out of the output port
• Both controUers 245A and 245D are constructed of a central processing unit (CPU), a random access memory (RAM) for storing the data, and read only memory (ROM) for storing the controller processing program. Data packets arrive from the switching fabric 50 via link 51.
• Data packets which have the priority bit 35P asserted are switched by the delay analysis and scheduling controller 245A to one of the l*k transmit buffers 45C (B-1, B- 2..., B-l*k).
• Each of the l*k buffers is designated to store packets that wtil be forwarded in each of the l*k time frames in every super cycle, as shown in FIG. 5 and FIG. 6.
• Having /*it transmit buffers enables the delay analysis and scheduling controller 245A to schedule data packets in a wide range of delay variations.
• the scheduUng capability of the delay analysis and scheduling controller 245A is up to one second. However, this is an extreme case and in most practical scenarios the scheduUng requirements, even with delay varying links, is only a small number of time frames.
• the transmit buffer 245C includes an additional buffer B-E for "best effort" data packets.
• the priority bit 35P in the "best effort” data packets is not asserted and this how the delay analysis and scheduling controller determines that such data packets should be stored in the "best effort” buffer.
• the "best effort" data packets are forwarded to the serial transmitter 49 whenever there are no more scheduled data packets
• FIG. 47 illustrates the flow chart for the select buffer controller 45D operation.
• CTR common time reference
• the transmit buffer B-i is not empty, at step 345-13, it wtil send a data packet from transmit buffer B-i, as specified in at step 345-14, else it wiU send a "best effort" data packet from the "best effort" buffer B-E, as specified at step 345-15.
• the flow chart for the program executed by the delay analysis and scheduUng controller is iUustrated in FIG. 48.
• the main task of the program is to compute the index, i, of the transmit buffer, B-i, between B-1 and B- T*k is computed in step 245- 05.
• FIG. 49 the case of continuous delay variations as described in FIGS. 40- 42, as specified in 45-051: 1.
• Let ⁇ sl, s2, s3, ... , s > be the set of time frames of a PED /?, which repeats in every super cycle, as it is specified in the forwarding table 245B at the p entry,
• Controller 245A searches the set ⁇ sl, s2, s3, ... , s/> in order to determine the first feasible time frame, si, that occur after (ToA 35T)+CONST (where
• CONST is a constant bound on the delay across the switching fabric
• si is the time frame the data packet is scheduled for transmission via the serial transmitter - where i is the index transmit buffer B-i.
• the set ⁇ sl, s2, s3, ... , sj> constitute plurality of time frame in which a data packet can be scheduled for transmission out of the output port of a switch.
• FIG. 50 the case of multiple path with resynchronization as described in FIGS. 43, 44, and 45:
• the present invention further relates to a system and method for monitoring, poticing and btiling of the transmission and forwarding of data packets over a packet switching network.
• the switches of the network maintain a common time reference, which is obtained either from an external source (such as GPS - Global Positioning System) or is generated and distributed internally.
• the output port 40 is iUustrated in FIG. 16, comprised of a scheduUng controller with a transmit buffer 45, serial transmitter 49 (as previously described herein), and the monitoring and policing controllers.
• the scheduling controUer 45 performs a mapping of each of the data packets between the associated respective time of arrival (ToA) and an associated forwarding time out of the output port via the serial transmitter 49.
• the forwarding time is determined relative to the common time reference (CTR) 002.
• a general scheduUng controller 45 operation was previously described in FIGS. 19-21, which includes a transmit buffer 45C and a select buffer controller 45D.
• the data packet scheduling controUer 45A together with the select buffer controUer 45D, perform the mapping, using the PID 35C and the data packet time of arrival (ToA) 35T in order to determine the respective time frame a respective packet should be forwarded out of the output port.
• Both controllers 45A and 45D are constructed of a central processing unit (CPU), a random access memory (RAM) for storing the data, and read only memory (ROM) for storing the controUer processing program.
• CPU central processing unit
• RAM random access memory
• FIGS. 52 and 53 describe the operation of a delay monitoring controller 65D. This controUer checks data packets in which their reserved priority bit, 35P in their headers, is asserted for three cases:
• Time- stamp 35TS (see box 65D-03), then comparing that it is in the predefined delay range: (65-Del > 65 - Par-L and 65-Del ⁇ 65 - Par-H) (see box 65D-04).
• Data packet is late (see box 65D-07): its delay is greater than 65-par-H, i.e., 65-Del >65 - Par-H (see box 65D-06), and
• Data packet is early (see box 65D-08): its delay is smaller than 65-par-L, i.e., 65-Del ⁇ 65 - Par-L.
• the three cases have importance on ensuring proper network operations and the adherence to the user quality of service (QoS) requirements.
• QoS quality of service
• the information coUected by the delay monitoring controller is reported to upper layer protocols, which are outside the scope of this invention.
• the two cases have importance on ensuring proper network operations and the adherence to the user quality of service (QoS) requirements.
• QoS quality of service
• L(p)+1 (see box 65P-02) using the load table 65L that stores previous values of L(p).
• the policing and load information is used also for ensuring proper network operations and the adherence to the user quality of service (QoS) requirements.
• QoS quality of service
• the information collected by the policing and load controller is reported to upper layer protocols, which are outside the scope of this invention. 6 Interconnecting a synchronous with an asynchronous switching networks
• the present invention further relates to a system and method for transmitting and forwarding packets over a heterogeneous packet switching network in which some of its some of its switches are synchronous and some switches are asynchronous.
• the invention specificaUy ensures that the synchronous switches wiU forward data packets in predefined time intervals although are arriving to the synchronous switches with relatively large, but bounded, delay uncertainty. Such delay uncertainty is the consequence of having asynchronous switches on the route of a data packet before it reaches the synchronous switch.
• a system is provided for managing in a timely manner transfer of data packets across asynchronous switches with three configurations:
• network interface 102 across asynchronous LAN switches 20 to an asynchronous to synchronous gateway 15, which converts the asynchronous data packets stream to a synchronous stream and then forward the data packets to a synchronous virtual pipe switch, as shown in FIG. 57.
• FIGS. 59-61 describe the resynchronization operation at the input port of either a synchronous virtual pipe switch 10 or a gateway
• the synchronous virtual pipe switch 10 In order to facilitates the resynchronization of data packets sent by the end- station 100, the synchronous virtual pipe switch 10 periodically sends timing messages M002 to the end-station 100, as shown in FIG. 59.
• the timing messages M002 represent the value of the common time reference (CTR) 002 as it is received by the synchronous switch 10.
• CTR common time reference
• the network interface 102 at the end-station 100 incorporates the timing information obtained from the timing message M002 into the time-stamp field 35TS (FIG. 15) in the header of the data packets, 1DP, 2DP, 3DP, ... , 9DP in FIG. 59, it sends across the asynchronous switches 20 to the synchronous virtual pipe switch 10.
• FIG. 60 show the possible time of arrival of data packets, 1DP, 2DP, 3DP, ... , 9DP, to the input port 35.
• a data packet can experience delay that is ranging between minimum delay and maximum delay, which constitute the delay bound uncertainty to be Maximum delay - Minimum delay, as shown in FIG. 60.
• FIGS. 61A and 61B show the resynchronization operation performed by the routing controUer 35 at the input port 30 using a resynchronization buffer 30R, which is executed in the foUowing two steps:
• the router controUer When there is an asynchronous to synchronous gateway 15 before the input to virtual pipe switch the router controUer operates as was previously specified herein in FIG. 14.
• the gateway receives the CTR 002 and also forward time frame delimiter (TFD) 47A to the serial receiver, as it wtil be specified below. More specifically, its operation can be identical to the output operation which will be described below.
• TFD forward time frame delimiter
• FIG. 14 iUustrates the flow chart for the router controller 35 processing program executed by the routing controller 35B.
• the program is responsive to two basic events from the serial receiver 31 of FIG. 14: the receive time frame delimiter TFD at step 35- 01, and the receive data packet at step 35-02.
• the routing controUer 35 computes the time of arrival (ToA) 35T value at step 35-03 that is attached to the incoming data packets. For this computation it uses a constant, Dconst, which is the time difference between the common time reference (CTR) 002 tick and the reception of the TFD at time t2 (generated on an adjacent switch by the CTR 002 on that node).
• CTR common time reference
• the routing controUer 35B executes three operations as set forth in step 35-04: attach the ToA, lookup the address of the queue 36 using the PID, and storing the data packet in that queue 36. 6.3 The router controller operation without a gateway
• the output operation described herein applies to both the synchronous virtual pipe switch 10, in FIGS. 56 and 58, and the asynchronous to synchronous gateway 15, in FIG. 57.
• the output port 40 was previously specified herein in FIG. 16, comprised of a scheduling controller with a transmit buffer 45, and serial transmitter 49 (as previously described herein).
• the scheduUng controller 45 performs a mapping of each of the data packets between the associated respective time of arrival (ToA) and an associated forwarding time out of the output port via the serial transmitter 49.
• the forwarding time is determined relative to the common time reference (CTR) 002. As it wtil be described, this mapping resynchronized the stream of data packets forwarded by the virtual pipe switch.
• CTR common time reference
• the scheduling controller and transmit buffer 45 has various modes of operation which are described in FIGS. 19, 48-49, and 62. The different operation modes corresponds to some of the possible configurations with the asynchronous switches, as was discussed in FIGS. 56-58.
• the scheduling controller and transmit buffer 45 in FIG. 19 includes three parts:
• a delay analysis and scheduUng controller which further comprises a forwarding table 45B; 2. a transmit buffer 45C which is typically realized as a random access memory (RAM); and 3. a select buffer controUer 45D which forward data packets to the serial transmitter.
• the delay analysis and scheduling controller 45A together with the select buffer controller 45D, perform the mapping, using the PID 35C, the time-stamp 35TS and the data packet time of arrival (ToA) 35T in order to determine the respective time frame a respective packet should be forwarded out of the output port.
• Both controllers 45A and 45D are constructed of a central processing unit (CPU), a random access memory (RAM) for storing the data, and read only memory (ROM) for storing the controUer processing program.
• Data packets arrive from the switching fabric 50 via Unk 51.
• Data packets which have the priority bit 35P asserted are switched by the delay analysis and scheduling controUer 45A to one of the k transmit buffers 45C (B-1, B-2, ...., B-k).
• Each of the k buffers is designated to store packets that wtil be forwarded in each of the it time frames in every time cycle, as shown in FIGS. 5 and 6. Having it transmit buffers enables the delay analysis and scheduling controller 45A to schedule data packets in a wide range of delay variations.
• the transmit buffer 45C includes an additional buffer B-E for "best effort" data packets.
• the priority bit 35P in the "best effort" data packets is not asserted and this is how the delay analysis and scheduling controller determine that such data packets should be stored in the "best effort” buffer.
• the "best effort" data packets are forwarded to the serial transmitter 49 whenever there are no more scheduled data packets
• FIG. 21 Ulustrates the flow chart for the select buffer controller 45D operation.
• CTR common time reference
• the flow chart for the program executed by the delay analysis and scheduUng controller is iUustrated in FIG. 48.
• the main task of the program is to compute the index, i, of the transmit buffer, B-i, between B-1 and B-k, is computed in step 245-05.
• FIG. 49 the case of arbitrary, but bounded, delay variations as described in FIGS. 56-58, as specified in 45-051: 1.
• Let ⁇ s 1 , s2, s3, ... , s > be the set of time frames of a PID p, which repeats in every time cycle, as it is specified in the forwarding table 45B at the p entry,
• controller 45A searches the set ⁇ sl, s2, s3, ... , s > in order to determine the first feasible time frame, si, that occur after (ToA 35T)+CONST (where CONST is a constant bound on the delay across the switching fabric); and
• si is the time frame the data packet is scheduled for transmission via the serial transmitter - where i is the index transmit buffer B-i.
• the set ⁇ s 1, s2, s3, ... , s > constitute plurality of time frame in which a data packet can be scheduled for transmission out of the output port of a switch.
• FIG. 62 - the case when using a time-stamp in the packet header (FIGS. 15 and 22):

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• 1999
  • 1999-06-11 WO PCT/US1999/013311 patent/WO1999065198A1/fr not_active Application Discontinuation
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