Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
  • G06F15/163—Interprocessor communication
  • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Definitions

• the present invention relates to a device for exchanging asynchronous data between two microprocessors via an interface constituted by a random access memory.
• the invention finds a particularly advantageous application whenever it is desired to exchange asynchronous data between two microprocessors without one of said microprocessors being slowed down or disturbed in the execution of its instruction cycles by the exchange of data.
• a known solution to satisfy this requirement consists in sharing the data bus, then called "multi-bus", between the two microprocessors.
• each microprocessor releases the bus at the request of a bus controller, which orchestrates the sharing of the bus between the two microprocessors.
• the microprocessors cannot guarantee a precise processing time because access to the bus is not deterministic.
• RAM dual access random access memory
• the technical problem to be solved by the object of the present invention is to propose a device for exchanging asynchronous data between two microprocessors by means of an interface constituted by a random access memory, a device which would allow obtain deterministic access to said memory, to ensure simple management of arbitration, while avoiding disturbing the operation of one of the microprocessors.
• each instruction executed by said master microprocessor comprises execution cycles followed by at least two cycles of data exchange in read / write with the second microprocessor, said microprocessor-slave, at an address of the random access memory defined by said microprocessor-slave,
• the master microprocessor is able to extend the access time of the slave microprocessor to the random access memory until the end of the last data exchange cycle.
• the management of access to the random access memory with single access is fully taken care of by the master microprocessor, the operation of which is therefore insensitive to the exchange of data. , at least two cycles of the master microprocessor being reserved for access to the RAM memory by the microprocessor-slave. This characteristic is very important if the execution time of the master microprocessor must be a time reference, in particular when it is desired to simulate a UART by software.
• Figure 1 is a general block diagram of the asynchronous data exchange device according to the invention.
• FIG. 2 is a breakdown into clock cycles of an instruction executed by the master microprocessor of the device of the invention.
• Figure 3 is a timing diagram between a microprocessor-master and microprocessor-slave.
• FIG. 1 is shown schematically an asynchronous data exchange device between a first microprocessor 10, which will be called microprocessor-master in the following, and a second microprocessor 20, called microprocessor-slave.
• a first microprocessor 10 which will be called microprocessor-master in the following
• a second microprocessor 20 called microprocessor-slave.
• the exchange of asynchronous data between the two microprocessors takes place via an interface constituted by a random access memory (RAM) 30 of the single access type.
• RAM random access memory
• Access to the RAM memory 30 is permanently under the control of the master microprocessor 10 in the sense that when the slave microprocessor 20 requests read / write access to a given address of the memory 30 (time tQ of the timing diagram of FIG. 3), this request RD / WR is recorded by the microprocessor-master 10 at the instant ti, according to the instant tg of a clock cycle of the microprocessor-master 10 for example. If, at this instant ti, access to the RAM memory 30 is not available because the microprocessor-master 10 is precisely in a situation of exchange with said memory 30, during one of the cycles of execution 1 to N-2 of the instruction represented in FIG. 2, the microprocessor-master 10 delivers to the microprocessor-slave 20 a signal S ⁇ of elongation access time to the RAM memory 30, the effect of the signal S ⁇ being to suspend the read / write cycle of the microprocessor-slave 20.
• an instruction executed by the master microprocessor 10 comprises, in addition to the execution cycles 1 to N- 2 with or without access to the memory RAM 30, an initial acquisition cycle O "FETCH" of an operating code and two final cycles, N-1 and N, of access to the memory 30 in write AM or in read AM-R by the microprocessor-slave 20.
• These cycles AM and AM-R therefore have the effect allow the exchange of asynchronous data between the two microprocessors 10, 20 at the address of the RAM memory 30 defined by the microprocessor-slave 20 and recorded by the microprocessor 10 at time ti.
• the AM and AM-R cycles of exchange with the slave microprocessor 20 being an integral part of the instructions executed by the master microprocessor 10 the latter is in no way disturbed or slowed down by the exchange of data.
• the cycle AM takes place between the instants t2 and during this interval the microprocessor-master 10 writes data which are read by the microprocessor-slave 20, while between the instants t_ and t_.
• the microprocessor-master 10 reads the data written by the microprocessor-slave 20.
• the signal S ⁇ is switched at time t5 thus marking the end of the RD / WR cycle of the microprocessor-slave 20.

Applications Claiming Priority (3)

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Family Cites Families (3)

• 1997
  • 1997-06-18 FR FR9707584A patent/FR2765006B1/fr not_active Expired - Fee Related
• 1998
  • 1998-06-15 CA CA002294245A patent/CA2294245A1/en not_active Abandoned
  • 1998-06-15 EP EP98930854A patent/EP0990208A1/de not_active Withdrawn
  • 1998-06-15 WO PCT/FR1998/001255 patent/WO1998058324A1/fr not_active Application Discontinuation

Non-Patent Citations (1)

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