EP0981077A1 - Régulateur de tension - Google Patents

Régulateur de tension Download PDF

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Publication number
EP0981077A1
EP0981077A1 EP98402065A EP98402065A EP0981077A1 EP 0981077 A1 EP0981077 A1 EP 0981077A1 EP 98402065 A EP98402065 A EP 98402065A EP 98402065 A EP98402065 A EP 98402065A EP 0981077 A1 EP0981077 A1 EP 0981077A1
Authority
EP
European Patent Office
Prior art keywords
signal
feedback
sampling
sampled
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98402065A
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German (de)
English (en)
Inventor
Ludovic Oddoart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Freescale Semiconducteurs France SAS
Original Assignee
Motorola Semiconducteurs SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Semiconducteurs SA filed Critical Motorola Semiconducteurs SA
Priority to EP98402065A priority Critical patent/EP0981077A1/fr
Publication of EP0981077A1 publication Critical patent/EP0981077A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to a regulator and a method of regulating a signal and in particular to a voltage regulator and a method of regulating a signal for use in portable communication devices.
  • a typical mobile phone has a number of voltage regulators several of which must be turned on, and therefore be consuming power while the phone is in standby mode.
  • the power consumed by such voltage regulators typically accounts a major fraction of the total current consumed by the mobile phone when it is in standby mode.
  • a conventional such voltage regulator may consume, for example, approximately 30 microamps.
  • a typical fully analogue voltage regulator such as is commonly found in portable communication devices such as mobile telephones has the basic structure of a differential amplifier arrangement having first and second differential inputs and an output from which the regulated voltage signal is taken and a feedback means in the form of a resistor ladder from which a feedback voltage is derived and input to one of the differential inputs where it is compared with a reference voltage which is applied to the other of the differential inputs.
  • a voltage regulator of this nature is stable (i.e. non oscillatory) the transfer function of the entire circuit must be such that for all frequencies below a certain cut off frequency at which the gain of the circuit has fallen to 0dB the phase change of the output signal is greater than 0.
  • the differential amplifier arrangement of such a regulator will generally comprise three amplification stages, one amplification stage provided by a power P-MOSFET, another amplification stage associated with an intermediate transistor stage and a further amplification stage provided by an operational amplifier (op-amp). Each of these amplification stages will generate an associated pole in the transfer function of the entire circuit.
  • the voltage regulator is generally designed to have the first pole ⁇ 1 at a fairly low frequency, the second pole ⁇ 2 at a much higher frequency and the third pole ⁇ 3 at frequency which is sufficiently higher than that of ⁇ 2 such that the additional phase roll off caused by ⁇ 3 only occurs at a frequency above the cut off frequency at which 0 dB gain has been reached.
  • the present invention seeks to provide a regulator and a method of regulating a signal which would enable reduced current consumption in applications such as portable communication devices.
  • a method of regulating a signal comprising the steps of generating a regulated signal by means of a differential amplifier arrangement having first and second differential inputs; sampling the regulated signal to generate a sampled regulator signal; applying the sampled regulated signal to the input of a feedback means; generating a feedback output signal whose value depends upon the sampled regulated signal; sampling the feedback output signal to generate a sampled feedback signal applying the sampled feedback signal to the first differential input of the differential amplifier arrangement and applying a referenced signal to the second differential input of the differential amplifier arrangement.
  • a regulator comprising a differential amplifier arrangement having first and second differential inputs and an output for generating a regulated signal; a first sampling means for sampling the regulated signal to generate a sampled regulated signal; a feedback means having an input for receiving the sampled regulated signal and an output for generating a feedback output signal; and a second sampling means for sampling the feedback output signal to generate a sampled feedback signal; the arrangement being such that the first differential input receives the sampled feedback signal and the second differential input receives a reference signal.
  • the transfer function of the regulator as a whole is altered significantly, but upon performing a suitable analysis of the circuit, it is found that the effect on the transfer function is that at a frequency which is related to the sampling frequency the gain of the regulator rapidly falls to 0dB. This enables the requirement on the third pole ⁇ 3 associated with the op-amp to be greatly relaxed. This in turn enables the amount of current which the op-amp needs to consume to be reduced significantly.
  • the feedback means comprises a switched capacitor arrangement. This gives rise to the significant advantage that only a very small amount of current is consumed by the feedback means.
  • a regulator comprising a differential amplifier arrangement having a first and second differential input and an output for generating a regulated signal and feedback means for generating a feedback output signal which depends upon the regulated signal and applying the feedback output signal to the first differential input, wherein a reference signal is applied to the second differential input and wherein the feedback means comprises a switched capacitor arrangement.
  • up conversion voltage regulator 10 comprises a basic voltage regulator architecture (excluding the feedback means) 1, a first sampling means 101, feedback means 100, and second sampling means 102.
  • the basic voltage regulator architecture (excluding the feedback means) 1 comprises a differential amplifier arrangement 50,60,70 and an output capacitor 80 having capacitance COUT.
  • the differential amplifier arrangement 50,60,70 comprises an op-amp 50 having a non inverting input 51, an inverting input 52, and an output 53 and an associated capacitance 55, an intermediate transistor gain stage 60 and a power transistor 70 the output 71 of the power transistor 70 forms the output to the differential amplifier arrangement 50, 60,70 and this is connected to one plate of the output capacitor 80 the other plate of which is connected to ground.
  • the first sampling means 101 comprises a first phase 1 switch P1 1 and is connected between the output 71 of the power transistor 70 and an input to the feedback means 100.
  • the second sampling means 102 comprises a phase 3 switch P3 in combination with the associated capacitance 55 of the inverting input 52 to op-amp 50.
  • the second sampling means 102 is connected between an output of the feedback means 100 and the inverting input 52 to op-amp 50.
  • Feedback means 100 comprises a second phase 1 switch P1 2 a phase 2 switch P2 a first capacitor C1 and a second capacitor C2. Also shown in FIG.1 is a current sink 90 connected between the output 71 of the power transistor 70 and ground. Current drain 90 represents a load supplied by the voltage regulator.
  • down conversion voltage regulator 20 comprises the same basic voltage regulator architecture (excluding the feedback means) 1 as for the up conversion voltage regulator 10 and the same reference numerals have been used to describe corresponding elements.
  • Down conversion voltage regulator 20 further comprises a first sampling means 201 a second sampling means 202 and a feedback means 200.
  • the first sampling means 201 comprises a first phase 1 switch P 1 1' and a second phase 1 switch P 1 2' .
  • the second sampling means 202 comprises a phase 3 switch P 3' together with the associated capacitance 55 of the inverting input 52 to op-amp 50.
  • Feedback means 200 comprises a third phase 1 switch P 1 3' a phase 2 switch P 2' prime a first capacitor C 1' a second capacitor C 2' and a third capacitor C 3'.
  • an up-down conversion regulator 30 again comprises the same basic voltage regulator architecture (excluding the feedback means) 1 of regulators 10 and 20 together with a first sampling means 301 a second sampling means 302 and a feedback means 300.
  • First sampling means 301 comprises a first phase 1 switch P 1''and a first phase 2 switch P 2 1'' .
  • the second sampling means 302 comprises a phase 4 switch P 4''together with the associated capacitance 55 of the inverting input 52 to the op-amp 50.
  • Feedback means 300 comprises a second phase 1 switch P 1 2'' a second phase 2 switch P 2 2'' a third phase 2 switch P 2 3'' a phase 3 switch P 3'' a first capacitor C 1'' a second capacitor C 2'', a third capacitor C 3'' and a fourth capacitor C 4''.
  • the basic operation of all three regulators 10,20, 30 is that of a differential amplifier arrangement having a negative feedback such that the differential amplifier arrangement 50,60,70 varies its output in such a way as to maintain the voltage signals at the non inverting 51 and inverting 52 inputs substantially equal.
  • V OUT V BG /K .
  • K may be less than unity or more than unity depending upon the structure of the feedback means.
  • the switches P1 1 to P3 of the first and second sampling means 101, 102 and feedback means 100 are all controlled by a suitable clocking or control signal which in this case includes at least three phases (or rather at least 3 signals are provided having the same frequency but differing phases, the duty cycle of each signal being sufficiently small to prevent overlay)
  • a suitable clocking or control signal which in this case includes at least three phases (or rather at least 3 signals are provided having the same frequency but differing phases, the duty cycle of each signal being sufficiently small to prevent overlay)
  • the first phase 1 switch P1 1 is closed and causes the first capacitor C1 to charge up to a voltage V OUT corresponding to the voltage of the output 71 of the differential amplifier arrangement 50,60,70; at the same time the second phase 1 switch P1 2 is also dosed and acts to discharge the second capacitor C2.
  • the phase 2 switch P2 is open such that the first and second capacitors are effectively disconnected from one another.
  • the first capacitor C1 will hold a voltage V OUT and the second capacitor C2 will hold a voltage of 0 volts.
  • the feedback means 100 is effectively disconnected again from the output 71 of the differential amplifier arrangement 50,60,70, the voltage V OUT having been sampled.
  • phase 2 commences the phase 2 switch P2 is closed and the first and second capacitors C1, C2 are connected together in parallel some of the charge stored on the first capacitor C1 will therefore flow to the second capacitor C2 until the voltage across both capacitors C1, C2 is equal.
  • phase 3 switch P3 is dosed and the voltage of V FB generated by the feedback means 100 is sampled and applied to the inverting input 52.
  • the associated capacitance 55 effectively stores this value between samples so as not to present a fluctuating input voltage since the input to the op-amp 50 draws practically no current, provided the sampling frequency is sufficiently high, the requirement for a non fluctuating input voltage will be attained.
  • phase 3 switch P3 is opened again the first phase will recommence and the cycle carry on as before.
  • V(C GS ) V OUT .C1/ C1 + C2).
  • V OUT V BG .(C1 + C2)/C1
  • V BG is a reference voltage signal supplied to the non inverting input 51 of op-amp 50 coming from a stable reference voltage generator such as a band gap reference voltage generator.
  • the operation of down conversion regulator 20 is similar to that of up conversion regulator 10 as described above.
  • the first phase 1 switch P 1' is closed and causes the third capacitor C 3' to charge up to voltage V OUT .
  • the second phase 1 switch P 1 2' is also closed and causes the first capacitor C 1' to charge up to voltage V OUT .
  • the third phase 1 switch P 1 3' is also closed and causes the second capacitor C 2' to discharge to 0 volts.
  • phase 1 switches P 1 1' P 1 2' and P 1 3' are all opened and the phase 2 switch P 2'is dosed which, as before, causes the charge stored in the first capacitor C 1'to flow the second capacitor C 2' until the voltage across both of these capacitors are equal.
  • V OUT will be less than V BG thus providing a down conversion regulator as required. Note this is not possible to achieve with a conventional resistor ladder feedback means.
  • up down conversion regulator 30 again operates in a similar way to the previously described regulators 10,20.
  • the first phase 1 switch P 1'' is turned on causing the third capacitor C3'' to charge to V OUT while the second phase 1 switch P 1 2'' is also turned on and causes the fourth capacitor C 4''to discharge to 0 volts.
  • V FB V ( C 3''/ C 4'')+ V ( C 1''/ C 2'') which is equal to KV OUT
  • K C 1''/( C 1'' + C 2'') + C 3''/( C 3'' + C 4'') .
  • the advantage of using the up/down conversion regulator 30 in place of either the up conversion regulator 10 or down conversation regulator 20 is that values of K close to unity can be achieved with capacitors having approximately the same capacitance (whereby the capacitors may be accurately matched). In the cases of the up conversion regulator 10 and down conversation regulator 20 it would be necessary to have capacitors with very different capacitances in order to achieve values of K close to unity. This would create problems with regards to accurate matching of the capacitors.
  • the up conversation regulator 10 is suitable for generating output voltages greater than 1.2 timed the reference voltage V BG applied to the non verting input 51 of the op-amp 50.
  • the down conversion regulator 20 is suitable for output voltages smaller than 0.8 times the reference voltage V BG .
  • the up/down conversion regulator is suitable for output voltages between 0.8 and 1.2 times the reference voltage V BG .
  • f s This frequency may be termed the sampling frequency f s .
  • the main constraint on the selection of f s is that f s must be chosen to be sufficiently large to maintain stable operation of the regulator.
  • the lower f s the lower is the requirement on maximising the frequency f 3 associated with the third pole W 3 associated with op-amp 50 which in turn means that the current required to be consumed by op-amp 50 maybe reduced.
  • the minimum sample frequency f s at which the regulator will be stable one needs to perform an AC sweep analysis on the complete circuit.
  • the sample and hold operation may be considered as a transfer function with a gain equal to 0dB up to half of the sampling frequency and a linear phase delay. At frequencies over the sampling frequency the gain can be considered to be so negatively large as to make the gain of the complete circuit zero or less.
  • a typical suitable sampling frequency f s may be of the order of a few Mhz.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
EP98402065A 1998-08-14 1998-08-14 Régulateur de tension Withdrawn EP0981077A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP98402065A EP0981077A1 (fr) 1998-08-14 1998-08-14 Régulateur de tension

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Application Number Priority Date Filing Date Title
EP98402065A EP0981077A1 (fr) 1998-08-14 1998-08-14 Régulateur de tension

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EP0981077A1 true EP0981077A1 (fr) 2000-02-23

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI402651B (zh) * 2009-01-16 2013-07-21 Mediatek Inc 電子電路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4728811A (en) * 1985-09-30 1988-03-01 Kabushiki Kaisha Toshiba Sample-and-hold circuit
EP0547916A2 (fr) * 1991-12-18 1993-06-23 Texas Instruments Incorporated Circuit de contrôle d'un régulateur de tension
US5686820A (en) * 1995-06-15 1997-11-11 International Business Machines Corporation Voltage regulator with a minimal input voltage requirement

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4728811A (en) * 1985-09-30 1988-03-01 Kabushiki Kaisha Toshiba Sample-and-hold circuit
EP0547916A2 (fr) * 1991-12-18 1993-06-23 Texas Instruments Incorporated Circuit de contrôle d'un régulateur de tension
US5686820A (en) * 1995-06-15 1997-11-11 International Business Machines Corporation Voltage regulator with a minimal input voltage requirement

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI402651B (zh) * 2009-01-16 2013-07-21 Mediatek Inc 電子電路
US9164523B2 (en) 2009-01-16 2015-10-20 Mediatek Inc. Voltage regulator having a plurality of capacitors configured to obtain a feedback voltage from a division voltage

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