EP0927460B1 - Steep edge time-delay relay - Google Patents

Steep edge time-delay relay Download PDF

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Publication number
EP0927460B1
EP0927460B1 EP97941798A EP97941798A EP0927460B1 EP 0927460 B1 EP0927460 B1 EP 0927460B1 EP 97941798 A EP97941798 A EP 97941798A EP 97941798 A EP97941798 A EP 97941798A EP 0927460 B1 EP0927460 B1 EP 0927460B1
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EP
European Patent Office
Prior art keywords
output
invertor
voltage
transistor
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP97941798A
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German (de)
French (fr)
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EP0927460A1 (en
Inventor
Paul-Werner Von Basse
Roland Thewes
Michael Bollu
Doris Schmitt-Landsiedel
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Siemens AG
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Siemens AG
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices

Definitions

  • Logic circuits are used to control sequential processes often delayed edges needed. With big delays but at the same time there is a slowdown of the flanks or a reduction in the slope to or Delay must be caused by a large number of simple circuits, for example using inverter chains.
  • One measure to eliminate this problem is, for example a series connection of an RC element or a Integrator and a downstream Schmitt trigger The disadvantage here is that such a circuit is relative is complex.
  • FIG. 1 is a delay stage with two inverters and two capacities are shown.
  • One on the input side with one Input E of the delay stage connected first inverter has a p-channel MOS transistor M1 and an n-channel transistor M2 on, both preferably very narrow and are long so that they are only in the conductive state carry very small currents or are very high-impedance.
  • a first one Connection of transistor M1 is with a supply voltage VDD and a second connection of transistor M1 with connected to an output V of the first inverter.
  • Corresponding is a first connection of the transistor M2 to the output V and a second connection of the transistor with the reference potential VSS connected.
  • the second inverter has a p-channel MOS transistor M3 and an n-channel MOS transistor M4, both of which are relatively low-resistance in the conductive state.
  • the transistors M1 and M2 should advantageously be conductive Condition should be at least 10 times higher than transistors M1 and M2.
  • the two gates of transistors M3 and M4 are connected to the output V connected to the first inverter stage and form the input the second inverter stage.
  • a first connection of the transistor M3 is with the supply voltage VDD and a second Connection of the transistor M3 to the output D of the delay stage wired.
  • a first entrance is accordingly of transistor M4 with output D and a second connection of the transistor M4 connected to the reference potential VSS.
  • a first capacitance and between the output D and the Transistor M4 has a second capacitance, the first capacitance being formed by a MOS transistor M5 whose gate is connected to the gate of transistor M3 and whose source and drain are connected to the output D and the second capacitance being through an n-channel MOS transistor M6 is formed, the gate of which is connected to the gate of transistor M4 and its source and drain connected to terminal D. are.
  • the main capacity of these through the transistors M5 and M6 capacities formed by the capacity formed between gate and channel as soon as the voltage between Gate and source connection greater than the threshold voltage of the transistors M5 and M6.
  • This middle range is called the capacity gap and is in Figure 2 at its limits by the letters A and B marked.
  • Figure 2 is on the ordinate VD and on the abscissa the voltage W between each Zero and VDD are plotted, whereby for small values of W for the voltage VD a value of approximately VDD and for large ones Values of W a value of approximately zero for the voltage VD results.
  • Vtn ⁇ VV ⁇ VDD - Vtp an S-shaped transition that covers the above area contains between A and B.
  • FIG Input E A rectangular input voltage VE is shown in FIG Input E, the voltage W at output V of the first inverter and the voltage VD at the output D of the delay stage in temporal correlation shown.
  • the voltage VV is relatively slow after the rising edge the voltage VE drops and relatively slowly after the falling Flank of voltage VE rises again.
  • a steep rise occurs at the output D. or steep drop in voltage VD.

Description

In Logikschaltungen werden zur Steuerung sequentieller Abläufe häufig verzögerte Flanken benötigt. Bei großen Verzögerungen tritt aber gleichzeitig auch eine Verlangsamung der Flanken bzw. eine Verringerung der Flankensteilheit auf oder die Verzögerung muß durch eine große Anzahl von einfachen Schaltungen, zum Beispiel durch Inverterketten, realisiert werden. Eine Maßnahme zur Beseitigung dieses Problems stellt beispielsweise eine Reihenschaltung aus einem RC-Glied bzw. einem Integrator und einem nachgeschalteten Schmitt-Trigger dar. Nachteilig ist hierbei, daß eine derartige Schaltung relativ aufwendig ist.Logic circuits are used to control sequential processes often delayed edges needed. With big delays but at the same time there is a slowdown of the flanks or a reduction in the slope to or Delay must be caused by a large number of simple circuits, for example using inverter chains. One measure to eliminate this problem is, for example a series connection of an RC element or a Integrator and a downstream Schmitt trigger The disadvantage here is that such a circuit is relative is complex.

Aus der US-Patentschrift 5,180,938 ist eine Anordnung nach dem Oberbegriff von Anspruch 1 bekannt, bei der eine PMOS-Kapazität zwischen V0 und VCC und eine NMOS-Kapazität zwischen V0 und VSS vorgesehen ist und die an V0 wirksame Kapazität in einem mittleren Spannungsbereich für V0 kleiner ist als außerhalb dieses Bereiches. Dieser Effekt wird dazu genutzt, daß zum einen die Verzögerungszeit weitgehend unabhängig von der Versorgungsspannung wird und zum anderen die Bearbeitungsgeschwindigkeit bei niedrigen Versorgungsspannungen vergrößert wird.An arrangement according to the preamble of claim 1 is known from US Pat. No. 5,180,938. where a PMOS capacity between V0 and VCC and an NMOS capacity between V0 and VSS is provided and the capacity effective at V0 in a medium voltage range for V0 is smaller than outside this range. This Effect is used to the one that the delay time largely independent of the supply voltage and secondly the processing speed at low Supply voltages are increased.

Aus der japanischen Patentanmeldung JP-A-7-46098 bzw. aus den Patent Abstracts of Japan, Band 95, Nr. 5, 30. Juni 1995 ist eine Verzögerungsschaltung bekannt, bei der eine Kapazität zwischen dem Eingang und dem Ausgang der zweiten Inverterstufe vorhanden ist. Aus dem gesamten Dokument ist jedoch kein Hinweis in Richtung einer Realisierung der Kapazität durch eine Parallelschaltung einer PMOS-Kapazität mit einer NMOS-Kapazität zu finden. Die Schaltung ist jedoch relativ aufwendig, da ein Widerstand zwischen einer ersten und zweiten Inverterstufe und eine dritte Inverterstufe zur Impulsformung erforderlich sind. From Japanese patent application JP-A-7-46098 or from Patent Abstracts of Japan, Volume 95, No. 5, June 30, 1995 a delay circuit known in which a capacitance between the input and the output of the second inverter stage is available. However, none is from the entire document Indication towards the realization of the capacity by a parallel connection of a PMOS capacitance with an NMOS capacitance to find. However, the circuit is relatively complex, there is a resistance between a first and second inverter stage and a third inverter stage for pulse shaping required are.

Die der Erfindung zugrundeliegende Aufgabe liegt nun darin, eine Verzögerungsstufe mit steilen Flanken anzugeben, die einen möglichst geringen Schaltungsaufwand erfordert. Diese Aufgabe wird erfindungsgemäß durch die Merkmale des Patentanspruchs 1 gelöst. Eine vorteilhafte Ausgestaltung der Erfindung ergibt sich aus dem abhängigen Anspruch.The object on which the invention is based is now to specify a deceleration level with steep flanks that a requires as little circuitry as possible. This The object is achieved by the features of the claim 1 solved. An advantageous embodiment of the invention results from the dependent claim.

Die Erfindung wird anhand der Zeichnung näher erläutert. Dabei zeigt

Figur 1
ein Schaltbild der erfindungsgemäßen Verzögerungsstufe,
Figur 2
ein Spannungs/Spannungs-Diagramm zur Erläuterung der in Figur 1 dargestellten Schaltung und
Figur 3
Spannungszeitdiagramme zur Erläuterung der in Figur 1 gezeigten Schaltung.
The invention is explained in more detail with reference to the drawing. It shows
Figure 1
2 shows a circuit diagram of the delay stage according to the invention,
Figure 2
a voltage / voltage diagram for explaining the circuit shown in Figure 1 and
Figure 3
Voltage-time diagrams to explain the circuit shown in FIG. 1.

In Figur 1 ist eine Verzögerungsstufe mit zwei Invertern und zwei Kapazitäten dargestellt. Ein eingangsseitig mit einem Eingang E der Verzögerungsstufe verbundener erster Inverter weist einen p-Kanal-MOS-Transistor M1 und einen n-Kanal-Transistor M2 auf, die beide vorzugsweise sehr schmal und lang ausgebildet sind, damit sie im leitenden Zustand nur sehr kleine Ströme führen bzw. sehr hochohmig sind. Ein erster Anschluß des Transistors M1 ist mit einer Versorgungsspannung VDD und ein zweiter Anschluß des Transistors M1 mit einem Ausgang V des ersten Inverters verbunden. Entsprechend ist ein erster Anschluß des Transistors M2 mit dem Ausgang V und ein zweiter Anschluß des Transistors mit dem Bezugspotential VSS verbunden. Der zweite Inverter weist einen p-Kanal-MOS-Transistor M3 und einen n-Kanal-MOS-Transistor M4 auf, die beide im leitenden Zustand relativ niederohmig sind. Die Transistoren M1 und M2 sollten vorteilhafterweise im leitenden Zustand mindestens um den Faktor 10 hochohmiger sein als die Transistoren M1 und M2.In Figure 1 is a delay stage with two inverters and two capacities are shown. One on the input side with one Input E of the delay stage connected first inverter has a p-channel MOS transistor M1 and an n-channel transistor M2 on, both preferably very narrow and are long so that they are only in the conductive state carry very small currents or are very high-impedance. A first one Connection of transistor M1 is with a supply voltage VDD and a second connection of transistor M1 with connected to an output V of the first inverter. Corresponding is a first connection of the transistor M2 to the output V and a second connection of the transistor with the reference potential VSS connected. The second inverter has a p-channel MOS transistor M3 and an n-channel MOS transistor M4, both of which are relatively low-resistance in the conductive state. The transistors M1 and M2 should advantageously be conductive Condition should be at least 10 times higher than transistors M1 and M2.

Die beiden Gates der Transistoren M3 und M4 sind mit dem Ausgang V der ersten Inverterstufe verbunden und bilden den Eingang der zweiten Inverterstufe. Ein erster Anschluß des Transistors M3 ist mit der Versorgungsspannung VDD und ein zweiter Anschluß des Transistors M3 mit dem Ausgang D der Verzögerungsstufe beschaltet. Entsprechend ist ein erster Eingang des Transistors M4 mit dem Ausgang D und ein zweiter Anschluß des Transistors M4 mit Bezugspotential VSS verbunden. Zwischen dem Ausgang D und dem Gate des Transistors M3 befindet sich eine erste Kapazität und zwischen dem Ausgang D und dem Gate des Transistors M4 befindet sich eine zweite Kapazität, wobei die erste Kapazität durch einen MOS-Transistor M5 gebildet wird, dessen Gate mit dem Gate des Transistors M3 und dessen Source und Drain mit dem Ausgang D verbunden sind und wobei die zweite Kapazität durch einen n-Kanal-MOS-Transistor M6 gebildet ist, dessen Gate mit dem Gate des Transistors M4 und dessen Source und Drain mit dem Anschluß D verbunden sind. The two gates of transistors M3 and M4 are connected to the output V connected to the first inverter stage and form the input the second inverter stage. A first connection of the transistor M3 is with the supply voltage VDD and a second Connection of the transistor M3 to the output D of the delay stage wired. A first entrance is accordingly of transistor M4 with output D and a second connection of the transistor M4 connected to the reference potential VSS. Between the output D and the gate of transistor M3 is located a first capacitance and between the output D and the Transistor M4 has a second capacitance, the first capacitance being formed by a MOS transistor M5 whose gate is connected to the gate of transistor M3 and whose source and drain are connected to the output D and the second capacitance being through an n-channel MOS transistor M6 is formed, the gate of which is connected to the gate of transistor M4 and its source and drain connected to terminal D. are.

Die wesentliche Kapazität von diesen durch die Transistoren M5 und M6 gebildeten Kapazitäten wird durch die Kapazität zwischen Gate und Kanal gebildet, sobald die Spannung zwischen Gate- und Source-Anschluß größer als die Schwellspannung der Transistoren M5 bzw. M6 ist. Sobald die Spannung zwischen dem Ausgang V des ersten Inverters und dem Ausgang D des zweiten Inverters positiver ist als eine Schwelle Vtn, bildet der Transistor M6 einen Kanal und damit eine große Kapazität. Unterhalb dieser Schwelle ist der Kanal nicht vorhanden und es wirken nur kleine parasitäre Kapazitäten. Entsprechendes gilt für die zweite Kapazität, die durch den Transistor M5 gebildet wird. Hierbei bildet sich beim Transistor M5 erst dann ein Kanal, wenn die Spannung zwischen dem Ausgang V und dem Ausgang D negativer ist als eine Schwelle Vtp des Transistors M5. Im mittleren Bereich, bei dem die Differenzspannung zwischen der Spannung W am Ausgang V und der Spannung VD am Ausgang D kleiner oder gleich der Schwelle Vtn des n-Kanal-Transistors M6 und größer oder gleich der Schwelle Vtp des p-Kanal-Transistors M5 ist, wirken bei beiden durch die Transistoren M5 und M6 gebildeten Kapazitäten nur die vergleichsweise kleinen parasitären Kapazitäten.The main capacity of these through the transistors M5 and M6 capacities formed by the capacity formed between gate and channel as soon as the voltage between Gate and source connection greater than the threshold voltage of the transistors M5 and M6. Once the tension between the output V of the first inverter and the output D of the second inverter is more positive than a threshold Vtn, The transistor M6 forms a channel and thus a large capacitance. The channel does not exist below this threshold and only small parasitic capacitances act. Corresponding applies to the second capacity, which is provided by the Transistor M5 is formed. This forms with the transistor M5 a channel only when the voltage between the Output V and output D is more negative than a threshold Vtp of transistor M5. In the middle area, where the Differential voltage between the voltage W at the output V and the voltage VD at the output D is less than or equal to the threshold Vtn of the n-channel transistor M6 and greater than or equal to that Threshold Vtp of the p-channel transistor M5 act on both capacitances formed by transistors M5 and M6 only the comparatively small parasitic capacities.

Dieser mittlere Bereich wird als Kapazitätslücke bezeichnet und ist in Figur 2 an seinen Bereichsgrenzen durch die Buchstaben A und B gekennzeichnet. In Figur 2 ist auf der Ordinate VD und auf der Abszisse die Spannung W jeweils zwischen Null und VDD aufgetragen, wobei sich für kleine Werte von W für die Spannung VD ein Wert von ungefähr VDD und für große Werte von W ein Wert von ungefähr Null für die Spannung VD ergibt. In einem Spannungsbereich Vtn ≤ VV ≤ VDD - Vtp erfolgt ein s-förmiger Übergang, der den obengenannten Bereich zwischen A und B enthält.This middle range is called the capacity gap and is in Figure 2 at its limits by the letters A and B marked. In Figure 2 is on the ordinate VD and on the abscissa the voltage W between each Zero and VDD are plotted, whereby for small values of W for the voltage VD a value of approximately VDD and for large ones Values of W a value of approximately zero for the voltage VD results. In a voltage range Vtn ≤ VV ≤ VDD - Vtp an S-shaped transition that covers the above area contains between A and B.

Außerhalb der sogenannten Kapazitätslücke ist infolge der großen Kapazitäten die Verzögerung der erfindungsgemäßen Verzögerungsstufe vergleichsweise groß und damit die Flankensteilheit am Ausgang D vergleichsweise gering. Innerhalb der Kapazitätslücke hingegen ist die Verzögerung der Verzögerungsstufe klein und damit die Flankensteilheit am Ausgang D vergleichsweise groß. Der steile Verlauf liegt direkt im Umschaltbereich der Inverter, so daß nachfolgende Inverter mit steilen Flanken durchschalten. Die Verzögerung und die flachen Flanken liegen außerhalb des Umschaltbereiches der CMOS-Schaltkreise und stören somit nicht.Outside the so-called capacity gap is due to the large capacities the delay of the delay stage according to the invention comparatively large and thus the slope at output D comparatively low. Within the Capacity gap, however, is the delay of the delay stage small and therefore the steepness of the slope at output D comparatively large. The steep course lies directly in the switching area the inverter so that subsequent inverters with switch through steep flanks. The delay and the flat Flanks are outside the switching range of the CMOS circuits and therefore do not interfere.

In Figur 3 ist eine rechteckförmige Eingangsspannung VE am Eingang E, die Spannung W am Ausgang V der ersten Inverstufe und die Spannung VD am Ausgang D der Verzögerungsstufe in zeitlicher Korrelation dargestellt. Hierbei wird deutlich, daß die Spannung VV relativ langsam nach der Anstiegsflanke der Spannung VE abfällt und relativ langsam nach der abfallenden Flanke der Spannung VE wieder ansteigt. In einem mittleren Bereich der langsam fallenden und langsam steigenden Bereiche der Spannung VV tritt am Ausgang D ein steiler Anstieg bzw. steiler Abfall der Spannung VD auf.A rectangular input voltage VE is shown in FIG Input E, the voltage W at output V of the first inverter and the voltage VD at the output D of the delay stage in temporal correlation shown. Here it becomes clear that the voltage VV is relatively slow after the rising edge the voltage VE drops and relatively slowly after the falling Flank of voltage VE rises again. In a medium one Range of slowly falling and slowly rising Ranges of the voltage VV a steep rise occurs at the output D. or steep drop in voltage VD.

Claims (2)

  1. Delay stage,
    in which a first invertor (M1, M2) and a second invertor (M3, M4) are connected in series, the input of the first invertor corresponding to the input (E) of the delay stage and the output of the second invertor corresponding to the output (D) of the delay stage, and the output of the first invertor is connected to the input (V) of the second invertor,
    in which the second invertor stage has a p-channel MOS transistor (M3) and an n-channel MOS transistor (M4), whose drain terminals are connected to the output (D) of the delay circuit, characterized in that
    a parallel circuit with capacitance gap comprising a p-channel MOS transistor (M5) connected as a capacitor and an n-channel MOS transistor (M6) connected as a capacitor is provided between the gates of the p-channel MOS transistor and of the n-channel MOS transistor, the said gates being connected to the input (V) of the second invertor, and the output (D) of the delay circuit.
  2. Delay stage,
    in which the MOS transistors (M1, M2) of the first invertor have an impedance at least ten times higher, in the on state, than the MOS transistors (M3, M4) of the second invertor.
EP97941798A 1996-09-18 1997-08-20 Steep edge time-delay relay Expired - Lifetime EP0927460B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19638163 1996-09-18
DE19638163A DE19638163C1 (en) 1996-09-18 1996-09-18 Delay level with steep edges
PCT/DE1997/001802 WO1998012812A1 (en) 1996-09-18 1997-08-20 Steep edge time-delay relay

Publications (2)

Publication Number Publication Date
EP0927460A1 EP0927460A1 (en) 1999-07-07
EP0927460B1 true EP0927460B1 (en) 2000-11-08

Family

ID=7806081

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Application Number Title Priority Date Filing Date
EP97941798A Expired - Lifetime EP0927460B1 (en) 1996-09-18 1997-08-20 Steep edge time-delay relay

Country Status (8)

Country Link
US (1) US6181183B1 (en)
EP (1) EP0927460B1 (en)
JP (1) JP3819036B2 (en)
KR (1) KR100468068B1 (en)
CN (1) CN1114268C (en)
DE (2) DE19638163C1 (en)
TW (1) TW350169B (en)
WO (1) WO1998012812A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100548530B1 (en) * 1999-12-15 2006-02-02 매그나칩 반도체 유한회사 Schmitt trigger
TWI309831B (en) 2002-09-25 2009-05-11 Semiconductor Energy Lab Clocked inverter, nand, nor and shift register
EP2104110B1 (en) 2004-06-14 2013-08-21 Semiconductor Energy Laboratory Co, Ltd. Shift register and semiconductor display device
JP2006041175A (en) * 2004-07-27 2006-02-09 Toshiba Corp Semiconductor integrated circuit device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58156226A (en) * 1982-03-12 1983-09-17 Hitachi Ltd Delay circuit
JP2685203B2 (en) * 1988-02-22 1997-12-03 富士通株式会社 Delay circuit
US5051625B1 (en) * 1988-10-28 1993-11-16 Nissan Motor Co.,Ltd. Output buffer circuits for reducing noise
KR940005004B1 (en) * 1991-03-21 1994-06-09 삼성전자 주식회사 Signal delay circuit
JPH0746098A (en) * 1993-08-03 1995-02-14 Nec Corp Delay circuit

Also Published As

Publication number Publication date
TW350169B (en) 1999-01-11
JP3819036B2 (en) 2006-09-06
KR20000023761A (en) 2000-04-25
US6181183B1 (en) 2001-01-30
EP0927460A1 (en) 1999-07-07
CN1231081A (en) 1999-10-06
KR100468068B1 (en) 2005-01-24
DE59702616D1 (en) 2000-12-14
DE19638163C1 (en) 1998-02-05
CN1114268C (en) 2003-07-09
WO1998012812A1 (en) 1998-03-26
JP2001500695A (en) 2001-01-16

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