EP0917063A3 - Data processing system and microprocessor - Google Patents

Data processing system and microprocessor Download PDF

Info

Publication number
EP0917063A3
EP0917063A3 EP98308924A EP98308924A EP0917063A3 EP 0917063 A3 EP0917063 A3 EP 0917063A3 EP 98308924 A EP98308924 A EP 98308924A EP 98308924 A EP98308924 A EP 98308924A EP 0917063 A3 EP0917063 A3 EP 0917063A3
Authority
EP
European Patent Office
Prior art keywords
data transfer
transfer
input
output device
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98308924A
Other languages
German (de)
French (fr)
Other versions
EP0917063A2 (en
Inventor
Takaaki Suzuki
Tomoya Takasuga
Atsushi Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Publication of EP0917063A2 publication Critical patent/EP0917063A2/en
Publication of EP0917063A3 publication Critical patent/EP0917063A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)

Abstract

An input/output device used as a transfer request source outputs a data transfer set command for specifying each transfer channel, each transfer address, the number of transfers, etc. onto a bus together with a data transfer request without being via a CPU. According to the data transfer set command, data transfer control information is set to direct memory access control means, and DMA transfer is started between the input/output device and a memory designated by the transfer address, for example. When the input/output device used as the data transfer request source desires to perform data transfer without noting the state of processing by a microcomputer, it can perform data transfer processing with its timing and the data transfer with the input/output device as a principal base is allowed.
EP98308924A 1997-11-06 1998-10-30 Data processing system and microprocessor Withdrawn EP0917063A3 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP30386697 1997-11-06
JP303866/97 1997-11-06
JP30386697 1997-11-06

Publications (2)

Publication Number Publication Date
EP0917063A2 EP0917063A2 (en) 1999-05-19
EP0917063A3 true EP0917063A3 (en) 2001-11-28

Family

ID=17926226

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98308924A Withdrawn EP0917063A3 (en) 1997-11-06 1998-10-30 Data processing system and microprocessor

Country Status (5)

Country Link
US (3) US6477599B1 (en)
EP (1) EP0917063A3 (en)
KR (1) KR19990044934A (en)
CN (1) CN1218227A (en)
TW (1) TW406229B (en)

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JP2001014212A (en) * 1999-06-25 2001-01-19 Canon Inc Device and method for controlling memory, and plotting device and printer using the same
US6766383B1 (en) * 1999-09-27 2004-07-20 Conexant Systems, Inc. Packet-based direct memory access
WO2001067260A1 (en) * 2000-03-09 2001-09-13 Fujitsu Limited I/o control device and i/o control method
US20020124083A1 (en) * 2000-09-06 2002-09-05 Sun Microsystems, Inc. Method and apparatus for increasing the efficiency of transactions and connection sharing in an enterprise environment
KR100406936B1 (en) * 2001-06-07 2003-11-21 삼성전자주식회사 Data relay apparatus and method thereof
US6941438B2 (en) * 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
EP1471421A1 (en) * 2003-04-24 2004-10-27 STMicroelectronics Limited Speculative load instruction control
KR100630071B1 (en) * 2003-11-05 2006-09-27 삼성전자주식회사 High speed data transmission method using direct memory access method in multi-processors condition and apparatus therefor
CN100337217C (en) * 2003-07-28 2007-09-12 深圳市朗科科技有限公司 Memory control chip and data memory control method
JP4391200B2 (en) 2003-11-05 2009-12-24 株式会社日立製作所 Disk array device and disk array device control method
DE102004006767B4 (en) * 2004-02-11 2011-06-30 Infineon Technologies AG, 81669 Method and device for transporting data sections by means of a DMA controller
CN1779666A (en) * 2004-11-19 2006-05-31 宇力电子股份有限公司 Data access method
US7249210B2 (en) * 2005-03-01 2007-07-24 Qualcomm Incorporated Bus access arbitration scheme
EP1899827B1 (en) * 2005-06-30 2010-09-08 Freescale Semiconductor, Inc. Device and method for executing a dma task
DE602005027003D1 (en) * 2005-06-30 2011-04-28 Freescale Semiconductor Inc DEVICE AND METHOD FOR CONTROLLING AN EXECUTION OF A DMA TASK
CN101218570B (en) * 2005-06-30 2010-05-26 飞思卡尔半导体公司 Device and method for arbitrating between direct memory access task requests
EP1899825B1 (en) * 2005-06-30 2009-07-22 Freescale Semiconductor, Inc. Device and method for controlling multiple dma tasks
US8510481B2 (en) * 2007-01-03 2013-08-13 Apple Inc. Memory access without internal microprocessor intervention
US20080270827A1 (en) * 2007-04-26 2008-10-30 International Business Machines Corporation Recovering diagnostic data after out-of-band data capture failure
US8977790B2 (en) * 2008-02-15 2015-03-10 Freescale Semiconductor, Inc. Peripheral module register access methods and apparatus
US8521921B1 (en) * 2009-05-22 2013-08-27 Marvell International Ltd. Automatic direct memory access (DMA)
US10713202B2 (en) * 2016-05-25 2020-07-14 Samsung Electronics Co., Ltd. Quality of service (QOS)-aware input/output (IO) management for peripheral component interconnect express (PCIE) storage system with reconfigurable multi-ports
US11072439B2 (en) 2018-09-07 2021-07-27 The Boeing Company Mobile fixture apparatuses and methods
US10782696B2 (en) 2018-09-07 2020-09-22 The Boeing Company Mobile fixture apparatuses and methods
US10472095B1 (en) 2018-09-07 2019-11-12 The Boeing Company Mobile fixture apparatuses and methods
CN111143897B (en) * 2019-12-24 2023-11-17 海光信息技术股份有限公司 Data security processing device, system and processing method
CN113703925B (en) * 2021-10-27 2022-01-25 长沙理工大学 Cooperative operation method and system of web3D multi-virtual-single-chip-microcomputer system

Citations (3)

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Publication number Priority date Publication date Assignee Title
US5099417A (en) * 1987-03-13 1992-03-24 Texas Instruments Incorporated Data processing device with improved direct memory access
US5535417A (en) * 1993-09-27 1996-07-09 Hitachi America, Inc. On-chip DMA controller with host computer interface employing boot sequencing and address generation schemes
US5634076A (en) * 1994-10-04 1997-05-27 Analog Devices, Inc. DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer

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US4313160A (en) * 1976-08-17 1982-01-26 Computer Automation, Inc. Distributed input/output controller system
US4245300A (en) * 1978-06-05 1981-01-13 Computer Automation Integrated and distributed input/output system for a computer
US4821170A (en) * 1987-04-17 1989-04-11 Tandem Computers Incorporated Input/output system for multiprocessors
EP0458304B1 (en) * 1990-05-22 1997-10-08 Nec Corporation Direct memory access transfer controller and use
CA2060820C (en) * 1991-04-11 1998-09-15 Mick R. Jacobs Direct memory access for data transfer within an i/o device
US5307458A (en) * 1991-12-23 1994-04-26 Xerox Corporation Input/output coprocessor for printing machine
JPH07122865B2 (en) * 1992-01-02 1995-12-25 インターナショナル・ビジネス・マシーンズ・コーポレイション Computer system having bus interface adapted to control operating speed of bus operation
US5444855A (en) * 1992-04-17 1995-08-22 International Business Machines Corporation System for guaranteed CPU bus access by I/O devices monitoring separately predetermined distinct maximum non CPU bus activity and inhibiting I/O devices thereof
US6038622A (en) * 1993-09-29 2000-03-14 Texas Instruments Incorporated Peripheral access with synchronization feature
KR970002689B1 (en) * 1994-06-30 1997-03-08 Hyundai Electronics Ind Cdma
JPH08110886A (en) * 1994-10-07 1996-04-30 Ricoh Co Ltd Dma controller and facsimile equipment
EP0776504B1 (en) * 1995-05-26 2004-08-18 National Semiconductor Corporation Integrated circuit with multiple functions sharing multiple internal signal buses for distributing bus access control and arbitration control
JPH10320349A (en) * 1997-05-15 1998-12-04 Ricoh Co Ltd Processor and data transfer system using the processor
JP3712842B2 (en) * 1997-08-05 2005-11-02 株式会社リコー Data transfer control method, data transfer control device, and information recording medium

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5099417A (en) * 1987-03-13 1992-03-24 Texas Instruments Incorporated Data processing device with improved direct memory access
US5535417A (en) * 1993-09-27 1996-07-09 Hitachi America, Inc. On-chip DMA controller with host computer interface employing boot sequencing and address generation schemes
US5634076A (en) * 1994-10-04 1997-05-27 Analog Devices, Inc. DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer

Also Published As

Publication number Publication date
US20020133661A1 (en) 2002-09-19
EP0917063A2 (en) 1999-05-19
US6477599B1 (en) 2002-11-05
US6493774B2 (en) 2002-12-10
TW406229B (en) 2000-09-21
CN1218227A (en) 1999-06-02
KR19990044934A (en) 1999-06-25
US20010010062A1 (en) 2001-07-26

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