EP0912945A2 - Verfahren und einrichtung zur steuerung von der zeitsynchronisation zwischen einer verarbeitungseinheit und externen mitteln - Google Patents
Verfahren und einrichtung zur steuerung von der zeitsynchronisation zwischen einer verarbeitungseinheit und externen mittelnInfo
- Publication number
- EP0912945A2 EP0912945A2 EP97934573A EP97934573A EP0912945A2 EP 0912945 A2 EP0912945 A2 EP 0912945A2 EP 97934573 A EP97934573 A EP 97934573A EP 97934573 A EP97934573 A EP 97934573A EP 0912945 A2 EP0912945 A2 EP 0912945A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- processing unit
- external means
- device providing
- providing time
- time synchronisation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9609018A FR2751444B1 (fr) | 1996-07-18 | 1996-07-18 | Procede et dispositif de controle de la synchronisation temporelle entre une unite de traitement, par exemple un microprocesseur, et des moyens exterieurs |
| FR9609018 | 1996-07-18 | ||
| PCT/FR1997/001320 WO1998003922A2 (fr) | 1996-07-18 | 1997-07-16 | Procede et dispositif de controle de la synchronisation temporelle entre une unite de traitement et des moyens exterieurs |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0912945A2 true EP0912945A2 (de) | 1999-05-06 |
| EP0912945A3 EP0912945A3 (de) | 2002-11-27 |
Family
ID=9494196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP97934573A Withdrawn EP0912945A3 (de) | 1996-07-18 | 1997-07-16 | Verfahren und einrichtung zur steuerung von der zeitsynchronisation zwischen einer verarbeitungseinheit und externen mitteln |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6324591B1 (de) |
| EP (1) | EP0912945A3 (de) |
| FR (1) | FR2751444B1 (de) |
| WO (1) | WO1998003922A2 (de) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7818457B1 (en) * | 2001-05-22 | 2010-10-19 | Rockwell Automation Technologies, Inc. | Apparatus for multi-chassis configurable time synchronization |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3564161A (en) * | 1967-12-14 | 1971-02-16 | Victor Company Of Japan | Cue signal recording and reproducing system for magnetic recording and reproducing apparatus |
| US4315308A (en) * | 1978-12-21 | 1982-02-09 | Intel Corporation | Interface between a microprocessor chip and peripheral subsystems |
| US5235698A (en) * | 1989-09-12 | 1993-08-10 | Acer Incorporated | Bus interface synchronization control system |
| JP3018404B2 (ja) * | 1990-06-21 | 2000-03-13 | 日本電気株式会社 | マイクロプロセッサ |
| US5333299A (en) * | 1991-12-31 | 1994-07-26 | International Business Machines Corporation | Synchronization techniques for multimedia data streams |
| US5838894A (en) * | 1992-12-17 | 1998-11-17 | Tandem Computers Incorporated | Logical, fail-functional, dual central processor units formed from three processor units |
| FR2725825B1 (fr) * | 1994-10-12 | 1997-01-10 | Majos Jacques | Dispositif de memoire asynchrone a acces sequentiel et procede de stockage et de lecture correspondant |
| US5794002A (en) * | 1996-03-22 | 1998-08-11 | Raytheon Company | System and technique for synchronizing data to instructions in a real time computing application |
-
1996
- 1996-07-18 FR FR9609018A patent/FR2751444B1/fr not_active Expired - Fee Related
-
1997
- 1997-07-16 EP EP97934573A patent/EP0912945A3/de not_active Withdrawn
- 1997-07-16 US US09/230,181 patent/US6324591B1/en not_active Expired - Fee Related
- 1997-07-16 WO PCT/FR1997/001320 patent/WO1998003922A2/fr not_active Ceased
Non-Patent Citations (1)
| Title |
|---|
| See references of WO9803922A2 * |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2751444A1 (fr) | 1998-01-23 |
| US6324591B1 (en) | 2001-11-27 |
| FR2751444B1 (fr) | 1998-09-11 |
| WO1998003922A2 (fr) | 1998-01-29 |
| WO1998003922A3 (fr) | 2002-10-10 |
| EP0912945A3 (de) | 2002-11-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| 17P | Request for examination filed |
Effective date: 19990105 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): CH DE GB IT LI NL |
|
| GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
| 17Q | First examination report despatched |
Effective date: 20010404 |
|
| GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
| GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 20011023 |
|
| PUAK | Availability of information related to the publication of the international search report |
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| AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): CH DE GB IT LI NL |