EP0910820A1 - Low voltage bias circuit for generating supply-independent bias voltages and currents - Google Patents

Low voltage bias circuit for generating supply-independent bias voltages and currents

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Publication number
EP0910820A1
EP0910820A1 EP97919572A EP97919572A EP0910820A1 EP 0910820 A1 EP0910820 A1 EP 0910820A1 EP 97919572 A EP97919572 A EP 97919572A EP 97919572 A EP97919572 A EP 97919572A EP 0910820 A1 EP0910820 A1 EP 0910820A1
Authority
EP
European Patent Office
Prior art keywords
transistor
current
coupled
terminal
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP97919572A
Other languages
German (de)
French (fr)
Other versions
EP0910820B1 (en
Inventor
Evert Seevinck
Monuko Du Plessis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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Publication of EP0910820A1 publication Critical patent/EP0910820A1/en
Application granted granted Critical
Publication of EP0910820B1 publication Critical patent/EP0910820B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Definitions

  • Low voltage bias circuit for generating supply-independent bias voltages and currents.
  • the invention relates to bias circuits for generating bias voltages and currents.
  • a bias circuit can be used, for example, in mixed-mode CMOS integrated circuits in which analog and digital circuits are integrated on the same semiconductor body.
  • a key building block needed in such circuits is a bias circuit providing supply-independent bias voltages and currents.
  • high-frequency supply interference generally caused by the digital part of the circuit, has to be rejected to enable good-quality performance of the analog part.
  • Figure 1 shows a threshold-referenced bias circuit known from P.R. Gray and R.G. Meyer, Analysis and design of analog integrated circuits, Second Edition, Wiley, New York, 1984, Figure 4.24a. It is not suitable for low supply voltage however, since it includes two stacked gate-source voltage drops of the transistors P A and N A , and a drain-source saturation voltage of transistor N B . Also this known bias circuit is not well-regulated against supply variations. It is an object of the invention to provide a bias circuit capable of generating supply-independent bias voltages and currents down to a low supply voltage.
  • a bias circuit comprising: a first supply terminal, a second supply terminal, and a bias voltage terminal; a first current mirror comprising first and second transistors of a first conductivity type, having a current input terminal, a current output terminal coupled to the bias voltage terminal, and a common terminal coupled to the second supply terminal; a second current mirror comprising third and fourth transistors of a second conductivity type opposite to the first conductivity type, having a current input terminal, a current output terminal coupled to the current output terminal of the first current mirror and to the bias voltage terminal, and a common terminal coupled to the first supply terminal; current providing means coupled between the first supply terminal and the current input terminal of the first current mirror for providing a current to the input terminal of the first current mirror; a fifth transistor of the first conductivity type having a gate, a source coupled to the second supply terminal, and a drain coupled to the current input terminal of the second current mirror; resistive means coupled in parallel to the gate and the source of the fifth transistor; and - a sixth transistor of the second
  • the bias circuit according to the invention operates down to a supply voltage equal to the sum of the threshold voltage and the saturation voltage. It generates a supply- independent threshold-referenced bias voltage relative to the first supply terminal, similar as the known bias circuit depicted in Figure 1.
  • This bias voltage is equal to the gate-source voltage of the sixth transistor needed for a current having a value equal to the threshold voltage of the fifth transistor divided by the resistance of the resistive means. Changes in the supply voltage cause corresponding changes in the gate-source voltage of the fifth transistor. Therefore the current through the resistive means and the sixth transistor will change proportionally causing a change in the gate-source voltage of the sixth transistor and the bias voltage.
  • the bias circuit may further comprise a seventh transistor of the second conductivity type, having a gate coupled to the bias voltage terminal, a source coupled to the first supply terminal, and a drain coupled to the drain of the fifth transistor.
  • the seventh transistor may be added to provide a slight amount of positive feedback in order to increase the current of the fifth transistor for very low supply voltage and to maintain a constant bias voltage.
  • Figure 1 shows a circuit diagram of a conventional bias circuit
  • Figure 2 shows a circuit diagram of a bias circuit according to the invention.
  • Figure 1 shows a conventional bias circuit.
  • a supply voltage V DD is connected between a positive supply terminal VP and a negative supply terminal VN which serves as signal ground.
  • the source of a PMOS transistor P A is connected to the positive supply terminal VP, whereas the interconnected gate and drain of transistor P A are connected to a bias voltage terminal BVT.
  • the bias voltage V B is therefore equal to the gate-source voltage of transistor P A .
  • the current supplied by resistor R B is forced to flow in transistor N A . and, in order for this to occur, the transistor N B must supply enough current into resistor R A so that the gate-source voltage of transistor N A is adapted to the current supplied by resistor R B .
  • the current through transistor P A is equal to the current flowing through resistor R A which is proportional to the gate-source voltage of transistor N A .
  • the bias voltage circuit thus generates a threshold-referenced bias voltage V B relative to the supply voltage V DD -
  • the current through transistor P A is determined by the loop comprising the NMOS transistors N A and N B , and the resistors R A and R B .
  • Scaled copies of the current through transistor P A may be obtained by means of one or more PMOS transistors P B with a source, gate and drain connected to, respectively, the positive supply terminal VP, the bias voltage terminal BVT and an bias current terminal BCT.
  • the lowest possible supply voltage V DD is equal to the sum of the gate-source voltages of the transistors N A and P A and the drain-source saturation voltage of transistor N B .
  • An increasing supply voltage V DD causes an increasing current through transistor N A and an increasing voltage over resistor R A . This in turn causes an increasing current through transistor P A and an increasing bias voltage V B .
  • the bias circuit of Figure 1 is therefore not well-regulated against supply voltage variations.
  • Figure 2 shows a bias circuit according to the invention.
  • the bias circuit comprises a first current mirror CMl having a current input terminal IT1 , a current output terminal OT1 coupled to the bias voltage terminal BVT, and a common terminal coupled to the second supply terminal VN; and a second current mirror CM2 having a current input terminal IT2, a current output terminal coupled to the current output terminal OT1 of the first current mirror CMl and to the bias voltage terminal BVT, and a common terminal CT2 coupled to the first supply terminal VP.
  • the current input terminal IT1 of current mirror CMl is coupled to the drain of a PMOS transistor P j , the source of which is connected to the positive supply terminal VP and the gate of which is connected to the negative supply terminal VN.
  • the transistor P j provides a current to the current mirror CMl .
  • the transistor Pj may be replaced by a resistor.
  • the current input terminal IT2 of current mirror CM2 is coupled to the drain of a NMOS transistor N 3 , the source of which is coupled to the negative supply terminal VN.
  • a resistor RS is connected between the gate and the source of transistor N 3 .
  • the bias circuit further comprises a PMOS transistor P 2 with a gate coupled to the bias voltage terminal BVT, a source coupled to the first supply terminal VP, and a drain coupled to the gate of transistor N 3 , an optional PMOS transistor P 3 with a gate coupled to the bias voltage terminal BVT, a source coupled to the first supply terminal VP, and a drain coupled to the drain of transistor N 3 , an optional PMOS transistor P 6 with a gate coupled to the bias voltage terminal BVT and a source and drain coupled to the positive supply terminal VP, and one or more optional PMOS transistors P 7 with a gate coupled to the bias voltage terminal BVT, a source coupled to the first supply terminal VP, and a drain coupled to the bias current terminal BCT.
  • a PMOS transistor P 2 with a gate coupled to the bias voltage terminal BVT, a source coupled to the first supply terminal VP, and a drain coupled to the gate of transistor N 3
  • an optional PMOS transistor P 3 with a gate coupled to the bias voltage terminal BVT, a source coupled to the
  • the current mirror CMl is implemented with NMOS transistors N, and N 2 .
  • the sources of transistors N j and N 2 are connected to the common terminal CTl .
  • the gates of the transistors N ] and N 2 are interconnected and also connected to the drain of transistor N, .
  • the drain of transistor N> is connected to the current input terminal IT1 and the drain of transistor N 2 is connected to the current output terminal OT1.
  • Current mirror CM2 is implemented with PMOS transistors P 5 and P 4 which are connected to the current input terminal IT2, current output terminal OT2 and common terminal CT2 in a fashion similar to the transistors N j and N 2 .
  • the bias circuit operates down to a supply voltage V DD equal to the sum of a threshold voltage Vt of transistor P 2 and a drain-source saturation voltage V DS m of transistor N 2 .
  • V DD a supply voltage
  • Vt threshold voltage
  • V DS m drain-source saturation voltage
  • Transistor P j is a weak transistor, i.e. a transistor with a small width over length ratio (W/L) and small transconductance factor, in saturation.
  • the current of transistor P j is attenuated by the mirror-ratio of current mirror CMl and forced to flow in transistor P 4 by the negative feedback loop consisting of transistors P 2 , N 3 , P 5 and P 4 . Since transistors P 4 and P 5 form a current mirror, the current of transistor N 3 is proportional of that of transistor P j .
  • Transistor N 3 is chosen strong, i.e.
  • the current of transistor P 2 is approximately equal to Vt/R, R being the resistance of resistor RS.
  • the bias voltage V B is therefore equal to the gate-source voltage of transistor P 2 needed for a current of Vt/R through transistor P 2 .
  • the bias current I B supplied by optional transistor P 7 will be proportional to Vt/R.
  • Transistor P 6 acts as a compensation capacitor to stabilize the aforementioned negative feedback loop of transistors P 2 , N 3 , P 5 and P 4 .
  • Transistor P 6 can be replaced with a capacitor connected between the positive supply terminal VP and the bias voltage terminal BVT. In applications where large or many transistors such as transistor P 7 are biased, transistor P 6 can be omitted since sufficient capacitance will then be present.
  • An advantage of compensating in this way, rather than via the Miller-effect of a capacitor between the bias voltage terminal BVT and the gate of transistor N 3 is that high-frequency interference on the positive supply terminal VP is rejected when generating V B .
  • bias circuit By replacing PMOS transistors by NMOS transistors and vice versa a bias circuit is obtained which generates a bias voltage relative to ground.
  • the bias circuit of Figure 2 was designed for fabrication in a 1.2 ⁇ n-well digital CMOS process with a threshold voltage Vt of about 0.9 V for both N and P devices. The design details are given in Table 1. W and L denote the width and length of the transistor.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

CMOS bias circuit capable of operating at supply voltages equal to the sum of a threshold voltage Vt and a saturation voltage. A current proportional to the current of PMOS transistor P1 is forced to flow through a PMOS transistor P4 by means of a negative feedback loop (P2, N3, P5, P4). PMOS transistor P4 forms a current mirror with PMOS transistor P5, so the current of NMOS transistor N3 is proportional to that of PMOS transistor P1. Transistor N3 has a large W/L in order that its gate-source voltage is slightly higher than the threshold voltage Vt. The bias voltage VB is therefore the gate-source voltage of transistor P2 needed for a current of Vt/R, R being the resistance of resistor RS. A change in the supply voltage VDD will change the current through transistor P1 and thus also through transistor N3 and through resistor RS. The change in current through the resistor RS is provided by an increase in the current of transistor P2 owing to the channel-shortening effect in transistor P2. The net result is a bias voltage VB which remains constant with changing supply voltage VDD. A PMOS transistor P3 may be added to provide a slight amount of positive feedback for very low supply voltages to increase the current of transistor N3 and to maintain a constant bias voltage VB.

Description

Low voltage bias circuit for generating supply-independent bias voltages and currents.
The invention relates to bias circuits for generating bias voltages and currents. Such a bias circuit can be used, for example, in mixed-mode CMOS integrated circuits in which analog and digital circuits are integrated on the same semiconductor body.
For future portable systems the circuits have to operate down to supply voltages just exceeding the threshold voltage of the MOS transistors. A key building block needed in such circuits is a bias circuit providing supply-independent bias voltages and currents. In addition, high-frequency supply interference, generally caused by the digital part of the circuit, has to be rejected to enable good-quality performance of the analog part.
Figure 1 shows a threshold-referenced bias circuit known from P.R. Gray and R.G. Meyer, Analysis and design of analog integrated circuits, Second Edition, Wiley, New York, 1984, Figure 4.24a. It is not suitable for low supply voltage however, since it includes two stacked gate-source voltage drops of the transistors PA and NA, and a drain-source saturation voltage of transistor NB. Also this known bias circuit is not well-regulated against supply variations. It is an object of the invention to provide a bias circuit capable of generating supply-independent bias voltages and currents down to a low supply voltage.
According to the invention there is provided a bias circuit comprising: a first supply terminal, a second supply terminal, and a bias voltage terminal; a first current mirror comprising first and second transistors of a first conductivity type, having a current input terminal, a current output terminal coupled to the bias voltage terminal, and a common terminal coupled to the second supply terminal; a second current mirror comprising third and fourth transistors of a second conductivity type opposite to the first conductivity type, having a current input terminal, a current output terminal coupled to the current output terminal of the first current mirror and to the bias voltage terminal, and a common terminal coupled to the first supply terminal; current providing means coupled between the first supply terminal and the current input terminal of the first current mirror for providing a current to the input terminal of the first current mirror; a fifth transistor of the first conductivity type having a gate, a source coupled to the second supply terminal, and a drain coupled to the current input terminal of the second current mirror; resistive means coupled in parallel to the gate and the source of the fifth transistor; and - a sixth transistor of the second conductivity type, having a gate coupled to the bias voltage terminal, a source coupled to the first supply terminal, and a drain coupled to the gate of the fifth transistor.
The bias circuit according to the invention operates down to a supply voltage equal to the sum of the threshold voltage and the saturation voltage. It generates a supply- independent threshold-referenced bias voltage relative to the first supply terminal, similar as the known bias circuit depicted in Figure 1. This bias voltage is equal to the gate-source voltage of the sixth transistor needed for a current having a value equal to the threshold voltage of the fifth transistor divided by the resistance of the resistive means. Changes in the supply voltage cause corresponding changes in the gate-source voltage of the fifth transistor. Therefore the current through the resistive means and the sixth transistor will change proportionally causing a change in the gate-source voltage of the sixth transistor and the bias voltage. This change is counteracted by a change in drain current of the sixth transistor owing to the channel-shortening effect of the sixth transistor. The net result is a bias voltage which is substantially constant with changing supply voltage. The bias circuit may further comprise a seventh transistor of the second conductivity type, having a gate coupled to the bias voltage terminal, a source coupled to the first supply terminal, and a drain coupled to the drain of the fifth transistor. The seventh transistor may be added to provide a slight amount of positive feedback in order to increase the current of the fifth transistor for very low supply voltage and to maintain a constant bias voltage.
These and other aspects of the invention will be elucidated and described with reference to the accompanying drawing in which:
Figure 1 shows a circuit diagram of a conventional bias circuit; and Figure 2 shows a circuit diagram of a bias circuit according to the invention.
In these Figures the same or similar elements have the same reference signs.
Figure 1 shows a conventional bias circuit. A supply voltage VDD is connected between a positive supply terminal VP and a negative supply terminal VN which serves as signal ground. The source of a PMOS transistor PA is connected to the positive supply terminal VP, whereas the interconnected gate and drain of transistor PA are connected to a bias voltage terminal BVT. The bias voltage VB is therefore equal to the gate-source voltage of transistor PA. The current supplied by resistor RB is forced to flow in transistor NA. and, in order for this to occur, the transistor NB must supply enough current into resistor RA so that the gate-source voltage of transistor NA is adapted to the current supplied by resistor RB. The current through transistor PA is equal to the current flowing through resistor RA which is proportional to the gate-source voltage of transistor NA. The bias voltage circuit thus generates a threshold-referenced bias voltage VB relative to the supply voltage VDD- The current through transistor PA is determined by the loop comprising the NMOS transistors NA and NB, and the resistors RA and RB. Scaled copies of the current through transistor PA may be obtained by means of one or more PMOS transistors PB with a source, gate and drain connected to, respectively, the positive supply terminal VP, the bias voltage terminal BVT and an bias current terminal BCT. The lowest possible supply voltage VDD is equal to the sum of the gate-source voltages of the transistors NA and PA and the drain-source saturation voltage of transistor NB. An increasing supply voltage VDD causes an increasing current through transistor NA and an increasing voltage over resistor RA. This in turn causes an increasing current through transistor PA and an increasing bias voltage VB. The bias circuit of Figure 1 is therefore not well-regulated against supply voltage variations. Figure 2 shows a bias circuit according to the invention. The bias circuit comprises a first current mirror CMl having a current input terminal IT1 , a current output terminal OT1 coupled to the bias voltage terminal BVT, and a common terminal coupled to the second supply terminal VN; and a second current mirror CM2 having a current input terminal IT2, a current output terminal coupled to the current output terminal OT1 of the first current mirror CMl and to the bias voltage terminal BVT, and a common terminal CT2 coupled to the first supply terminal VP. The current input terminal IT1 of current mirror CMl is coupled to the drain of a PMOS transistor Pj , the source of which is connected to the positive supply terminal VP and the gate of which is connected to the negative supply terminal VN. The transistor Pj provides a current to the current mirror CMl . The transistor Pj may be replaced by a resistor. The current input terminal IT2 of current mirror CM2 is coupled to the drain of a NMOS transistor N3, the source of which is coupled to the negative supply terminal VN. A resistor RS is connected between the gate and the source of transistor N3.
The bias circuit further comprises a PMOS transistor P2 with a gate coupled to the bias voltage terminal BVT, a source coupled to the first supply terminal VP, and a drain coupled to the gate of transistor N3, an optional PMOS transistor P3 with a gate coupled to the bias voltage terminal BVT, a source coupled to the first supply terminal VP, and a drain coupled to the drain of transistor N3, an optional PMOS transistor P6 with a gate coupled to the bias voltage terminal BVT and a source and drain coupled to the positive supply terminal VP, and one or more optional PMOS transistors P7 with a gate coupled to the bias voltage terminal BVT, a source coupled to the first supply terminal VP, and a drain coupled to the bias current terminal BCT.
The current mirror CMl is implemented with NMOS transistors N, and N2. The sources of transistors Nj and N2 are connected to the common terminal CTl . The gates of the transistors N] and N2 are interconnected and also connected to the drain of transistor N, . The drain of transistor N> is connected to the current input terminal IT1 and the drain of transistor N2 is connected to the current output terminal OT1. Current mirror CM2 is implemented with PMOS transistors P5 and P4 which are connected to the current input terminal IT2, current output terminal OT2 and common terminal CT2 in a fashion similar to the transistors Nj and N2.
As can be seen from Figure 2 the bias circuit operates down to a supply voltage VDD equal to the sum of a threshold voltage Vt of transistor P2 and a drain-source saturation voltage VDS m of transistor N2. However, when minimum supply voltage is of less concern more sophisticated current mirror configurations may be employed, for instance cascoded current mirrors or Wilson current mirrors.
The bias circuit operates as follows. First the transistors P3 and P6 are ignored. Transistor Pj is a weak transistor, i.e. a transistor with a small width over length ratio (W/L) and small transconductance factor, in saturation. The current of transistor Pj is attenuated by the mirror-ratio of current mirror CMl and forced to flow in transistor P4 by the negative feedback loop consisting of transistors P2, N3, P5 and P4. Since transistors P4 and P5 form a current mirror, the current of transistor N3 is proportional of that of transistor Pj . Transistor N3 is chosen strong, i.e. a transistor with a large W/L, in order that its gate-source voltage is slightly higher than the threshold voltage Vt. Therefore the current of transistor P2 is approximately equal to Vt/R, R being the resistance of resistor RS. The bias voltage VB is therefore equal to the gate-source voltage of transistor P2 needed for a current of Vt/R through transistor P2. The bias current IB supplied by optional transistor P7 will be proportional to Vt/R.
The effect of supply-voltage variations is twofold. Suppose the supply voltage VDD increases. First, since the currents of the transistors N3 and Pt are proportional and both transistors are saturated, the gate-source voltage of transistor N3 will increase proportional to the increase in the supply voltage VDD. Therefore the current through resistor RS will also increase proportionally. Second, the source-drain voltage of transistor P2 increases with the supply voltage VDD. Therefore, owing to the channel-shortening effect, its drain current will increase proportional to the increase in the supply voltage VDD By designing the bias circuit such that the increase in current through resistor RS is provided by the increase in the current of transistor P2 owing to channel shortening, it can be achieved that the bias voltage VB will remain constant with changing supply voltage VDD. Transistor P3, which is very weak, may be added to provide a slight amount of positive feedback. This is only relevant for very low supply voltages to increase the current of transistor N3 and thus to maintain a constant value for the bias voltage VB. If transistor P3 is too strong, unwanted hysteresis can result.
Transistor P6 acts as a compensation capacitor to stabilize the aforementioned negative feedback loop of transistors P2, N3, P5 and P4. Transistor P6 can be replaced with a capacitor connected between the positive supply terminal VP and the bias voltage terminal BVT. In applications where large or many transistors such as transistor P7 are biased, transistor P6 can be omitted since sufficient capacitance will then be present. An advantage of compensating in this way, rather than via the Miller-effect of a capacitor between the bias voltage terminal BVT and the gate of transistor N3, is that high-frequency interference on the positive supply terminal VP is rejected when generating VB.
By replacing PMOS transistors by NMOS transistors and vice versa a bias circuit is obtained which generates a bias voltage relative to ground. The bias circuit of Figure 2 was designed for fabrication in a 1.2 μ n-well digital CMOS process with a threshold voltage Vt of about 0.9 V for both N and P devices. The design details are given in Table 1. W and L denote the width and length of the transistor. Resistor RS was a n-well resistor with resistance R = 80 kΩ.
The measured bias voltage VB was 1.123 V, varying by 9 mV from VDD = 1.130 V to VDD = 5 V. Regulation is maintained down to a supply voltage only 7 mV higher than the bias voltage VB and 220 mV higher than the threshold voltage Vt. This performance is the result of the conductance cancelling through the channel-shortening effect in transistor P2 and the positive feedback provided by transistor P3.

Claims

CLAIMS:
1. A bias circuit comprising: a first supply terminal (VP), a second supply terminal (VN), and a bias voltage terminal (BVT); a first current mirror (CMl) comprising first (Ni) and second (N^ transistors of a first conductivity type, having a current input terminal (ITl), a current output terminal (OTl) coupled to the bias voltage terminal (BVT), and a common terminal (CTl) coupled to the second supply terminal (VN); a second current mirror (CM2) comprising third (P4) and fourth (P5) transistors of a second conductivity type opposite to the first conductivity type, having a current input terminal (IT2), a current output terminal (OT2) coupled to the current output terminal (OTl) of the first current mirror (CM l) and to the bias voltage terminal (BVT), and a common terminal (CT2) coupled to the first supply terminal (VP); current providing means (P,) coupled between the first supply terminal (VP) and the current input terminal (ITl) of the first current mirror (CM l) for providing a current to the input terminal (ITl) of the first current mirror (CMl); a fifth transistor (N3) of the first conductivity type having a gate, a source coupled to the second supply terminal (VN), and a drain coupled to the current input terminal (IT2) of the second current mirror (CM2); resistive means (RS) coupled in parallel to the gate and the source of the fifth transistor (N3); and a sixth transistor (P2) of the second conductivity type, having a gate coupled to the bias voltage terminal (BVT), a source coupled to the first supply terminal (VP), and a drain coupled to the gate of the fifth transistor (N3).
2. A bias circuit as claimed in claim 1 , further comprising a seventh transistor (P3) of the second conductivity type, having a gate coupled to the bias voltage terminal (BVT), a source coupled to the first supply terminal (VP), and a drain coupled to the drain of the fifth transistor (N3).
3. A bias circuit a s claimed in claim 1 or 2, further comprising capacitive means (P6) coupled between the first supply terminal (VP) and the bias voltage terminal (BVT).
4. A bias circuit as claimed in claim 3, wherein the capacitive means comprises an eighth transistor (P6) of the second conductivity type, having a gate coupled to the bias voltage terminal (BVT), and having source and drain connected to the first supply terminal
(VP).
5. A bias circuit as claimed in claim 1 , 2, 3 or 4, further comprising a ninth transistor (P7) of the second conductivity type, having a gate, a source and a drain coupled to, respectively, the bias voltage terminal (BVT), the first supply terminal (VP) and a bias current terminal (BCT).
6. A bias circuit as claimed in claim 1, 2, 3, 4 or 5, wherein the current providing means comprises a tenth transistor (P,) of the second conductivity type having a gate, a source and a drain coupled to, respectively, the second supply terminal (VN), the first supply terminal (VP) and the current input terminal (ITl) of the first current mirror (CMl).
7. A bias circuit as claimed in claim 1 , 2, 3, 4, 5 or 6, wherein respective sources of the first (N,) and second (N2) transistors are coupled to the common terminal (CTl) of the first current mirror (CMl), respective gates of the first (Nj) and second (N2) transistors are coupled to a drain of the first transistor (N^, the drain of the first transistor (N .) is coupled to the current input terminal (ITl) of the first current mirror (CM l), and a drain of the second transistor (N2) is coupled to the current output terminal (OTl) of the first current mirror (OTl).
8. A bias circuit as claimed in claim 1 , 2, 3, 4, 5, 6 or 7, wherein respective sources of the third (P4) and fourth (P5) transistors are coupled to the common terminal (CT2) of the second current mirror (CM2), respective gates of the third (P4) and fourth (P5) transistors are coupled to a drain of the fourth transistor (P5), the drain of the fourth transistor (P5) is coupled to the current input terminal (IT2) of the second current mirror CM2), and a drain of the third transistor (P4) is coupled to the current output terminal (OT2) of the second current mirror (CM2).
EP97919572A 1996-05-22 1997-05-07 Low voltage bias circuit for generating supply-independent bias voltages and currents Expired - Lifetime EP0910820B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP96201415 1996-05-22
PCT/IB1997/000507 WO1997044721A1 (en) 1996-05-22 1997-05-07 Low voltage bias circuit for generating supply-independent bias voltages and currents

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EP0910820A1 true EP0910820A1 (en) 1999-04-28
EP0910820B1 EP0910820B1 (en) 2001-10-17

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US (1) US5825236A (en)
EP (1) EP0910820B1 (en)
JP (1) JPH11511280A (en)
WO (1) WO1997044721A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046944A (en) * 1998-01-28 2000-04-04 Sun Microsystems, Inc. Bias generator circuit for low voltage applications
US6043702A (en) * 1998-01-29 2000-03-28 Sun Microsystems, Inc. Dynamic biasing for overshoot and undershoot protection circuits
DE69830469D1 (en) * 1998-03-16 2005-07-14 St Microelectronics Srl Polarization voltage control circuit for floating sink in a semiconductor integrated circuit
US6326836B1 (en) * 1999-09-29 2001-12-04 Agilent Technologies, Inc. Isolated reference bias generator with reduced error due to parasitics
FR2825806B1 (en) * 2001-06-08 2003-09-12 St Microelectronics Sa POLARIZATION CIRCUIT WITH VOLTAGE AND TEMPERATURE STABLE OPERATING POINT
US7071770B2 (en) * 2004-05-07 2006-07-04 Micron Technology, Inc. Low supply voltage bias circuit, semiconductor device, wafer and system including same, and method of generating a bias reference
US7161430B1 (en) * 2004-10-04 2007-01-09 National Semiconductor Corporation Low voltage folded metal oxide semiconductor field effect transistor (MOSFET) amplifier circuit
US7132887B1 (en) * 2004-10-04 2006-11-07 National Semiconductor Corporation Low voltage semi-folded metal oxide semiconductor field effect transistor (MOSFET) amplifier circuit
US7459961B2 (en) * 2006-10-31 2008-12-02 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Voltage supply insensitive bias circuits
TWI654510B (en) 2017-03-24 2019-03-21 立積電子股份有限公司 Bias circuit
CN111818690B (en) * 2020-07-06 2023-06-06 天津中科新显科技有限公司 High-precision current scaling circuit and scaling method applied to display driving

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4618816A (en) * 1985-08-22 1986-10-21 National Semiconductor Corporation CMOS ΔVBE bias current generator
NL9001017A (en) * 1990-04-27 1991-11-18 Philips Nv BUFFER SWITCH.
JP2978226B2 (en) * 1990-09-26 1999-11-15 三菱電機株式会社 Semiconductor integrated circuit
US5124632A (en) * 1991-07-01 1992-06-23 Motorola, Inc. Low-voltage precision current generator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9744721A1 *

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WO1997044721A1 (en) 1997-11-27
JPH11511280A (en) 1999-09-28
EP0910820B1 (en) 2001-10-17
US5825236A (en) 1998-10-20

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