EP0908946B1 - Improved gapfill of semiconductor structures using doped silicate glass - Google Patents
Improved gapfill of semiconductor structures using doped silicate glass Download PDFInfo
- Publication number
- EP0908946B1 EP0908946B1 EP98118244A EP98118244A EP0908946B1 EP 0908946 B1 EP0908946 B1 EP 0908946B1 EP 98118244 A EP98118244 A EP 98118244A EP 98118244 A EP98118244 A EP 98118244A EP 0908946 B1 EP0908946 B1 EP 0908946B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- silicate glass
- doped silicate
- layer
- dopant concentration
- concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000005368 silicate glass Substances 0.000 title claims description 65
- 239000004065 semiconductor Substances 0.000 title description 2
- 239000002019 doping agent Substances 0.000 claims description 59
- 239000013078 crystal Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 12
- 230000007423 decrease Effects 0.000 claims description 9
- 230000008018 melting Effects 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 description 23
- 235000012431 wafers Nutrition 0.000 description 22
- 239000005380 borophosphosilicate glass Substances 0.000 description 19
- 238000006243 chemical reaction Methods 0.000 description 18
- 238000000151 deposition Methods 0.000 description 14
- 230000008021 deposition Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000011065 in-situ storage Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000005247 gettering Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- AJSTXXYNEIHPMD-UHFFFAOYSA-N triethyl borate Chemical compound CCOB(OCC)OCC AJSTXXYNEIHPMD-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000013022 venting Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
Definitions
- the invention relates to device fabrication.
- insulating, semiconducting, and conducting layers are formed on a substrate.
- the layers are patterned to create features and spaces, forming devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, producing an integrated circuit (IC).
- IC integrated circuit
- Doped silicate glass is used as, for example, an insulating layer between conductive or semiconductive layers in the manufacture of ICs.
- doped silicate glass such as borophosphosilicate glass (BPSG) is attractive due to its ability to reflow when annealed at a sufficiently high temperature.
- BPSG borophosphosilicate glass
- doped silicate glass can be used to fill gaps relatively small gaps without voids.
- the term "gap" refers to any generic nonplanar feature on a given surface and may include such features as trenches or spaces between gates of transistors.
- doped silicate glass such as BPSG is formed by various chemical vapor deposition (CVD) techniques.
- the BPSG is deposited at a relatively low temperature of about 400°C.
- the substrate is heated to a high enough temperature to cause the glass to soften.
- annealing BPSG having B and P concentrations of about 4 wt% each at a temperature of 800 °C for about 30 minutes can fill structures as narrow as 0.25 ⁇ m with aspect ratios of up to 3:1 without voids.
- the dopant concentration of the B in the BPSG affects its reflow or melting temperature.
- increasing the B concentration improves the glass ability to fill gaps at a given temperature.
- the upper limit of dopant concentration is about 11 wt% (all percentages are wt%). Of course, this limit may vary depending on the type of doped silicate glass and deposition conditions.
- the doped silicate glass is required to fill narrower structures with higher aspect ratios. Due to the inherent upper limit in the dopant concentration of the doped silicate glass, a higher temperature anneal of longer duration is required in order to satisfy the needs of advanced IC designs. However, such an anneal typically exceeds the allowable thermal budget, resulting in a non-existing manufacturable process window.
- the invention relates to improved gap fill of narrow spaces in the fabrication of integrated circuits. Improved gap fill is achieved by providing a doped silicate glass having a dopant concentration gradient which is higher in the bottom than at the top. This allows the doped silicate glass to have a very high dopant concentration at the bottom where gap fill is important and a lower concentration at the top where gap fill is not an issue. As such, the overall concentration of the doped silicate glass is lower than that which causes surface crystal growth while achieving better gap fill than conventional doped silicate glass layers.
- the invention relates to doped silicate glass as used in, for example, an insulating layer in IC fabrication.
- a cross-section of a portion of an IC structure formed on a substrate 101 is shown.
- the IC structure which is not shown in detail, is, for example, a portion of a memory IC including a random access memory (RAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), or a read only memory (ROMs).
- the IC structure may be a logic IC such as a programmable logic array (PLA), an application specific IC (ASIC), a merged DRAM-logic IC (embedded DRAM), or any other logic circuit.
- PDA programmable logic array
- ASIC application specific IC
- merged DRAM-logic IC embedded DRAM
- ICs are fabricated on a semiconductor substrate, such as a silicon wafer, in parallel. After processing, the wafer is diced in order to separate the ICs into a plurality of individual chips. The chips are then packaged into final products for use in, for example, consumer products such as computer systems, cellular phones, personal digital assistants (PDAs), and other electronic products.
- a semiconductor substrate such as a silicon wafer
- PDAs personal digital assistants
- the substrate 201 is, for example, a silicon wafer. Other substrates such as silicon on insulator (SOI), silicon on sapphire (SOS), germanium, gallium arsenide, and group III-V compounds, are also useful. The major surface of the substrate is not critical and any suitable orientation such as a (100), (110), or (111) is useful.
- the substrate for example, includes a plurality of devices such as trench capacitors (not shown) formed therein. Such trench capacitors serve as storage capacitors for DRAM cells. Formation of the trench capacitors is achieved using conventional techniques.
- device features 120 are provided on the surface of the substrate.
- the device structures for example, are gates of transistors.
- the transistors represent wordlines that connect a plurality of memory cells in a memory array.
- the gates include a gate oxide layer, a doped poly layer, and a cap nitride layer.
- the poly layer may comprise a polycide layer that includes a layer of silicide over a doped poly layer.
- a nitride liner is provided over the device structures, serving as an etch stop for borderless contact formation.
- the device structures are separated by gaps 125, creating an uneven surface topology on the substrate surface.
- the aspect ratio of the gaps is defined by the height H of the device structures over the width W of the space separating them.
- a technique for forming a doped silicate glass layer over uneven surface topography is provided.
- the invention enables the formation of doped silicate glass that fills small gaps having relatively high aspect ratios without voids as well as the formation of surface crystals with a reduced thermal budget, resulting in a larger manufacturable process window.
- the doped silicate glass has a predetermined thickness.
- the predetermined thickness depends on the specific application. For example, when used as an interlevel dielectric layer, the thickness of the doped silicate glass is sufficient to provide isolation between the device structures and the overlying conductive layer.
- the deposited thickness should also take into account the planarization and any other processes that erode the thickness of the layer.
- the thickness of the doped silicate glass is about 0.75 to 1.2 ⁇ m.
- the actual thickness may be optimized for different GRs and applications.
- a doped silicate glass layer 230 is formed in accordance with the invention.
- the doped silicate glass in one embodiment comprises B.
- B dopants are desirable as they lower the melting point of the silicate glass.
- Other dopants such as germanium (Ge), which lower the melting temperature of the doped silicate glass are also useful.
- the doped silicate glass can include other dopants.
- P may be added to improve gettering.
- the doped silicate glass comprises a dopant concentration gradient, wherein the dopant concentration is greatest at the bottom and decreases toward the top of the layer.
- the dopant concentration of the doped silicate glass can be varied over a wide range from bottom to top.
- the dopant concentration at the bottom of the doped silicate glass comprises a dopant concentration greater than an amount that causes surface crystal growth.
- the dopant concentration is decreased, providing a layer having an overall concentration below an amount that causes surface crystal growth. As we move toward the top of the layer, the dopant concentration is decreased.
- the lower portion By depositing a layer with a concentration gradient which decreases toward the surface, the lower portion can comprise a significantly higher dopant concentration, enabling the filling of much smaller gaps having high aspect ratios while the overall concentration of the glass is maintained below that which causes surface crystal growth. As a result, a reliable doped silicate glass layer with much higher gapfill characteristics over conventional doped silicate glass is provided.
- a top surface 243 of the doped silicate glass is non-planar.
- the doped silicate glass is planarized by, for example, chemical mechanical polish (CMP).
- CMP chemical mechanical polish
- the CMP removes a portion of the doped silicate glass layer in order to provide a planar top surface depicted by dotted line 245.
- a doped silicate glass with a planar top surface having a predetermined thickness T is provided.
- the actual thickness T is determined by design parameters such as functionality of the layer as an insulator.
- the doped silicate glass can be deposited by various deposition techniques, one of which may be chemical vapor deposition (CVD).
- the doped silicate glass is deposited at a temperature sufficient to cause reflow.
- in situ reflow of the doped silicate glass occurs during deposition.
- In situ reflow in combination with the high dopant concentration at the lower portions of the doped silicate glass achieves excellent gap fill behavior with a lower thermal budget.
- a doped silicate glass having a gradient dopant concentration in accordance with the invention is shown.
- the doped silicate glass is deposited by various CVD techniques.
- doped silicate glass comprises BPSG.
- the doped silicate glass is deposited by low pressure CVD (LPCVD).
- the deposition temperature range is from about 720 to 870°C, preferably 750 to 850°C. Such a temperature range is sufficient to cause in situ reflow of the doped silicate glass during deposition.
- the doped silicate glass includes a plurality of sub-layers.
- the doped silicate glass is shown to include five sub-layers 331-335. The interfaces between adjacent sub-layers are shown for purposes of illustration. The actual doped silicate glass layer may not have such defined interfaces.
- a first sub-layer 331 is formed over the surface of the IC structure.
- the total dopant concentration of the bottom of the layer is greater than an amount which causes surface crystal growth. With each subsequent sub-layer, the total dopant concentration therein decreases such that the overall dopant concentration of the sub-layers is below an amount which causes surface crystal growth.
- the total concentration of the dopants in the first sub-layer is about 20 wt%.
- the P dopants in the BPSG layer is used for gettering.
- the concentration of P is, for example, about 2-6 wt%.
- the P concentration can vary depending on design parameters.
- by increasing the total dopant concentration of the first BPSG sub-layer it can include a correspondingly greater amount of B dopants to lower its melting point.
- the B concentration of the B layer can be increased to 14-19 wt%.
- the dopant concentration incrementally decreases for subsequent sub-layers, producing a decreasing gradient from bottom to top.
- the total dopant concentration of the top sub-layer 335 is about 0 wt%.
- the total dopant concentration gradient of the doped silicate glass layer is from about 15-0 wt% from bottom to, with an overall dopant concentration of the layer of less than that which causes surface crystal growth.
- Providing a high dopant concentration in the sub-layer 331 lowers the reflow temperature. As a result, depositing the sub-layer 331 at the high temperature range produces a material with low viscosity that exhibits excellent gap fill characteristics. The in situ reflow facilitates the flowing of the doped silicate glass material to the bottom of the high aspect ratio gap 325. As a result, the aspect ratio of the gap decreased.
- the second sub-layer is deposited with a dopant concentration lower than that of the first sub-layer. This is typically achieved by lowering the amount of dopant source material available for the deposition. Due to the decrease in aspect ratio of the gap as a result of the first sub-layer, the gap becomes easier to fill. As such, the lower dopant concentration in the second sub-layer is sufficient to provide filling of the gap 335. Again, the in situ reflow facilitates the flowing of the material to the bottom, further reducing the aspect ratio of the gap.
- the aspect ratio of the gap is decreased with each subsequent sub-layer deposition, making it easier to fill.
- the deposition continues until the doped silicate glass reaches a desired thickness. Thereafter, a CMP planarizes the surface, resulting in a planar doped silicate glass layer having a predefined thickness.
- the sub-layers are relatively equal in thickness, it is not critical to the invention.
- a doped silicate glass with a gradient dopant concentration, high aspect ratio structures are easily filled with lower thermal budget.
- the doped silicate glass comprises BSG.
- Doped silicate glass comprising dopants, such as Ge or other dopants that reduces the melting point of the material is also useful. Other dopants which serve other purposes, such as gettering, can also be included in the doped silicate glass. What is important is that the doped silicate glass comprises a dopant concentration exceeding a concentration that causes formation of crystals in the bottom portion of the layer. Furthermore, the doped silicate glass also comprises a lower dopant concentration in the upper portion that produces a layer with overall dopant concentration that is below a concentration which causes surface crystal formation.
- the doped silicate glass layers are formed using a low pressure chemical vapor deposition (LPCVD) process.
- LPCVD low pressure chemical vapor deposition
- Other CVD processes are also useful.
- Fig. 4a a simplified top view of a CVD reactor 310 is shown.
- the reactor is, for example, a DSM TM 9800 that is manufactured by Lam Research Corporation of Fremont.
- the Lam Integrity DSM 9800 is described in US Patent 4,976, 996. It should be noted that the CVD reactor shown is merely illustrative.
- reactor 310 comprises wafer cassette storage bays 330 and 335, loadlock units 340 and 345, transfer chamber 350, and reaction chamber 360.
- the cassette storage bays store a cassette, such as those used for holding and storing a plurality of wafers in conventional device fabrication.
- the wafers in the cassettes are transferred to the respective load lock units by wafer transfer arms.
- the transfer chamber 350 includes a wafer loading arm 351.
- the wafer loading arm removes a wafer from either loadlock 340 or loadlock 345 and places it in a wafer slot of a rotating platen in the reaction chamber.
- the platen comprises a plurality of wafer slots. Wafers are loaded into the other slots by rotating the platen to the appropriate position.
- Fig. 4b shows the reaction chamber in greater detail.
- the reaction chamber comprises platen.
- the platen rotates around a hub 302 (the direction of rotation of platen 380 is arbitrary).
- the platen includes a plurality of slots for placement of a wafer therein. Typically, the slots are depressed such that the top surface of the wafer, when placed therein, is substantially planar with the surface of the platen.
- a plurality of injectors is located at the circumference of the reaction chamber.
- Feed lines 370 connected to the injectors provide materials from a supply source for the reaction. The number of feed lines depends on the number of different types of materials used for forming the layer. The materials are mixed and delivered into the reaction area of the chamber by the injectors.
- An exhaust port 385 passes excess materials and by-products of the reaction out of the reaction chamber.
- the exhaust port is formed by, for example, an interior passageway through hub 302 for venting gases from the reactor chamber.
- the direction of the flow of the chemistry is from injectors toward the center.
- reversing the direction of chemistry flow is also useful. Reversing the flow is achieved by locating the injectors at the center of the chamber and the exhaust vents at the circumference of the chamber.
- the reactor is essentially isothermal.
- heaters (not shown for ease of illustration), which may be resistive, are strategically located throughout the reactor chamber to compensate for any heat loss. In this manner, a constant temperature may be maintained during the deposition process.
- An outer heater surrounding the reactor chamber compensates for the heat loss to the outside world.
- a resistive middle heater which radiates heat to the entire chamber to maintain a suitable wafer temperature during deposition.
- an illustrative reaction chamber is provided with twelve injectors (depicted by arrows). Providing the reaction chamber with a fewer or a greater number of injectors is also useful.
- the injectors are equally spaced apart at the periphery of the reaction chamber. Each injector therefore defines a 30° injection area in the reactor chamber, as delineated by the dotted lines. In other words, each injector injects into a different sector of the reactor.
- Such an injection scheme is referred to as a segmented delivery system.
- source materials for the silicate glass which typically are in gaseous form, are injected into the reaction chamber via the injectors.
- the source material flows from the injectors toward the center of the reaction chamber.
- the platen supporting the wafers is rotated, moving the wafers through the injected source materials.
- the source materials contact the wafer surfaces, they chemically react to deposit doped silicate glass thereon. Excess source materials and their by-products are exhausted through exhaust port.
- source materials for the silicate glass which typically are in gaseous form, are injected into the reaction chamber via the injectors.
- the source material flows from the injectors toward the center of the reaction chamber.
- the platen supporting the wafers is rotated, moving the wafers through the injected source materials.
- the source materials contact the wafer surfaces, they chemically react to deposit doped silicate glass thereon. Excess source materials and their by-products are exhausted through exhaust port.
- source materials that make up BPSG are injected into the reaction chamber.
- two source materials or chemistries are injected to form BPSG.
- the first chemistry comprises, for example, TEB/TEOS/O 2 /N 2 .
- the TEOS tetraethoxysilane
- TEB triethyl borate
- B boron
- O 2 and N 2 are carrier gases.
- the second source material comprises a phosphine chemistry such as PH 3 /O 2 /N 2 .
- PH 3 (phosphine) provides the source of phosphorus (P) dopant atoms, and O 2 and N 2 are oxidation and carrier gases.
- Other chemistries used in forming BPSG are also useful.
- the two chemistries are, for example, flowed into the reaction chamber via alternating injectors.
- the formation of the BPSG layer is achieved using conventional process conditions, such as those described in Tedder et al., Appl. Phys. Lett. 62, p. 699 (1993).
- the dopant concentration varies over the deposition of the BPSG layer.
- the concentration of the dopants in the bottom is greater than an amount which causes surface crystal growth.
- the concentration for example, is about 20 wt%.
- the concentration of dopants is about 15 wt% at the bottom.
- P dopants are provided for gettering purposes.
- the P concentration is about 2-6 wt%.
- the concentration of B, which lowers the melting point of the BPSG is about 14-18 wt%.
- the actual concentration depends on the design requirement. Since the concentration of the dopant that lowers the melting point of the BPSG is relatively high, reflow is enhanced. This enables the lower portion of the BPSG to fill smaller gaps having a higher aspect ratio than, for example, 4:1.
- the concentration of dopants in the upper portion of the layer is less than the bottom portion so as to provide a BPSG layer having an overall dopant concentration below that which causes surface crystal growth.
- the layer can comprise a dopant concentration gradient that is about 20 wt%, preferably 15wt%, and decreases toward the top to provide a layer having an overall dopant concentration less than that which causes surface crystal growth.
- the concentration at the upper portion is about 0 wt%.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
- Chemical Vapour Deposition (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Led Devices (AREA)
Description
- The invention relates to device fabrication. In device fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces, forming devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, producing an integrated circuit (IC).
- Doped silicate glass is used as, for example, an insulating layer between conductive or semiconductive layers in the manufacture of ICs. In particular, the use of doped silicate glass such as borophosphosilicate glass (BPSG) is attractive due to its ability to reflow when annealed at a sufficiently high temperature. As such, doped silicate glass can be used to fill gaps relatively small gaps without voids. As the term is used herein, the term "gap" refers to any generic nonplanar feature on a given surface and may include such features as trenches or spaces between gates of transistors.
- Conventionally, doped silicate glass such as BPSG is formed by various chemical vapor deposition (CVD) techniques. The BPSG is deposited at a relatively low temperature of about 400°C. After deposition, the substrate is heated to a high enough temperature to cause the glass to soften. For example, annealing BPSG having B and P concentrations of about 4 wt% each at a temperature of 800 °C for about 30 minutes can fill structures as narrow as 0.25 µm with aspect ratios of up to 3:1 without voids.
- The dopant concentration of the B in the BPSG affects its reflow or melting temperature. The higher the B concentration, the lower the reflow temperature and vice-versa. Thus, increasing the B concentration improves the glass ability to fill gaps at a given temperature. Generally, it is desirable to have as high a B concentration to enable filling of small gaps with a lower thermal budget. However, if the total dopant concentration of the BPSG or doped silicate glass exceeds an upper limit, the dopants tend to precipitate and form acid crystals on the surface. Such surface crystals adversely affect the reliability and characteristics of subsequently formed layers. Typically, the upper limit of dopant concentration is about 11 wt% (all percentages are wt%). Of course, this limit may vary depending on the type of doped silicate glass and deposition conditions.
- As dimensions continue to decrease in advance IC designs, the doped silicate glass is required to fill narrower structures with higher aspect ratios. Due to the inherent upper limit in the dopant concentration of the doped silicate glass, a higher temperature anneal of longer duration is required in order to satisfy the needs of advanced IC designs. However, such an anneal typically exceeds the allowable thermal budget, resulting in a non-existing manufacturable process window.
- As shown from the above discussion, it is desirable to provide filling of narrow structures with high aspect ratios having a manufacturable process window.
- The invention relates to improved gap fill of narrow spaces in the fabrication of integrated circuits. Improved gap fill is achieved by providing a doped silicate glass having a dopant concentration gradient which is higher in the bottom than at the top. This allows the doped silicate glass to have a very high dopant concentration at the bottom where gap fill is important and a lower concentration at the top where gap fill is not an issue. As such, the overall concentration of the doped silicate glass is lower than that which causes surface crystal growth while achieving better gap fill than conventional doped silicate glass layers.
-
- Fig. 1 shows a cross-section of an integrated circuit with device features separated by narrow spaces;
- Fig. 2 shows a device layer in accordance with one embodiment that provides improved gap fill of the narrow spaces;
- Fig. 3 shows the device layer with improved gap fill in greater detail; and
- Figs. 4a-b show a CVD reactor for forming the device layer with improved gap fill characteristics.
- The invention relates to doped silicate glass as used in, for example, an insulating layer in IC fabrication. Referring to Fig. 1, a cross-section of a portion of an IC structure formed on a substrate 101 is shown. The IC structure, which is not shown in detail, is, for example, a portion of a memory IC including a random access memory (RAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), or a read only memory (ROMs). Alternatively, the IC structure may be a logic IC such as a programmable logic array (PLA), an application specific IC (ASIC), a merged DRAM-logic IC (embedded DRAM), or any other logic circuit.
- Typically, numerous ICs are fabricated on a semiconductor substrate, such as a silicon wafer, in parallel. After processing, the wafer is diced in order to separate the ICs into a plurality of individual chips. The chips are then packaged into final products for use in, for example, consumer products such as computer systems, cellular phones, personal digital assistants (PDAs), and other electronic products.
- The
substrate 201 is, for example, a silicon wafer. Other substrates such as silicon on insulator (SOI), silicon on sapphire (SOS), germanium, gallium arsenide, and group III-V compounds, are also useful. The major surface of the substrate is not critical and any suitable orientation such as a (100), (110), or (111) is useful. The substrate, for example, includes a plurality of devices such as trench capacitors (not shown) formed therein. Such trench capacitors serve as storage capacitors for DRAM cells. Formation of the trench capacitors is achieved using conventional techniques. - As shown,
device features 120 are provided on the surface of the substrate. The device structures, for example, are gates of transistors. In one embodiment, the transistors represent wordlines that connect a plurality of memory cells in a memory array. - Typically, the gates include a gate oxide layer, a doped poly layer, and a cap nitride layer. In some embodiments, the poly layer may comprise a polycide layer that includes a layer of silicide over a doped poly layer. A nitride liner is provided over the device structures, serving as an etch stop for borderless contact formation.
- The device structures are separated by
gaps 125, creating an uneven surface topology on the substrate surface. The aspect ratio of the gaps is defined by the height H of the device structures over the width W of the space separating them. - In accordance with the invention, a technique for forming a doped silicate glass layer over uneven surface topography is provided. The invention enables the formation of doped silicate glass that fills small gaps having relatively high aspect ratios without voids as well as the formation of surface crystals with a reduced thermal budget, resulting in a larger manufacturable process window.
- The doped silicate glass has a predetermined thickness. The predetermined thickness, of course, depends on the specific application. For example, when used as an interlevel dielectric layer, the thickness of the doped silicate glass is sufficient to provide isolation between the device structures and the overlying conductive layer. The deposited thickness should also take into account the planarization and any other processes that erode the thickness of the layer. Typically, for a 256 Megabit DRAM employing 0.25 µm groundrule (GR), the thickness of the doped silicate glass is about 0.75 to 1.2 µm. Of course, the actual thickness may be optimized for different GRs and applications.
- Referring to Fig. 2, a doped
silicate glass layer 230 is formed in accordance with the invention. The doped silicate glass in one embodiment comprises B. B dopants are desirable as they lower the melting point of the silicate glass. Other dopants, such as germanium (Ge), which lower the melting temperature of the doped silicate glass are also useful. In addition, the doped silicate glass can include other dopants. For example, P may be added to improve gettering. In accordance with the invention, the doped silicate glass comprises a dopant concentration gradient, wherein the dopant concentration is greatest at the bottom and decreases toward the top of the layer. - The dopant concentration of the doped silicate glass can be varied over a wide range from bottom to top. In one embodiment, the dopant concentration at the bottom of the doped silicate glass comprises a dopant concentration greater than an amount that causes surface crystal growth. In the upper portion, the dopant concentration is decreased, providing a layer having an overall concentration below an amount that causes surface crystal growth. As we move toward the top of the layer, the dopant concentration is decreased.
- By depositing a layer with a concentration gradient which decreases toward the surface, the lower portion can comprise a significantly higher dopant concentration, enabling the filling of much smaller gaps having high aspect ratios while the overall concentration of the glass is maintained below that which causes surface crystal growth. As a result, a reliable doped silicate glass layer with much higher gapfill characteristics over conventional doped silicate glass is provided.
- As shown, a
top surface 243 of the doped silicate glass is non-planar. After deposition is completed, the doped silicate glass is planarized by, for example, chemical mechanical polish (CMP). The CMP removes a portion of the doped silicate glass layer in order to provide a planar top surface depicted bydotted line 245. As a result, a doped silicate glass with a planar top surface having a predetermined thickness T is provided. As discussed, the actual thickness T is determined by design parameters such as functionality of the layer as an insulator. The doped silicate glass can be deposited by various deposition techniques, one of which may be chemical vapor deposition (CVD). In one embodiment, the doped silicate glass is deposited at a temperature sufficient to cause reflow. As such, in situ reflow of the doped silicate glass occurs during deposition. In situ reflow in combination with the high dopant concentration at the lower portions of the doped silicate glass achieves excellent gap fill behavior with a lower thermal budget. - Referring to Fig. 3, a doped silicate glass having a gradient dopant concentration in accordance with the invention is shown. The doped silicate glass is deposited by various CVD techniques. In one embodiment, doped silicate glass comprises BPSG. The doped silicate glass is deposited by low pressure CVD (LPCVD). The deposition temperature range is from about 720 to 870°C, preferably 750 to 850°C. Such a temperature range is sufficient to cause in situ reflow of the doped silicate glass during deposition.
- Illustratively, the doped silicate glass includes a plurality of sub-layers. In the illustrative embodiment, the doped silicate glass is shown to include five sub-layers 331-335. The interfaces between adjacent sub-layers are shown for purposes of illustration. The actual doped silicate glass layer may not have such defined interfaces.
- As shown, a
first sub-layer 331 is formed over the surface of the IC structure. In one embodiment, the total dopant concentration of the bottom of the layer is greater than an amount which causes surface crystal growth. With each subsequent sub-layer, the total dopant concentration therein decreases such that the overall dopant concentration of the sub-layers is below an amount which causes surface crystal growth. - In one embodiment, the total concentration of the dopants in the first sub-layer is about 20 wt%. The P dopants in the BPSG layer is used for gettering. Typically, the concentration of P is, for example, about 2-6 wt%. Of course, the P concentration can vary depending on design parameters. However, by increasing the total dopant concentration of the first BPSG sub-layer, it can include a correspondingly greater amount of B dopants to lower its melting point. For example, with a P concentration of 2-6 wt%, the B concentration of the B layer can be increased to 14-19 wt%. The dopant concentration incrementally decreases for subsequent sub-layers, producing a decreasing gradient from bottom to top. In one embodiment, the total dopant concentration of the
top sub-layer 335 is about 0 wt%. Preferably, the total dopant concentration gradient of the doped silicate glass layer is from about 15-0 wt% from bottom to, with an overall dopant concentration of the layer of less than that which causes surface crystal growth. - Providing a high dopant concentration in the sub-layer 331 lowers the reflow temperature. As a result, depositing the sub-layer 331 at the high temperature range produces a material with low viscosity that exhibits excellent gap fill characteristics. The in situ reflow facilitates the flowing of the doped silicate glass material to the bottom of the high
aspect ratio gap 325. As a result, the aspect ratio of the gap decreased. - The second sub-layer is deposited with a dopant concentration lower than that of the first sub-layer. This is typically achieved by lowering the amount of dopant source material available for the deposition. Due to the decrease in aspect ratio of the gap as a result of the first sub-layer, the gap becomes easier to fill. As such, the lower dopant concentration in the second sub-layer is sufficient to provide filling of the
gap 335. Again, the in situ reflow facilitates the flowing of the material to the bottom, further reducing the aspect ratio of the gap. - The aspect ratio of the gap is decreased with each subsequent sub-layer deposition, making it easier to fill. The deposition continues until the doped silicate glass reaches a desired thickness. Thereafter, a CMP planarizes the surface, resulting in a planar doped silicate glass layer having a predefined thickness.
- Although the sub-layers, as shown, are relatively equal in thickness, it is not critical to the invention. By providing a doped silicate glass with a gradient dopant concentration, high aspect ratio structures are easily filled with lower thermal budget.
- Alternatively, the doped silicate glass comprises BSG. Doped silicate glass comprising dopants, such as Ge or other dopants that reduces the melting point of the material is also useful. Other dopants which serve other purposes, such as gettering, can also be included in the doped silicate glass. What is important is that the doped silicate glass comprises a dopant concentration exceeding a concentration that causes formation of crystals in the bottom portion of the layer.
Furthermore, the doped silicate glass also comprises a lower dopant concentration in the upper portion that produces a layer with overall dopant concentration that is below a concentration which causes surface crystal formation. This enables a higher dopant concentration of dopants that decreases the melting point of the material where it is needed to fill narrow gaps while maintaining the overall concentration of the doped silicate glass to that which causes formation of surface crystals. The higher dopant concentration results in better gap fill. - In one embodiment, the doped silicate glass layers are formed using a low pressure chemical vapor deposition (LPCVD) process. Other CVD processes are also useful Referring to Fig. 4a, a simplified top view of a
CVD reactor 310 is shown. The reactor is, for example, a DSM™ 9800 that is manufactured by Lam Research Corporation of Fremont. The Lam Integrity DSM 9800 is described in US Patent 4,976, 996. It should be noted that the CVD reactor shown is merely illustrative. - As shown,
reactor 310 comprises wafercassette storage bays loadlock units transfer chamber 350, andreaction chamber 360. The cassette storage bays store a cassette, such as those used for holding and storing a plurality of wafers in conventional device fabrication. The wafers in the cassettes are transferred to the respective load lock units by wafer transfer arms. Thetransfer chamber 350 includes awafer loading arm 351. The wafer loading arm removes a wafer from eitherloadlock 340 or loadlock 345 and places it in a wafer slot of a rotating platen in the reaction chamber. Illustratively, the platen comprises a plurality of wafer slots. Wafers are loaded into the other slots by rotating the platen to the appropriate position. - Fig. 4b shows the reaction chamber in greater detail. As shown, the reaction chamber comprises platen. The platen rotates around a hub 302 (the direction of rotation of platen 380 is arbitrary). Illustratively, the platen includes a plurality of slots for placement of a wafer therein. Typically, the slots are depressed such that the top surface of the wafer, when placed therein, is substantially planar with the surface of the platen.
- A plurality of injectors is located at the circumference of the reaction chamber.
Feed lines 370 connected to the injectors provide materials from a supply source for the reaction. The number of feed lines depends on the number of different types of materials used for forming the layer. The materials are mixed and delivered into the reaction area of the chamber by the injectors. - An
exhaust port 385 passes excess materials and by-products of the reaction out of the reaction chamber. The exhaust port is formed by, for example, an interior passageway throughhub 302 for venting gases from the reactor chamber. As such, the direction of the flow of the chemistry is from injectors toward the center. Alternatively, reversing the direction of chemistry flow is also useful. Reversing the flow is achieved by locating the injectors at the center of the chamber and the exhaust vents at the circumference of the chamber. - The reactor is essentially isothermal. In one embodiment, heaters (not shown for ease of illustration), which may be resistive, are strategically located throughout the reactor chamber to compensate for any heat loss. In this manner, a constant temperature may be maintained during the deposition process. For example, there may exist an inner heater proximate to exhaust port to compensate for the heat loss therethrough. An outer heater surrounding the reactor chamber compensates for the heat loss to the outside world. Preferably, there is also provided a resistive middle heater, which radiates heat to the entire chamber to maintain a suitable wafer temperature during deposition.
- Referring to Fig. 4c, an illustrative reaction chamber is provided with twelve injectors (depicted by arrows). Providing the reaction chamber with a fewer or a greater number of injectors is also useful. The injectors are equally spaced apart at the periphery of the reaction chamber. Each injector therefore defines a 30° injection area in the reactor chamber, as delineated by the dotted lines. In other words, each injector injects into a different sector of the reactor. Such an injection scheme is referred to as a segmented delivery system.
- In operation, source materials for the silicate glass, which typically are in gaseous form, are injected into the reaction chamber via the injectors. The source material flows from the injectors toward the center of the reaction chamber. Simultaneously, the platen supporting the wafers is rotated, moving the wafers through the injected source materials. As the source materials contact the wafer surfaces, they chemically react to deposit doped silicate glass thereon. Excess source materials and their by-products are exhausted through exhaust port.
- In operation, source materials for the silicate glass, which typically are in gaseous form, are injected into the reaction chamber via the injectors. The source material flows from the injectors toward the center of the reaction chamber. Simultaneously, the platen supporting the wafers is rotated, moving the wafers through the injected source materials. As the source materials contact the wafer surfaces, they chemically react to deposit doped silicate glass thereon. Excess source materials and their by-products are exhausted through exhaust port.
- In accordance with one embodiment of the invention, source materials that make up BPSG are injected into the reaction chamber. In one embodiment, two source materials or chemistries are injected to form BPSG. The first chemistry comprises, for example, TEB/TEOS/O2/N2. The TEOS (tetraethoxysilane) is the source of silicon, TEB (triethyl borate) provides the source of boron (B) dopant atoms, and O2 and N2 are carrier gases. The second source material comprises a phosphine chemistry such as PH3/O2/N2. PH3 (phosphine) provides the source of phosphorus (P) dopant atoms, and O2 and N2 are oxidation and carrier gases. Other chemistries used in forming BPSG are also useful.
- The two chemistries are, for example, flowed into the reaction chamber via alternating injectors. The formation of the BPSG layer is achieved using conventional process conditions, such as those described in Tedder et al., Appl. Phys. Lett. 62, p. 699 (1993).
- In one embodiment, the dopant concentration varies over the deposition of the BPSG layer. The concentration of the dopants in the bottom is greater than an amount which causes surface crystal growth. The concentration, for example, is about 20 wt%. Preferably, the concentration of dopants is about 15 wt% at the bottom. P dopants are provided for gettering purposes. Typically the P concentration is about 2-6 wt%. As such, the concentration of B, which lowers the melting point of the BPSG, is about 14-18 wt%. Of course, the actual concentration depends on the design requirement. Since the concentration of the dopant that lowers the melting point of the BPSG is relatively high, reflow is enhanced. This enables the lower portion of the BPSG to fill smaller gaps having a higher aspect ratio than, for example, 4:1.
- The concentration of dopants in the upper portion of the layer is less than the bottom portion so as to provide a BPSG layer having an overall dopant concentration below that which causes surface crystal growth. For example, the layer can comprise a dopant concentration gradient that is about 20 wt%, preferably 15wt%, and decreases toward the top to provide a layer having an overall dopant concentration less than that which causes surface crystal growth. In one embodiment, the concentration at the upper portion is about 0 wt%.
Claims (1)
- A method of fabricating an integrated circuit comprising:providing a substrate comprising high aspect ratio device features separated by narrow spaces;forming a doped silicate glass layer over the substrate surface, wherein the bottom portion of the doped silicate glass comprises a dopant concentration that is greater than an amount which causes surface crystal growth, so as to decrease the melting point of the glass to provide gap fill of the narrow spaces, and wherein an upper portion of the doped silicate glass comprises a dopant concentration lower than the bottom portion, to result in the doped silicate glass layer having a dopant concentration that is below that which causes surface crystal growth.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US942273 | 1997-09-30 | ||
US08/942,273 US6096654A (en) | 1997-09-30 | 1997-09-30 | Gapfill of semiconductor structure using doped silicate glasses |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0908946A2 EP0908946A2 (en) | 1999-04-14 |
EP0908946A3 EP0908946A3 (en) | 1999-08-11 |
EP0908946B1 true EP0908946B1 (en) | 2006-11-15 |
Family
ID=25477840
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP98118244A Expired - Lifetime EP0908946B1 (en) | 1997-09-30 | 1998-09-25 | Improved gapfill of semiconductor structures using doped silicate glass |
Country Status (7)
Country | Link |
---|---|
US (2) | US6096654A (en) |
EP (1) | EP0908946B1 (en) |
JP (1) | JPH11176826A (en) |
KR (1) | KR100516037B1 (en) |
CN (1) | CN1143368C (en) |
DE (1) | DE69836406T2 (en) |
TW (1) | TW400536B (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6096654A (en) * | 1997-09-30 | 2000-08-01 | Siemens Aktiengesellschaft | Gapfill of semiconductor structure using doped silicate glasses |
US6514876B1 (en) * | 1999-09-07 | 2003-02-04 | Steag Rtp Systems, Inc. | Pre-metal dielectric rapid thermal processing for sub-micron technology |
US6362508B1 (en) * | 2000-04-03 | 2002-03-26 | Tower Semiconductor Ltd. | Triple layer pre-metal dielectric structure for CMOS memory devices |
US6511923B1 (en) * | 2000-05-19 | 2003-01-28 | Applied Materials, Inc. | Deposition of stable dielectric films |
US6521537B1 (en) * | 2000-10-31 | 2003-02-18 | Speedfam-Ipec Corporation | Modification to fill layers for inlaying semiconductor patterns |
US6358845B1 (en) | 2001-03-16 | 2002-03-19 | Taiwan Semiconductor Manufacturing Company | Method for forming inter metal dielectric |
JP2004214610A (en) * | 2002-12-20 | 2004-07-29 | Renesas Technology Corp | Method of manufacturing semiconductor device |
DE102005022840B3 (en) * | 2005-05-18 | 2006-09-28 | Infineon Technologies Ag | Contact structure manufacture for dynamic random access memory, by forming contact openings on isolation layer on top of semiconductor substrate, annealing semiconductor substrate and filing contact openings with conductive material |
JP2007180365A (en) * | 2005-12-28 | 2007-07-12 | Nec Electronics Corp | Semiconductor device and manufacturing method therefor |
US7884030B1 (en) * | 2006-04-21 | 2011-02-08 | Advanced Micro Devices, Inc. and Spansion LLC | Gap-filling with uniform properties |
US7927990B2 (en) * | 2007-06-29 | 2011-04-19 | Sandisk Corporation | Forming complimentary metal features using conformal insulator layer |
CN110120382A (en) * | 2019-05-23 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | Semiconductor devices and forming method |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60198847A (en) * | 1984-03-23 | 1985-10-08 | Nec Corp | Semiconductor device and manufacture thereof |
JPS61245541A (en) * | 1985-04-23 | 1986-10-31 | Seiko Instr & Electronics Ltd | Manufacture of silicon oxide film |
JPH0793354B2 (en) * | 1988-11-28 | 1995-10-09 | 株式会社東芝 | Method for manufacturing semiconductor device |
US5094984A (en) * | 1990-10-12 | 1992-03-10 | Hewlett-Packard Company | Suppression of water vapor absorption in glass encapsulation |
JP2538722B2 (en) * | 1991-06-20 | 1996-10-02 | 株式会社半導体プロセス研究所 | Method for manufacturing semiconductor device |
JPH07245342A (en) * | 1994-03-03 | 1995-09-19 | Fuji Electric Co Ltd | Semiconductor device and its manufacture |
DE9412376U1 (en) * | 1994-08-01 | 1995-12-07 | TELBUS Gesellschaft für elektronische Kommunikations-Systeme mbH, 85391 Allershausen | Memory circuit to compensate for bit errors in memory modules |
US5770469A (en) * | 1995-12-29 | 1998-06-23 | Lam Research Corporation | Method for forming semiconductor structure using modulation doped silicate glasses |
US5642316A (en) * | 1996-05-21 | 1997-06-24 | Information Storage Devices, Inc. | Method and apparatus of redundancy for non-volatile memory integrated circuits |
US5656556A (en) * | 1996-07-22 | 1997-08-12 | Vanguard International Semiconductor | Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures |
US5716890A (en) * | 1996-10-18 | 1998-02-10 | Vanguard International Semiconductor Corporation | Structure and method for fabricating an interlayer insulating film |
US5753948A (en) * | 1996-11-19 | 1998-05-19 | International Business Machines Corporation | Advanced damascene planar stack capacitor fabrication method |
US5807792A (en) * | 1996-12-18 | 1998-09-15 | Siemens Aktiengesellschaft | Uniform distribution of reactants in a device layer |
US6096654A (en) * | 1997-09-30 | 2000-08-01 | Siemens Aktiengesellschaft | Gapfill of semiconductor structure using doped silicate glasses |
-
1997
- 1997-09-30 US US08/942,273 patent/US6096654A/en not_active Expired - Lifetime
-
1998
- 1998-09-25 EP EP98118244A patent/EP0908946B1/en not_active Expired - Lifetime
- 1998-09-25 DE DE69836406T patent/DE69836406T2/en not_active Expired - Lifetime
- 1998-09-28 KR KR10-1998-0040203A patent/KR100516037B1/en not_active IP Right Cessation
- 1998-09-28 CN CNB981197663A patent/CN1143368C/en not_active Expired - Fee Related
- 1998-09-30 JP JP10279022A patent/JPH11176826A/en active Pending
-
1999
- 1999-02-09 TW TW087116258A patent/TW400536B/en not_active IP Right Cessation
- 1999-09-28 US US09/407,384 patent/US6048475A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
TW400536B (en) | 2000-08-01 |
EP0908946A3 (en) | 1999-08-11 |
US6048475A (en) | 2000-04-11 |
DE69836406D1 (en) | 2006-12-28 |
KR100516037B1 (en) | 2005-12-08 |
US6096654A (en) | 2000-08-01 |
JPH11176826A (en) | 1999-07-02 |
CN1143368C (en) | 2004-03-24 |
CN1221211A (en) | 1999-06-30 |
DE69836406T2 (en) | 2007-09-20 |
KR19990030191A (en) | 1999-04-26 |
EP0908946A2 (en) | 1999-04-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6180480B1 (en) | Germanium or silicon-germanium deep trench fill by melt-flow process | |
US6869874B2 (en) | Method for fabricating contact plug with low contact resistance | |
US5928959A (en) | Dishing resistance | |
US5770469A (en) | Method for forming semiconductor structure using modulation doped silicate glasses | |
US6511888B1 (en) | Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step | |
US9129848B2 (en) | Method and structure for integrating capacitor-less memory cell with logic | |
EP0908946B1 (en) | Improved gapfill of semiconductor structures using doped silicate glass | |
US20020045322A1 (en) | Method of depositing tungsten nitride using a source gas comprising silicon | |
US6743670B2 (en) | High dielectric constant materials forming components of DRAM such as deep-trench capacitors and gate dielectric (insulators) for support circuits | |
US8772178B2 (en) | Technique for forming a dielectric interlayer above a structure including closely spaced lines | |
US6344673B1 (en) | Multilayered quantum conducting barrier structures | |
EP1025583B1 (en) | Improved gapfill of semiconductor structure using doped silicate glasses with multi-step deposition/anneal process | |
US6344390B1 (en) | Methods of forming the buried strap and its quantum barrier in deep trench cell capacitors | |
US6040020A (en) | Method of forming a film having enhanced reflow characteristics at low thermal budget | |
CN100413055C (en) | Method for making conpacitor device of integrated circuit and structure thereof | |
US6524911B1 (en) | Combination of BPTEOS oxide film with CMP and RTA to achieve good data retention | |
JP2001518712A (en) | Improved gap filling of semiconductor structures using doped silicate glass in a multi-step deposition / annealing process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB IE IT NL |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
17P | Request for examination filed |
Effective date: 19991214 |
|
AKX | Designation fees paid |
Free format text: DE FR GB IE IT NL |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: INFINEON TECHNOLOGIES AG |
|
REG | Reference to a national code |
Ref country code: HK Ref legal event code: WD Ref document number: 1017490 Country of ref document: HK |
|
RTI1 | Title (correction) |
Free format text: IMPROVED GAPFILL OF SEMICONDUCTOR STRUCTURES USING DOPED SILICATE GLASS |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: QIMONDA AG |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB IE IT NL |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20061115 Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED. Effective date: 20061115 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REF | Corresponds to: |
Ref document number: 69836406 Country of ref document: DE Date of ref document: 20061228 Kind code of ref document: P |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D |
|
NLV1 | Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act | ||
EN | Fr: translation not filed | ||
EN | Fr: translation not filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20070817 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070629 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20070925 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20070925 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20070925 Ref country code: FR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20061115 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R081 Ref document number: 69836406 Country of ref document: DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE Ref country code: DE Ref legal event code: R081 Ref document number: 69836406 Country of ref document: DE Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R081 Ref document number: 69836406 Country of ref document: DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20170920 Year of fee payment: 20 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R071 Ref document number: 69836406 Country of ref document: DE |