EP0895159A1 - Method for flushing high throughput transfer buffers and apparatus for carrying out the method - Google Patents

Abstract

The method of removing bottle necks involves placing a transporter (4) in a functioning absorption mode. In this mode replies are accepted independent of their order of arrival on paths (400, 401) and are ignored by the transporter. Generation of specific handwriting is requested. A specific perusal request in all or some of the links is generated. Specific requests have no effect on memories (12a,12c). Each barrier marker and control character is in response to each specific request. Replies are compared so as to detect a location of a breakdown.

Description

The present invention relates to a method of purging buffers. high speed serial links as well as a device for implementing the process. The invention relates more particularly to a method and device for purging the serial link buffers of an integrated circuit or two circuits Integrated with a parallel serial and parallel serial port.

The invention applies in particular when it is desired to use gigabit serial links having a non-zero error rate, of the order for example of 10 ^-15 to 10 ^-17 , to make an internal connection to a logic assembly which is normally realized by a parallel link which is not subject to disturbances. This substitution is motivated by the fact that fast serial links have many advantages. For example, fast serial links have a high density, simplicity of connection with identical bandwidth and allow a long link, up to 10 meters for example, which is impossible with standard internal logical links.

In the case where the serial link is a 1 Giga baud serial link, and if it is assumed that two ports of the same type communicate with each other via the serial link, and allow machines, whose error rate is the order of 10 ^-17 by message corruption and loss of calibration and / or protocol inconsistency, to communicate with each other, it is noted given the speed of the serial link and the machine error rate, that this rate errors that seem small can cause a major error and a machine malfunction every two days.

The invention can be applied, for example, when the activity of a serial link has been stopped following the detection of an error and requires a recovery procedure which makes the disturbance invisible to the user. In this Regarding the detection of errors on the serial link, we can refer to the French patent application filed by the applicant on June 26 1997 under number 97 07997.

There are known integrated circuits comprising interfaces between a parallel bus and a serial bus, but in general these do not have error recovery device and method, because it is assumed that the communication contains no errors involving the connection series, or if it includes one, error recoveries are made in a higher layer (loss of calibration) at the software level (Software).

A first object of the invention is to propose a purging process high-speed serial link buffers for setting or restoring link service links that were stopped due to, for example, of a disturbance.

• une étape de mise du transbordeur dans un mode de fonctionnement dit d"'absorption" dans lequel les réponses sont acceptées
• une étape de génération d'une requête spécifique d'écriture et d'une requête spécifique de lecture dans tout ou partie des voies de la liaison série, les requêtes spécifiques étant sans effet sur les mémoires et comportant chacune un. marqueur dit de "barrière" contenu dans un caractère de contrôle précédant et/ou suivant la requête, la marque de barrière se retrouvant également dans un caractère de contrôle associé à la réponse correspondante de chaque requête spécifique,
• une étape de cumul des réponses reçues comportant un marqueur de barrière, et
• une étape de comparaison des réponses reçues comportant un marqueur de barrière avec les requêtes spécifiques générées, pour permettre, soit la localisation d'une panne éventuelle dans le cas où des réponses attendues pour un marqueur de barrière sont manquantes, soit la reconnaissance que la purge de l'ensemble des voies a été effectuée dans le cas où toutes les réponses attendues avec un marqueur de barrière ont été reçues.

This object is achieved by the fact that for the purging of the buffers (buffer) of high-speed serial links used between a transporter circuit (MOVER) performing data movement operations, namely reads and writes, and at least two memories, the ferry (MOVER) being connected to each memory by at least two channels, the data movement operations each consisting of a movement request followed by return of a response, or acknowledgment of the request, the ferry using at least two bidirectional channels connecting it to a memory in a cyclic manner with interleaving, for the same operation, each section of track retaining the order of emission of the requests, respectively of the responses, of the same train of requests, respectively of the same train of responses, the responses using the same pair of serial channels as the requests for which they constitute acknowledgment, the method comprises :

• a step of putting the ferry in a mode of operation called "absorption" in which the responses are accepted
• a step of generating a specific write request and a specific read request in all or part of the channels of the serial link, the specific requests having no effect on the memories and each comprising a. so-called "barrier" marker contained in a control character preceding and / or following the request, the barrier mark also being found in a control character associated with the corresponding response of each specific request,
• a step of accumulating the responses received comprising a barrier marker, and
• a step of comparing the responses received comprising a barrier marker with the specific requests generated, to allow either the location of a possible failure in the event that expected responses for a barrier marker are missing, or the recognition that the purging of all channels has been performed in the event that all the expected responses with a barrier marker have been received.

According to another particular feature, the step of comparing the responses received with a barrier marker with specific requests generated includes a step of comparing the number of responses received with barrier marker with the number of specific requests generated.

According to another particular feature, the control character (s) associated with the requests, respectively the responses, contain information about the emission source and the paths taken by the requests, respectively by the responses, the step of comparing the responses received including a barrier marker with requests specific generated including a step of reading information contained in the response control characters with marker barrier and which relate to the emission source and the paths taken, to allow the localization of possible faults of the serial link.

According to another particular feature, the step of placing the ferry in "absorption" mode is performed while the serial link is disconnected, the serial link being restarted after putting the ferry in the "absorption" mode.

According to another particular feature, the specific write requests are made up of partial write requests with a null mask so as not to not change the state of the machine during the purge.

In another feature, the ferry makes transfers data in blocks of up to 4K bytes and stored in registers the information on the data block transferred in progress and the next block of data to transfer to allow resumption of transfer data to the point where it was before the failure.

According to another particular feature, when the step of comparing the responses received, including barrier marker with requests generated, leads to the recognition that the purging of all the tracks have been completed, the ferry is returned to the normal operation in which it uses the channels connecting it to a memory cyclically, with interleaving.

According to another particular feature, the method of purging the buffers (buffer) of high speed serial links is used following a failure of the link such as an electrical disturbance, after restarting or reset the serial link and before restarting the application course at the last checkpoint, without resetting the entire system.

According to another particular feature, the method of purging the buffers high-speed serial link (buffer) is used for scanning self-test from the subset of the memory interconnection network to ferry, the location of any faults allowing the reconfiguration of the link in a degraded mode ignoring the channel (s) Out of order.

According to another particular feature, each bidirectional channel of the serial link consists of two unidirectional cables, the data transit directions are opposite.

Another object of the invention is therefore to propose a device allowing the implementation of the method.

• des moyens de mise du transbordeur dans un mode de fonctionnement dit d"'absorption" dans lequel les réponses sont acceptées indépendamment de tout ordre d'arrivée sur les différentes voies et sont ignorées par le transbordeur,
• des moyens de génération d'une requête spécifique d'écriture et d'une requête spécifique de lecture dans chacune des voies de la liaison série, les requêtes spécifiques étant sans effet sur les mémoires et des moyens de générer dans ces requêtes un marqueur dit de "barrière" contenu dans un caractère de contrôle précédant et/ou suivant la requête, des moyens de générer un marqueur de barrière dans un caractère de contrôle associé à la réponse correspondante de chaque requête spécifique,
• des moyens de cumul des réponses reçues comportant un marqueur de barrière, et
• des moyens de comparaison des réponses reçues comportant un marqueur de barrière avec les requêtes spécifiques générées pour permettre soit la localisation d'une panne éventuelle dans le cas des réponses attendues comportant un marqueur de barrière sont manquantes, soit la reconnaissance que la purge de l'ensemble des voies a été effectuée dans le cas où toutes les réponses attendues comportant un marqueur de barrière ont été reçues.

This object is achieved by the fact that the device for implementing the method of purging buffers (buffer) of high speed serial links is applied to high speed serial links being by a transporter circuit (MOVER) carrying out operations of movement of data, namely reads and writes, between at least two memories, the transporter (MOVER) being connected to each memory by at least two bidirectional channels, the data movement operations each consisting of a movement request followed in return by a response, or acknowledgment of the request, the ferry using the tracks connecting it to a memory in a cyclic manner with interleaving, for the same operation, each section of track retaining the order of emission of the requests, respectively responses, from the same train of requests, respectively from the same train of responses, the responses following the same path as the requests thy which they constitute the acknowledgment, the device comprising:

• means for putting the ferry in a mode of operation called "absorption" in which the responses are accepted independently of any order of arrival on the different tracks and are ignored by the ferry,
• means for generating a specific write request and a specific read request in each of the channels of the serial link, the specific requests having no effect on the memories and means for generating in these requests a so-called marker of "barrier" contained in a control character preceding and / or following the request, means for generating a barrier marker in a control character associated with the corresponding response of each specific request,
• means for accumulating the responses received comprising a barrier marker, and
• means for comparing the responses received comprising a barrier marker with the specific requests generated to allow either the location of a possible breakdown in the case of the expected responses comprising a barrier marker are missing, or the recognition that the purging of the set of routes has been performed in the event that all expected responses with a barrier marker have been received.

According to another particular feature, the device for purging buffers (buffer) of high speed serial links includes means of comparison of the number of responses received with barrier marker with the number of specific requests generated.

According to another particular feature, the device for purging buffers (buffer) of high-speed serial links includes means of generating information about the emission source and the paths taken by the requests, respectively by the responses in the character or characters of control associated with requests, respectively responses, the device purge comprising means for reading the information contained in these response control characters with barrier marker concerning the emission source and the paths taken, to allow the localization of possible failures of the serial link.

According to another particular feature, the device for purging buffers (buffer) of high speed serial links includes processing means of data ensuring the reset of the serial link followed by the setting of the ferry in the so-called absorption mode ".

According to another particular feature, the data processing means ensure the generation of specific requests for writing and reading, responses with barrier marker to specific requests being taken into account by these same data processing means.

According to another particular feature, the data processing means have at least one accumulation register of which each bit is representative the generation of a specific request, each response with a marker of barrier received by the processing means causing the writing of a bit said of "barrier" in the accumulation register to allow the comparison of number of responses received with barrier marker with number of specific requests generated.

According to another particular feature, the data processing means include timing means allowing the generation of a failure detection message in case an expected response with barrier marker is missing after a lapse of time determined.

• la figure 1 représente de manière schématique et simplifiée le système de liaison série reliant deux mémoires via un dispositif de transfert de données, dans lequel un processus de purge selon l'invention est réalisé,
• la figure 2 représente de manière schématique une partie détaillée d'un chemin ou lien de la liaison série de la figure 1,
• la figure 3A représente la partie un circuit intégré constituant un port d'interface série parallèle selon l'invention,
• la figure 3B représente le schéma général d'un circuit intégré incorporant un tel port d'interface,
• la figure 3C représente le schéma de la partie du circuit intégré constituant le circuit transbordeur (MOVER),
• la figure 4 représente le schéma d'architecture d'une machine utilisant le circuit intégré de la figure 3B,
• la figure 5 représente de manière schématique et simplifiée les fonctionnalités mises en oeuvre par l'architecture de la figure 3B, constituant le dispositif de purge des tampons de la liaison série selon l'invention,
• la figure 6 représente de manière schématique et simplifiée une partie d'un lien de la liaison série reliant le dispositif de transfert de donnée à une mémoire,
• la figure 7A représente un logigramme simplifié illustrant les étapes du processus de purge de la liaison série selon l'invention,
• la figure 7B représente un logigramme simplifié détaillant une partie des étapes du processus illustré à la figure 7A,
• la figure 8 représente schématiquement un réseau d'interconnexions auquel est appliqué le procédé de purge de liaisons série selon l'invention.

Other features and advantages of the present invention will appear more clearly on reading the description below made with reference to the appended drawings in which:

• FIG. 1 shows schematically and simplified the serial link system connecting two memories via a data transfer device, in which a purging process according to the invention is carried out,
• FIG. 2 schematically represents a detailed part of a path or link of the serial link of FIG. 1,
• FIG. 3A represents the part of an integrated circuit constituting a parallel serial interface port according to the invention,
• FIG. 3B represents the general diagram of an integrated circuit incorporating such an interface port,
• FIG. 3C represents the diagram of the part of the integrated circuit constituting the transporter circuit (MOVER),
• FIG. 4 represents the architecture diagram of a machine using the integrated circuit of FIG. 3B,
• FIG. 5 schematically and simplified represents the functionalities implemented by the architecture of FIG. 3B, constituting the device for purging the buffers of the serial link according to the invention,
• FIG. 6 schematically and simplified represents part of a link of the serial link connecting the data transfer device to a memory,
• FIG. 7A represents a simplified flow diagram illustrating the steps in the process of purging the serial link according to the invention,
• FIG. 7B represents a simplified flow diagram detailing part of the steps of the process illustrated in FIG. 7A,
• FIG. 8 diagrammatically represents an interconnection network to which the serial link purging method according to the invention is applied.

The invention, the method of which is explained below, requires for its implementation of the use of ports such as that of FIG. 3A.

Port 10 _0, called Serial Link Control (SLC) control block, is incorporated into an integrated circuit of the type, for example, shown in FIG. 3B. This integrated circuit (1) comprises a plurality of ports 10 ⁰ , 10 ¹ , 10 ² , 10 ³ of the same type as that of FIG. 3A, which communicate at a system frequency, for example of 33 MHz, with two parallel buses of 72-bit data, L2CB at input (6) and C2LB at output (7). These parallel buses communicate with logic circuits (3, 4, 5) providing for the circuit (3) an interface functionality with a microprocessor via a 64-bit bus (30), for the circuit (4) a transhipment functionality (MOVER) for the integrated circuit when the latter is incorporated in a data type card, and for the circuit (5) a memory controller functionality (Slave Control). These circuits (3, 4, 5) also communicate by two 72-bit data buses M2CB (9), C2MB (8), with two IOBX 2 ⁰ , 2 ¹ input / output interfaces, which allow communication with buses 36 bits coming either from a memory (12a, fig. 4) main MMU, or from a memory (12c) of extension EMU as represented in figure 4. A control bus CPB allows the microprocessor communicating with the integrated circuit (1) to access the control and status registers (Status) of the various circuits (3, 4, 5, 2, 10) present in the integrated circuit. This integrated circuit (1) is used in a machine comprising a main memory (12a), an extended memory (12c) which can be shared by several systems. A first integrated circuit (1a) according to the invention communicates by the bus (30a) with a first processor (11a) and by the IOBX interface with the memory (12a), while a second integrated circuit (1c) slave communicates on the one hand, with the first master circuit (11a), and on the other hand by the bus (30c) with a second processor (11c) and with an extended memory (12c). The serial parallel transmission and parallel serial reception port (10a) of the circuit (1a) comprises for the transmission part (40, FIG. 3A) a pair of TDBUF 8 x 72 bit buffers linked to the transmission bus. C2LB. A multiplexer (103) makes it possible to select one of the two buffers (buffers) TDBUF or one of the two buffers (buffer) TCBUF of control signals which contain the header. A TCBUF buffer and a TDBUF buffer can be unified to form a TBUF buffer. The information leaving the multiplexer (103) is sent on a disassembly circuit (105), which generates a succession of 9-bit characters constituting the characters to be transmitted. This disassembly circuit (105) is also connected to a CRC redundant cyclic control character generation circuit (106 _T ). A second multiplexer (107) makes it possible to select the signals transmitted to an encoder (108 _T ) allowing the 9/12 coding of the information transmitted by associating with the normal character formed of a nonet, a control bit and, by supplementing with 12 bits by a start bit and a stop bit. The multiplexer (107) receives signals from a serial link transmission state machine (1021T) which contains at least one 2-bit token counter, each bit of which represents a token indicating the availability of the associated buffer. The multiplexer (107) receives signals from a substitute state machine (1022 _T ), and signals from a port initialization state machine (1023 _T ). The output of the encoder (108 _T ) is connected to a serializer circuit (109 _T ), the output of which constitutes a serial line (120) which transmits signals at a speed for example of 1 Giga bits / sec. The serializer is also connected by a serial loopback link (1090) to a deserializer (109 _R ) of the reception circuit, or reception part (41) of the port (10 ⁰ ). This serial loopback link (1090) is validated on the deserializer (109 _R ) by a signal (lct03). Each transmission buffer is controlled by a state machine for managing the transmission buffers (101 _T ) which receives Istatus 0: 6, Istrw 0: 3, and transmits the signal Inrdy. In the reception part (41), the deserializer (109 _R ) is connected to a decoder (108 _R ) operating on the same principle as the encoder (108 _T ) of the transmission circuit. This decoder of the reception circuit sends the 9 bits of each data on a circuit (104) of data assembly, to transform into a message of (1 x 72, 3 x 72, 8 x 72, 9 x 72) the data received in series, which are loaded into a pair of data reception buffers (RDBUF). This pair of data reception buffers (RDBUF) is controlled by a state machine for managing reception buffers (101 _R ) and is associated with a pair of command reception buffers (RCBUF). which contain the message headers. The output of the decoder (108 _R ) of the reception circuit is connected to a message verification code circuit developing a CRC cyclic control character (106 _R ) for comparison. The CRC _{N + 1} is updated after each reception of 9 bits of data by calculating the CRC over 16 bits by a cyclic permutation algorithm on the basis of the data received D _i and of the values R _i of the bits of the preceding CRC _N. Of course, we can plan to calculate the CRC on 18 bits instead of 16 bits. The information transmitted by this decoder (108 _R ) is also transmitted on the one hand, to a state machine constituting a history buffer (1022 _R ), and on the other hand, to a state machine from the receiving port (1021 _R ), and finally to an initialization state machine (1023 _R ) from the port. The reception buffer management state machine (101 _R ) sends three signals (Connect, Outrdy, Status 0: 10), and receives the information on three lines as input (Istrr 0: 3). The signal (Outrdy) indicates that the output is ready, this signal indicates that there is a complete message awaiting reading. The Status signal indicates the status of the outputs: interruptions or not, indivisible operations or not, memory access / access registers, local / remote or ISCON / non ISCON, micro source / ferry (MOVER) / slaves (SLAVE), delayed responses or not, last message or not, data error or not, access out of memory or not, message insignificant or not. The Connect output indicates that the SLC port (10 ⁰ ) is disconnected when this output is deactivated. The Istrr inputs allow the reception ports to be read in FIFO order, and the command which reads the last double word of a message generates the generation of a flow control character (token) associated with the buffer which becomes thus free. This flow control character is transmitted from the state machine for managing the reception buffers (101 _R ) to the state machine for managing the transmission (1021T), and through the latter to the multiplexer. (107) so as to transmit this information to the input port (10c) of the card (1c) associated in the serial link to the reception port (109 _R ) for which the reception buffers (RDBUF) have just been read ). The state machine for managing the transmission buffers (101 _T ) has two Istatus and Istrw inputs, and an Inrdy output. This Inrdy output indicates that there is a free transmission buffer (TDBUF) waiting to be written. The Istatus lines allow you to specify the types of message to write, and to determine according to the value of the first two status bits the following meanings: 00 are not used, 01 is only data, 10 is is a header, 11 it is a header and data. The third bit Istatus, indicates whether it is the last message or not. The fourth bit, whether it is a data error or not; and the fifth bit if we have an external access to the memory or not. Finally the signal Istrw makes it possible to write the buffers of transmissions (TDBUF) in FIFO order. The signal Istrw which writes the last double word of a message initializes the transmission of the message as soon as a remote reception buffer (RDBUF) (for example from port 10c) is declared free by a reception port connected to the serial link (120) and when the possible transmission in progress from another transmit buffer of the same serial parallel port is finished.

The transporter part (4) of the integrated circuit comprises each next to a header calculation circuit (40a, 40b). A first (40a) circuit header calculation is connected to the circuit's C2LB transmission bus SLC serializer and C2MB transmission bus from IOBX port. A second (40b) header calculation circuit is connected to the C2LB transmission bus SLC serializer circuits, and to the C2MB transmission bus of the ports IOBX. This header calculation circuit for reception (40a) receives information from RLP, RPA, RIPA, RAC registers, registers RLP receiving information from the RNLP register. The RPA register receives RNPA register information, these two RPA and RNPA registers being 28-bit registers. The 7-bit RAC register receives information from the 7-bit RNAC register. The RAC, RNAC, RIPA, RPA, RLP registers can be accessed by the given part of the CPB bus, likewise for the register RNLP, RNPA.

A FIFO register stack (41) is connected on the one hand to the L2CB, M2CB reception, on the other hand, to the C2LB, C2MB transmission bus. This stack (41) of register of 64 bytes of 9 bits is addressed in reading by a DSRP register and in writing by a DSWP register. The calculation circuit header for transmission (40b) receives information from registers WPA, WIPA, OVFB, WMSKB, OVFE, WMSKE, all of these circuits being controlled by an interrupt management circuit (42), a circuit for event management (43) and a control circuit (44). The register RIPA contains the internal address of a page formed on 6 bits, the RPA register contains the address of a page formed on 28 bits, and this allowing to access a current page of 4 Kbytes. The 7-bit RAC register allows to count the 64 bytes of access in the page. The RLP register constitutes a mark indicating whether the page is the last to be accessed.

The 28-bit RNPA register indicates the address of the next page, the 7-bit RNAC register contains the count of 64 bytes of access in the next page, the RNLP register is a mark indicating whether the next page is the last to be accessed. An NVR register constitutes a mark indicating whether these three previous registers have valid content. All these elements are the resources that allow address generation for the source memory in a transhipment.

Similarly, address generation resources for memory destination can be divided into three parts. A first resource constitutes the resources to manage write accesses in the first and last block of 64 bytes of transhipment. These first resources consist of a first mask specifying the first 8 bytes of the sub-block of the first transhipment block to write and content in the 3-bit WMSKB register. A second mask specifies the last 8-byte sub-block in the last displacement block to write, this mask being contained in a 3-bit WMSKE register. An OVFE register contains the indication of a write access in the first block of a transhipment. An OVFE register contains an indication of access writing in the last block of a transhipment. A second resource to access a current page of 4 Kbytes consists of a first 28-bit WPA address register containing the address of the page and a 6-bit WIPA register containing the address inside the page. The third resource gives information on the next page to access and consists of a WNPA address register containing the address of the next page on 28 bits, and a WNV register which constitutes a mark indicating whether these previous registers have valid content.

The FIFO stack (41) of 64 bytes is a data buffer dedicated to transhipment to manage the non-alignment of the departure addresses of the MMU and EMU. This buffer (41) is a FIFO with a pointer to 3-bit DSRP read and a 3-bit DSWP write pointer. The circuit control (44) authorizes the processor (11) to stop a transhipment and configure the ferry in a special way to handle a fatal serial link error. The event register (43) stores the source of an interruption intended for the processor interface circuit (3). The processor (11) connected to the circuit (1) provides the information for the read access to the first page of the source memory giving the transfer direction by an E2M bit set to 1 for a transfer of the EMU to the MMU, and to 0 for a transfer from the MMU to the EMU. This processor also loads RPA, RIPA addresses, access register RAC and the RLP register. This initialization inhibits the transmission of access writing to a destination memory.

The processor provides the information for the write accesses to the first page of the destination memory by loading: the starting address in the registers WPA, WIPA, the write mask for the first and the last 64 bytes in the WMSKB and WMSKE registers, the FIFO write pointer, the FIFO read pointer and the OVFB, OVFE registers. This initialization validates the transmission of a write access in the destination memory. Likewise, the processor (11) provides the information for the next page by loading the registers RNPA, RNLP and RNAC for the resource memory and, for the destination memory, the register WNPA. When the RAC register is not equal to 0, the circuit allows the generation of read access to the source memory. When the source memory is the EMU memory of FIG. 4, the read accesses of the EMU are interleaved on two serial links per block of 64 bytes transmitted on the serial link 10 ₀ for the blocks having an even address, and transmitted by the serial link 10 ₁ for the blocks having an odd address.

Each time a read request is transmitted, the RAC access account register is decremented by 1, 2 or 4, and the RIPA address register is incremented by 1, 2 or 4, depending on the type of request. . Data responses are transmitted over two serial links in blocks of 64 bytes according to the same interleaving rule. Likewise, the read accesses to the MMU are interleaved on the two IOBX interfaces, the first interface (2 ₀ ) for the blocks of 64 bytes having an even address and the second interface (2 ₁ ) for the blocks having an odd address. The RAC and RIPA registers are respectively decremented and incremented by 1 on each access. The transporter circuit memorizes the identification of the SLC or IOBX transmission circuit from which the first block of 64 bytes comes.

The operation of the writing part is identical by use WPA, WIPA registers, exchanges are also done in intertwined. The ferry (4) addresses the read requests to the memory source and uses the DSWP write pointer to write data from response in the FIFO stack (41). Whenever an 8-bit sub-block is written, the DSWP register is incremented by 1. When the ferry address write requests to the destination memory, it uses the DSRP read pointer to read data from the FIFO stack. Every time an 8-byte sub-block is read, the DSRP register is incremented by 1 and like every time a write request is sent, the circuit increments of 1 the WIPA register.

The integrated circuit of FIG. 3B, incorporated for example in an electronic circuit board comprising memories (Mo ... Mi, mo ... mj) achieves, by a transfer circuit (4) (MOVER), a displacement functionality of data between memories [(M0, ..., Mi], figure 1) and memories [(mo, ..., mj], figure 1). The memories [(M0, ..., Mi)] and [(m0, ..., mj] belong, for example, respectively to two different memories (12a, 12c) such as, for example, the memories MMU and EMU of the circuit of FIG. 4. The ferry (4) can use several high speed serial links (10 ₀ , 10 ₁ , 10 ₂ , 10 ₃ ), for example two bidirectional serial links (10 ₀ , 10 ₁ ) at high speed , to carry out data movement between the two memories (12a, 12c), for example, the ferry (4) performs data transfers between a main memory (12a) MMU and a memory (12c) with extension EMU. Serial link (10 ₀ , 10 ₁ ) constitutes, for example, a channel (400, 401) or even and odd paths respectively. Each path (400, 401) or channel uses two transmission cables (1400A, 1400B, figure 2) unidirectional with opposite data transmission directions. The two unidirectional transmission cables (1400A, 1400B) ent respectively the transmission of requests and responses from the same link or path (400, 401). Each path (400) comprises different buffers (200, FIG. 2) constituting stages of temporary storage for crossing cards or buses for example. The operations transiting on the channels (400, 401) of the serial links consist essentially of operations of reading and writing from a memory area (12a, 12c). Each operation (read or write) consists of a request followed by the return of a response or acknowledgment of the request. That is to say that for a read operation of a memory area, a read request is generated, then in return, a response signifying the acknowledgment of the read request is returned to the source of emission of the request. . Similarly, the write operations each consist of a write request followed by the return of a response or acknowledgment of the write request. The responses follow the same route (400, 401) as the requests for which they constitute an acquittal. In addition, for a given source and type of operation, the order of responses follows exactly the order of the requests for which they constitute acknowledgment. That is to say that for each channel (400, 401), the order of a train of responses to a read order is identical to the order of the train of read requests of which they constitute the acknowledgment. The same is true for write operations. Thus no "overtaking" is possible on the paths (400, 401). However, the respect of the order between read operations and write operations is not necessarily guaranteed. Requests are processed according to the cards available, ie not necessarily in their order of arrival, but the corresponding responses are returned to their source in the order of requests. In its so-called "normal" operating mode, the ferry (4) uses the tracks (400, 401) or paths cyclically, with interleaving. The data are interleaved on the different channels (400, 401) of the serial link. As mentioned above, the serial link can comprise, for example, two channels designated respectively as even channel (400) and odd channel (401). The choice of even (400) or odd channels for responses or requests depends solely on their address. For example, for a reading of 256 bytes (bytes), the source can transmit its request on the even channel (400) and can receive the first 64 bytes (bytes) read on this same channel (400) even, the second 64 ( bytes) bytes on the odd channel (401), the third 64 bytes (bytes) on the even channel (400) and finally the last 64 bytes on the odd channel (401). Each of the messages passing through the channels (400, 401), namely the requests and the responses, is preceded by a control character indicating the type and the length of the message. A second control character follows the end of the message and contains information on the status of the message, i.e., for example, if this message is the last message in a sequence and / or if memory has delivered a message error.

Figure 6 shows schematically on a section a bidirectional link two-way series (400, 401), connecting the ferry (4) to a memory (12b), a stream of read requests (rqj + 1, rqj, rqj-1, rqj-2, rqj-3, rqj-4, ...) on the first channel (400), and responses (..., rpi + 5, rpi + 4, rpi + 3, rpi + 2, rpi + 1, rpi) of reading on the second channel (401) which are interlaced with a flow of write requests (rqt + 1, rqt, rqt-1, rqt-2, rqt-3, rqt-4, ...) on the first channel (400) and responses (..., rps + 5, rps + 4, rps + 3, rps + 2, rps + 1, rps) of writing on the second channel (401). A disturbance (P) occurring on the link (400) of the first channel will block the link. Indeed, the error detection on one side (44A) of the link will generate an error of the other side (44B) of the link. The perturbation (P) isolates the link. Detection error causes an automatic reset of the link by through, for example, wired logic as described, by example, in the applicant's earlier applications entitled "Method for detecting errors on a serial link of an integrated circuit and device for implementing the process "and filed in France under the N ° .97 07997, "Device and method for detecting errors on a circuit integrated with a parallel serial port "filed in France under the number 97 01944 and "Method for initializing a serial link between two integrated circuits comprising a serial parallel port and setting device work of the process "filed in France under No. 97 02974. Detection an error by the serial link controller can generate an interrupt to the microprocessor (11, Figure 5) which manages the integrated circuit (1). The microprocessor (11) then initiates the reset of the serial link. Thus, following the detection of an error on a link, the two controllers link (SLC) located respectively at the two ends of the connection are disconnected from the outside and are reset by through the microprocessor (11). The messages (rqj + 1, rqj, rqj-1, rqj-2; rpi + 3, rpi + 2, rpi + 1, rpi) for reading and messages (rqt + 1, rqt, rqt-1, rqt-2; rps + 3, rps + 2, rps + 1, rps) of writing which passed on the link (400) are lost when resetting the link. Messages that have been sent to the memory (12b) before the disturbance, are blocked in the buffers (200) of the link pending the return to service of the bidirectional link (400). For example, pending messages are blocked in buffers or FIFO registers. That is to say that, for example, requests (rqj-3 and rqj-4, ...) and responses (..., rpi + 5, rpi + 4) in reading as well as the requests (..., rqt-3, rqt-4) and write responses (..., rps + 5, rps + 4) that were sent from completely to memory (12b) are blocked awaiting the return to service of the link (400). From the point of view of the outside of the link series, i.e. for the rest of the machine, the disturbance does not generate erroneous messages, in fact, only are sent to the outside of complete and valid messages. The link which is interlaced with the link (400) defective is also blocked. Indeed, the ferry (4) waits the responses in a cyclic manner on the interleaved links (400, 401). Of this fact the ferry (4) quickly ends up blocking the link (401) when waits for a response from the faulty link (400). If the disturbed connection is return to service after resetting, all messages (rqj-3, rqj-4; rpi + 5, rpi + 4; rqt-3, rqt-4; rps + 5, rps + 4) blocked in the buffers go resume their flow in the connection. So to avoid that pass on the link (401) of responses from operations which have failed because of the disturbance, all messages blocked in the buffers must be purged.

The method of purging the link according to the invention comprises a first step (70) in which the ferry (4) is put into a mode of so-called absorption ". In this mode, the ferry (4) accepts responses to requests regardless of their order of arrival on the different routes (400, 401). That is to say that, in the "absorption" mode, the ferry (4) no longer waits for responses cyclically. Through elsewhere, in the "absorption" mode, the responses received are ignored by the ferry (4). As symbolized in Figure 5, the placing of the ferry in "absorption" mode can be carried out by the microprocessor (11) which manages the integrated circuit (1) through the interface circuit (3, FIG. 3B and 5) of this integrated circuit (1) with the 64-bit bus (30). Thus, the ferry (4) of the circuit integrated (1) can be put in its "absorption" mode by the microprocessor (11) which manages this integrated circuit (1), by means of a logic (30) of management of the ferry located in the interface circuit (3). When the ferry (4) is in its absorption mode, the serial link is reset en route and the process continues with a step (71, Figure 7A) during of which a specific request for writing and a specific request for reads are generated in each of the channels (400, 401) of the serial link. Each of the specific requests has a marker or flag called "barrier" contained in the control character located at the end of the message sent on the channel. The barrier marker also appears in the control character located at the start of the message or header. That is, for each channel (400, 401) of the link, a request specific with barrier marker each type of operation is generated. Remember that the order of requests and responses for the same operation is kept strictly on each channel (400, 401) or path of the link. The responses to specific requests include also the corresponding barrier marks in their character of start or header control. Specific requests are also without effect on the memories, because they do not modify the state of the machine. Thus, specific write requests can, for example, be partial write requests with null mask, which do not perform any writing. Specific read requests which by definition do not modify not the memory state can be, for example, operations of reading memory blocks. The generation of specific requests is performed by request generation logic (31) located in the circuit interface (3) and controlled by the microprocessor (11) which manages the circuit integrated (1). The interface circuit (3) includes a request sequencer controlled by the microprocessor (11) to ensure this generation of specific requests by having in the header control character (header) of each request, the barrier mark. The purge process then continues with a step (72, FIG. 7A) of accumulating the responses received with a barrier marker. So the responses that return to the corresponding source of requests with a tag barrier, are collected by a logic (32) of cumulative circuit (3) interface. This logic (32), which collects or accumulates responses with barrier marker, includes a revstat accumulation register (33) of which each bit is representative of the generation of a specific request.

Each response has its special requests sets a bit in the revstat register, among 6 bits, in which bits 0 to 4 to indicate if the response comes by the serial link 10 ₀ to 10 ₃ and bits 4 to 6 to indicate if the response comes from the IOBXs of (2 ₀ ) or (2 ₁ ), so we determine the path taken by the requests and respectively by the responses. Each response with barrier marker received by the logic (32) of accumulation of the interface circuit (3) causes the writing of a corresponding bit called "barrier" in the accumulation register (33). The microprocessor (11) which manages the integrated circuit (1) will read the revstat accumulation register (33) to verify that the responses with barrier marker of all the specific requests have returned. The microprocessor (11) performs this reading of the revstat accumulation register (33) with a certain time delay. In this way, if the responses with the expected barrier marker are missing, the logic (3) will be able, in the next step (73), to locate possible breakdowns of the link. Indeed, the control characters associated with the requests, respectively with the responses, include information concerning the source of emission and the paths followed by the requests, respectively by the responses. In this way, the logic (32) of cumulative responses can locate the fault or faults in the serial link by determining the paths for which the expected responses have not returned. Ineffective data from responses with barrier marker are ignored by the interface circuit (3).

Figure 7B shows in more detail the process of determination of the valid paths of the connection by the interface logic (3). A mask (700) of the valid paths is produced by comparing the process for generating (72) requests and accumulating (72) with timing of corresponding responses. As shown in step (73) the location of possible faults allows the reconfiguration of the link in a degraded mode ignoring the faulty channel (s).

In the event that all of the expected barrier marker responses have been received, the microprocessor (11) recognizes in step (74) that the cleaning or purging of the serial link is complete and the current application can then be restarted from the last recovery point stored in the ferry (4). For example, the last recovery point of the ferry (4) can be automatically memorized at each reset in a specific register of the interface logic (3), which register is read by the microprocessor (11). The microprocessor can then return the ferry (4) to "normal" operating mode, in which it uses the channels connecting it to a memory, cyclically and with interleaving. The ferry (4) performs data transfers, in slices, for example of 4K bytes maximum and keeps in internal registers information on the data block which is being transferred and the next block of data to be transferred. In this way the transporter (4) can resume data transfer from the point where it was before any link failure. For this, the ferry (4) will search, at each reset, for this information characterizing the next data block to be transmitted. In the nonlimiting exemplary embodiment described in connection with FIGS. 3B and 3C, the EMA card has on the one hand four channels or paths (c0, c1, c2, c3) incorporating the SLC circuits (10 ₀ to 10 ₃ ) as shown diagrammatically in FIG. 5, towards the EMC card of the memory (12c) of extension EMU, or remote memory and, on the other hand of two paths (a0, a1) towards the memory (12a) main MMU or memory local incorporating IOBX circuits (2 ₀ and 2 ₁ ). In this case, the process of purging all of the paths will require the generation of six specific requests for reading with barrier marker and six specific requests for writing with barrier marker. Thus, the corresponding accumulation register (revstat) of the accumulation logic (32) comprises 12 bits. In the example described, the steps of the purge process of the serial link are carried out by a wired logic whose sequencing is ensured by a program executed by the microprocessor (11). Of course, without departing from the spirit of the invention, the process of purging the serial link can be carried out by a fully wired device.

We understand that we have a process and a device for purging serial link buffers that can be implemented easily following, for example, a link failure such as a electrical disturbance. This link purge process can be implemented after the resumption of service or reset of the serial link and before restarting the current application at the last recovery point, without requiring a reset of the entire system.

Of course, this purge device can also be used to the self-test by scanning the subset of the interconnection network of memories to a ferry, such as for example the ferry (4B) of the interconnection network shown schematically in Figure 8. The interconnection network of FIG. 8 comprises four ferries (4A, 4B, 4C and 4D). For example, the four ferries (4A, 4B, 4C and 4D) interleave the connection of four memory areas (mo, m1, m2, m3) extension with two main memory areas (M0, M1). Two first (4A, 4B) ferries are connected each, on the one hand to two first areas (m0, m1) extension memory and secondly, to both main memory areas (M0, M1). The other two (4C, 4D) ferries are each connected on the one hand to two second zones (m2, m3) extension memory and on the other hand to the same two memory zones (M0, M1) main. The process of generating specific requests in the four channels of the visible interconnection network subset of a ferry (48) and the processing of the corresponding responses received can allow the localization of possible faults by the device purge and thus a possible reconfiguration of the connection in a mode degraded ignoring the faulty channel (s) detected.

Other modifications within the reach of those skilled in the art make also part of the spirit of the invention.

Claims (17)

Method for purging buffers (buffer) of high speed serial links used between a transporter circuit (4) (MOVER) performing data movement operations, namely reads and writes, and at least two memories (12a, 12c ), the transporter (MOVER) being connected to each memory (12a, 12c) by at least two channels (400, 401), the data movement operations each consisting of a movement request followed by a response , or acknowledgment of the request, the ferry using at least two bidirectional tracks (400, 401) connecting it to a memory (12a, 12c) cyclically with interleaving, for the same operation, each section of track (400, 401) retaining the order of emission of the requests, respectively the responses, of the same train of requests, respectively of the same train of responses, the responses using the same pair of channels (400, 401) series as the requests for which they constitute the acquittal, characterized in that it comprises: a step of putting the ferry (4) in a mode of operation called "absorption" in which the responses are accepted regardless of any order of arrival on the tracks (400, 401) and are ignored by the ferry (4) , a step of generating a specific write request and a specific read request in all or part of the channels (400, 401) of the serial link, the specific requests having no effect on the memories (12a, 12c) and each comprising a so-called "barrier" marker contained in a control character preceding and / or following the request, the barrier mark also being found in a control character associated with the corresponding response of each specific request, a step of accumulating the responses received comprising a barrier marker, and a step of comparing the responses received comprising a barrier marker with the specific requests generated, to allow either the location of a possible failure in the event that expected responses for a barrier marker are missing, or the recognition that the purging of all channels (400, 401) has been performed in the event that all of the expected responses with a barrier marker have been received. Method for purging buffers from high serial links flow according to claim 1 characterized in that the step of comparing responses received including a barrier marker with requests specific data generated includes a step of comparing the number of responses received with barrier marker with number of requests specifics generated. Method for purging buffers from high serial links flow according to claim 1 or 2 characterized in that the one or more control characters associated with requests, respectively responses, include information about the emission source and the paths (400, 401) borrowed by the requests, respectively by the responses, the step of comparing the responses received comprising a marker of barrier with the specific requests generated comprising a step of reading the information contained in the control characters of the barrier marker responses relating to the source of emission and the paths (400, 401) taken, to allow the location of possible failures of the serial link. Method for purging buffers from high serial links flow according to any one of claims 1 to 3 characterized in that the step of putting the ferry (4) in the "absorption" mode is carried out while the serial link is disconnected, the serial link being restored route after putting the ferry (4) in the "absorption" mode. Method for purging buffers from high serial links flow according to any one of claims 1 to 4 characterized in that specific write requests consist of write requests partial with a null mask in order not to modify the state of the machine during purge. Method for purging buffers from high serial links flow according to any one of claims 1 to 5 characterized in that the ferry (4) transfers data in 4K increments bytes maximum and stores block information in registers of data transferred in progress and the next block of data to be transferred to allow resumption of data transfer to the point where it was before the failure. Method for purging buffers from high serial links flow according to any one of claims 1 to 6 characterized in that when the step of comparing the responses received, comprising a barrier marker with the specific requests generated, leads to the recognition that the purging of all the channels (400, 401) has been completed, the ferry is returned to normal operating mode in which it uses the channels (400, 401) connecting it to a memory (12a, 12c) cyclically, with interlacing. Method for purging buffers from high serial links flow according to any one of claims 1 to 7 characterized in that it is used following a link failure such as a disturbance after restarting or resetting the serial link and before restarting the current application at the last recovery point, without resetting the entire system. Method for purging buffers from high serial links flow according to any one of claims 1 to 7 characterized in that it is used for the self-test by scanning the network subset memory interconnection to the ferry (4), the location of possible failures allowing reconfiguration of the link in a mode degraded ignoring the faulty channel (s) (400, 401). Method for purging buffers from high serial links flow according to any one of claims 1 to 9 characterized in that each bidirectional channel (400, respectively 401) of the serial link is consisting of two unidirectional cables (1400A, 1400B), the data transit directions are opposite. Device for implementing the method of purging the buffers of high speed serial links according to any one of claims 1 to 7, the high speed serial links being used by a circuit (4) ferry (MOVER) realizing data movement operations, namely reads and writes, between at least two memories (12a, 12c), the transporter (MOVER) being connected to each memory by at least two bidirectional channels (400, 401), the operations of data movements each consisting of a movement request followed by return of a response, or acknowledgment of the request, the ferry using the channels (400, 401) connecting it to a memory (12a, 12c) cyclically with interleaving, for the same operation, each section of track preserving the order of emission of the requests, respectively the responses, of the same train of requests, respectively of the same train of response s, the responses using the same channel (400, 401) as the requests for which they constitute acquittal, characterized in that it comprises: means for placing the ferry (4) in a so-called "absorption" operating mode in which the responses are accepted independently of any order of arrival on the different tracks (400, 401) and are ignored by the ferry (4 ), means for generating a specific write request and a specific read request in each of the channels of the serial link, the specific requests having no effect on the memories and means for generating in these requests a so-called marker of "barrier" contained in a control character preceding and / or following the request, means for generating a barrier marker in a control character associated with the corresponding response of each specific request, means for accumulating the responses received comprising a barrier marker, and means for comparing the responses received comprising a barrier marker with the specific requests generated to allow either the location of a possible breakdown in the case of the expected responses comprising a barrier marker are missing, or the recognition that the purging of the set of routes has been performed in the event that all expected responses with a barrier marker have been received. Device for purging buffers (buffer) from serial links to broadband according to claim 11 characterized in that it comprises means (11) for comparing the number of responses received with a marker barrier with the number of specific requests generated. Device for purging buffers (buffer) from serial links to broadband according to claim 11 or 12 characterized in that it comprises means for generating information regarding the emission source and the paths taken by the requests, respectively by the responses in the control character (s) associated with the requests, respectively in response, the purge device comprising means for reading the information in these response control characters with barrier marker for emission source and paths borrowed, to allow the localization of possible breakdowns of the serial link. Device for purging buffers (buffer) from serial links to broadband according to any one of claims 11 to 13 characterized in what it includes means (11) for processing data ensuring the reset the serial link followed by putting the ferry (1) in the so-called "absorption" operating mode. Device for purging buffers (buffer) from serial links to broadband according to claim 14 characterized in that the means (11) of data processing ensure the generation of specific requests writing and reading, responses with barrier marker to specific requests being taken into account by these same means (11) of data processing. Device for purging buffers (buffer) from serial links to broadband according to claim 15 characterized in that the means (11) of data processing include at least one accumulation register, each bit is representative of the generation of a specific request, each response with barrier marker received by the means (11) of processing causing the writing of a so-called "barrier" bit in the register of cumulative to allow comparison of the number of responses received with barrier marker with the number of specific requests generated. Device for purging buffers (buffer) from serial links to broadband according to claim 15 or 16 characterized in that the means data processing (11) include timing means allowing the generation of a fault detection message in the case an expected response with barrier marker is missing after a specified period of time.

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