Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/30—Peripheral units, e.g. input or output ports
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/20—Support for services
  • H04L49/205—Quality of Service based
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/30—Peripheral units, e.g. input or output ports
  • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/50—Overload detection or protection within a single switching element
  • H04L49/501—Overload detection
  • H04L49/503—Policing
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5629—Admission control
  • H04L2012/5631—Resource management and allocation
  • H04L2012/5632—Bandwidth allocation
  • H04L2012/5635—Backpressure, e.g. for ABR
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5629—Admission control
  • H04L2012/5631—Resource management and allocation
  • H04L2012/5636—Monitoring or policing, e.g. compliance with allocated rate, corrective actions
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
  • H04L2012/5679—Arbitration or scheduling
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/15—Interconnection of switching modules
  • H04L49/1515—Non-blocking multistage, e.g. Clos
  • H04L49/1523—Parallel switch fabric planes
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/50—Overload detection or protection within a single switching element
  • H04L49/505—Corrective measures
  • H04L49/508—Head of Line Blocking Avoidance

Definitions

• the invention relates to an asynchronous transfer mode (ATM) network switch. More particularly, the invention relates to an ATM switch having cell buffers for each available bit rate (ABR) virtual connection (VC) and means for outputting cells which conforms to a minimum cell rate (MCR) for each ABR VC and which fairly allocates bandwidth to all VCs on the switch.
• ATM asynchronous transfer mode
• cells of data conventionally comprising fifty-three bytes (forty-eight bytes carrying data and the remaining five bytes defining the cell header, the address and related information) pass through the network on a virtual connection at an agreed upon rate related to the available bandwidth and the level or service paid for.
• the agreed upon rate will relate not only to the steady average flow of data, but will also limit the peak flow rates.
• the network will include, for example at the boundary between different networks, means for policing the flow.
• the flow policing means typically includes a "leaky bucket" device which assesses the peak and average flow rates of cells on a VC and if required either downgrades the cells' priority or discards cells.
• traffic shaping Since policing can result in the discarding of cells which should not be discarded, it is desirable to effect "traffic shaping" to space out the cells on a VC sufficiently so as to ensure that they meet the agreed upon rates, and in particular the peak rates.
• traffic shaping is that it is desirable to delay the transmission of cells by variable amounts in an attempt to avoid cell loss. In practice, however, variable cell delay has been difficult to implement.
• Co-owned International Application Number PCT/US96/05606 discloses an ATM switch with a traffic shaping mechanism which delays the transmission of incoming cells by varying amounts of time and which accounts for both peak and average cell flow rates.
• the traffic shaping mechanism broadly comprises means for determining for each cell received an onward transmission time dependent upon the time interval between the arrival of the cell and the time of arrival of the preceding cell on the same VC, buffer means for storing each new cell at an address corresponding to the onward transmission time, and means for outputting cells from the buffer means at a time corresponding to the address thereof.
• the traffic shaping mechanism results in cells being output at a rate which is related to the rate at which they are received which eliminates or minimizes bunching.
• CBR constant bit rate
• VBR variable bit rate
• ABR available bit rate
• PCT/US96/15737 discloses an ATM switch which includes a plurality of slot controllers each having at least one external network link and a link to a switch fabric, the slot controllers receiving ATM cells from the network and transmitting cells to other slot controllers via the switch fabric and receiving cells from the switch fabric and transmitting cells onto the network.
• Each slot controller is provided with a plurality of FIFO buffers, one cell FIFO for each VC established on the switch and one arbitration FIFO for each priority level, and a FIFO controller.
• the cell header is examined to determine the VCl and the priority level.
• the slot controller examines the switch fabric to find a path for the VC, selects a VC FIFO for the VC, pushes the cell into the VC FIFO, increments a counter for the VC FIFO, and, if the VC FIFO was previously empty, writes a pointer to the arbitration FIFO for the priority level of the cell FIFO.
• the arbitration FIFOs are examined according to a schedule and cells are popped from VC FIFOs according to priority for exit from the slot controller.
• the highest priority arbitration FIFO is always examined first and none of the lower priority arbitration FIFOs are examined unless the highest priority arbitration FIFO is empty.
• timers are set for the lower priority arbitration FIFOs and if a timer expires for a lower priority arbitration FIFO, it is examined regardless of the contents of the highest priority arbitration FIFO.
• the slot controllers are coupled to two switch fabrics and two sets of arbitration FIFOs are used, one set for each switch fabric.
• the switch fabric Prior to popping a cell from a FIFO into the switch fabric, the switch fabric is examined to determine if the path is broken and whether an alternate path exists through the second switch fabric. If an alternate path is available, the cell is not sent, but the pointer for the VC FIFO is pushed into the corresponding arbitration FIFO for the second switch fabric.
• the system described provides efficient handling of all priority levels, but is not specifically mindful of the needs of ABR traffic.
• ABR service is intended to make the best use of any remaining available bandwidth in an ATM switch after providing for the higher priority services.
• ABR service is suitable for data transmission which is not time sensitive, but which may be cell loss sensitive.
• ABR service is generally implemented by buffering data at the ingress of an ATM switch and releasing the data from the buffer into the switch core only when some available bandwidth is not being used by a higher priority connection.
• cell rate a rate which does not cause the buffer to overflow.
• Rm cells are sent from the source through the destination and return to the source with information about the congestion level in the ATM switches which form the ABR VC between the source and the destination. The source is then able to modify its transmission cell rate to avoid cell loss due to congestion.
• Rm cells include fields for indicating the current cell rate (CCR) , the minimum cell rate (MCR) , and the explicit rate (ER) .
• CCR is the rate at which the source is presently transmitting ATM cells.
• MCR is a rate which is established at the time the VC is set up and indicates the minimum rate at which the source may always transmit cells without cell loss.
• the ER is the new rate to which the source should adjust cell transmission due to the level of congestion in the switches which form the ABR VC.
• the ER is set by the switches which form the ABR VC and may be a rate which is higher than or lower than the CCR. However, the ER may not be set lower than the MCR.
• Various algorithms are utilized in ATM switches to set the ER for an ABR VC.
• an ATM switch includes a plurality of slot controllers each having at least one external network link and a link to a switch fabric, the slot controllers receiving ATM cells from the network and transmitting cells to other slot controllers via the switch fabric and receiving cells from the switch fabric and transmitting cells onto the network.
• Each slot controller is provided with an input cell processor, an output cell processor, and a plurality of FIFO buffers, one cell FIFO for each VC established on the switch, one arbitration FIFO for each priority level, and a traffic shaping FIFO.
• the traffic shaping FIFO is preferably configured as a leaky bucket and is provided with a look-up table for storing the MCRs of the ABR VCs.
• the cell header is examined to determine the VCl and the priority level.
• the slot controller examines the switch fabric to find a path for the VC, selects a VC FIFO for the VC, pushes the cell into the VC FIFO, increments a counter for the VC FIFO, and, if the VC FIFO was previously empty, writes a pointer to the arbitration FIFO for the priority level of the cell FIFO.
• the arbitration FIFOs are examined according to a schedule and cells are popped from VC FIFOs according to priority for exit from the slot controller as described in co-owned International Application Number PCT/US96/15737.
• an onward transmission time for each ABR cell is calculated according to the methods described in co-owned International Application Number PCT/US96/05606 and address pointers to ABR cells are stored in the traffic shaping FIFO as well as in an arbitration FIFO.
• the input cell processor monitors the peak cell flow rate for each ABR VC on the switch according to a leaky bucket process and determines for each cell whether the peak cell flow rate has been exceeded. If the peak rate has been exceeded, such that the leaky bucket overflows, the amount of overflow is added to the current time as the address for the cell in the VC FIFO so that the onward transmission of the cell is delayed by the amount of the overflow.
• the ABR cells are thus output from the VC FIFOs in the order of time slots stored in the traffic shaping FIFO.
• the cell processor monitors the output bandwidth of all ABR traffic and calculates an average over a predetermined period of time.
• the output bandwidth per ABR VC, the output cell rate (OCR) is determined by dividing the average output bandwidth of all ABR traffic by the number of pointers in the traffic shaping FIFO.
• OCR output cell rate
• the pointer from the traffic shaping FIFO is discarded and the cell is output according to the arbitration FIFO scheduling, i.e. the cell is temporarily left in the VC FIFO. If the OCR is less than the MCR, the pointer from the traffic shaping FIFO is used immediately to output a cell from the appropriate VC FIFO. When pointers from arbitration FIFOs are used, the OCR is also compared to the MCR. If the OCR is greater than the MCR, the pointer is used to .output the cell and the pointer is pushed back to the bottom of the arbitration FIFO. If the OCR is less than the MCR, the cell is left in the VC FIFO.
• an ER value is set at or just below the OCR and is signalled back to the source for each ABR VC.
• the ER for individual ABR VCs may be fine tuned according to the factor VCcount ⁇
• MAXcount is the number of cells in a particular VC FIFO and MAXcount is a configurable parameter for each particular ABR VC.
• FIG. 1 is a high level schematic diagram of an ATM switch according to the invention.
• Figure 2 is a high level schematic diagram of a slot controller according to a first embodiment of the invention
• Figure 3 is a high level schematic diagram of a cell buffering system according to one embodiment of the invention
• Figure 4 is a schematic flow chart of how all cells entering the buffering system are handled
• Figure 5 is a schematic flow chart of how ABR cells entering the buffering system are handled
• Figure 6 is a schematic flow chart of how all cells exiting the buffering system are handled.
• Figure 7 is a schematic flow chart of how ABR cells exiting the buffering system are handled.
• an ATM switch 10 includes a plurality of controllers (which are often called “slot controllers” or “link controllers”) 12a-12g and two dynamic crosspoint switch fabrics 14, 14' .
• Each slot controller has at least one external link l ⁇ a-16h to an ATM network (not shown), an input link 18a-18h to the switch fabric 14, an output link 20a-20h from the switch fabric 14, an input link 18'a-18'h to the switch fabric 14', and an output link 20'a-20'h from the switch fabric 14 ' .
• This general arrangement is described in co- owned UK Patent Application No. 9507454.8 and UK Patent Application No. 9505358.3 which are hereby incorporated by reference herein in their entireties.
• each slot controller 12 has an input cell processor 22, an output cell processor 24, and a cell buffering system 26.
• the cell buffering system 26 is coupled to the input cell processor 22 for buffering cells received from the ATM network before they pass through the switch 10.
• the output cell processor 24 is conventional and handles such functions as writing cell headers with new VPI/VCI information before passing cells onto the network.
• the input cell processor 22 is unconventional in that it controls the buffering system 26 in addition to other conventional functions such as reading cell headers and routing cells through the switch fabric to another slot controller.
• the buffering system 26 generally includes a plurality of VC FIFOs 30a, 30b, 30c, ..., 30n , a plurality of priority level arbitration FIFOs 32a-32d, 32'a-32'd, a traffic shaping FIFO 34, and an MCR look-up table 36.
• the FIFOs are coupled to the input cell processor and controlled by the input cell processor as described below with reference to Figures 4 and 5.
• the VC FIFOs are not individual hardware components but are rather dynamically configured in RAM as needed. The number of FIFOs created depends on the number of VCs being handled by the particular slot controller.
• each VC FIFO would be a 64K FIFO, although FIFOs of different sizes could be used depending on the number of cells expected for a particular VC.
• the arbitration FIFOs are preferably also dynamically configured in RAM. The number of arbitration FIFOs corresponds to the number of priority levels for VCs through the switch. As shown in Figure 3, there are four arbitration FIFOs representing the current ATM priority levels of "0" through "3" ("0" being the highest priority and "3" being ABR) .
• a separate set of arbitration FIFOs is used for each switch fabric.
• FIFOs 32a-32d would be used for switch fabric 14 ( Figure 1) and FIFOs 32'a-32'd would be used for switch fabric 14' .
• the traffic shaping FIFO 34 and the MCR look-up table 36 are also preferably dynamically configured in RAM. The size of the traffic shaping FIFO and the MCR look-up table is related to the number of ABR VCs being handled by a particular slot controller and the MCR for each ABR VC.
• the header is examined at 50 and the VCl and priority level are determined at 52. If it is determined at 53 that the cell is an ABR cell, leaky bucket processing is performed at 55 (described in more detail below with reference to Figure 5) and the next cell is then examined at 50. If the cell is not an ABR cell, the cell processor inspects the switch fabric at 54 to determine whether a path is available for the VC. If, at 56, it is determined that no path exists for the VC, the cell is discarded at 58.
• the cell processor pushes the cell into VC FIFO(n), where "n" represents the VC, and increments a cell counter for VC FIFO(n) at 60. If it is determined at 62 that the cell count for VC FIFO (n) is "1", i.e. that the FIFO was previously empty, a pointer pointing to VC FIFO(n) is written and pushed at 64 into the appropriate arbitration FIFO depending on the priority level of the cell which was determined at 52. The cell processor then returns to 50 to examine the next cell received from the network. If it is determined at 62 that the VC FIFO was not previously empty, no pointer is written and the cell processor returns to 50 to examine the next cell received from the network. This process is repeated for each cell received by the input cell processor and new VC FIFOs are created as needed for new VCs. Similarly, empty VC FIFOs are released from RAM so that RAM is made available for new VC FIFOs.
• the leaky bucket processing begins at 150 as shown in Figure 5.
• the leaky bucket processor times the arrival of each ABR cell and calculates the time difference between the arrival of cells for each VC. Each time difference is compared to a stored bucket level and bucket increment and the bucket level and bucket increment are adjusted accordingly. A stored maximum bucket level is then subtracted from the adjusted bucket level to provide a current overflow level.
• the peak rate has not been exceeded and the processing of the cell continues at 154 in Figure 5.
• the cell is pushed into the appropriate VC FIFO and a pointer to the cell is pushed into the traffic shaping buffer at 154.
• the switch fabric is examiner to determine whether a path is available and the cell is discarded if there is no available path.
• the pointer pushed into the traffic shaping buffer includes the onward transmission time for the cell. If, on the other hand, it is determined at 152 that the peak rate has been exceeded, the overflow value is added to the onward transmission time at 156 before the cell is buffered and the pointer is written at 154.
• the pointer will include the sum of the onward transmission time plus the overflow value.
• the cell is then treated like all other cells so that a pointer is placed in the arbitration buffer at 160 if it is determined at 158 that this is the first cell entering the buffer.
• the leaky bucket processing of incoming cells then returns at 162 to examine the next cell at 50 in Figure 4.
• two leaky bucket processors are operated in parallel, one for monitoring peak flow rates and the other for monitoring average flow rates. Overflow values from the two buckets are compared and the greater of the two values is used to increment the time pointer for the ABR cell.
• the cell processor outputs cells to the switch fabric from the VC FIFOs according to a selected procedure.
• Figures 6 and 7 show a presently preferred procedure with optional portions shown in phantom lines and phantom line boxes.
• the arbitration FIFOs are examined to determine whether they contain pointers to VC FIFOs.
• the highest priority FIFO(0) is always examined first at 72. If the FIFO is not empty, the top pointer in the FIFO is popped at 74. At 76, the VC FIFO to which the pointer points is popped and the cell count for the VC FIFO is decremented. If it is determined at 78 that the cell count of the VC FIFO is zero, the procedure returns to the start 70 and examines the arbitration FIFO(0) again at 72.
• the pointer to the VC FIFO is pushed back into the arbitration FIFO(0) at 80 and the procedure then returns to start 70 and examines the arbitration FIFO(0) again at 72.
• none of the other arbitration FIFOs are examined until the FIFO (0) is empty as determined at 72. If it is determined at 72 that the arbitration FIFO(O) is empty, the procedure goes to 82 and examines the contents of arbitration FIFO(l) .
• the procedure returns to the start at 70. Only if it is determined at 82 that the arbitration FIFO(l) is empty, will the procedure go to 92 to examine the contents of arbitration FIFO (2) . If, at 82, it is determined that the arbitration FIFO(l) is empty, the procedure described above is repeated at 92-100 with respect to the arbitration FIFO (2) .
• the above simplified embodiment of the invention may be enhanced by setting a timer for each of the three lower level arbitration FIFOs.
• timers are examined at 112-116 before examining the arbitration FIFO(0) .
• the timer for arbitration FIF0(1) is examined at 112 and if it has expired the procedure goes to 82 where the arbitration FIFO(l) is examined as described above.
• the timer for arbitration FIF0(1) is reset at 118 before the procedure returns to start at 70.
• the timer for arbitration FIFO (2) is examined at 114 and if it has expired the procedure goes to 92 where the arbitration FIFO (2) is examined as described above. In addition, the timer for arbitration FIFO(2) is reset at 120 before the procedure returns to start at 70. If the timer for arbitration FIFO (2) has not expired as determined at 114, the timer for arbitration FIFO (3) is examined at 116 and if it has expired the procedure goes to 102 where the arbitration FIFO (3) is examined as described above. In addition, the timer for arbitration FIFO(3) is reset at 122 before the procedure returns to start at 70. In this embodiment, the decisions at 82, 92, and 102 may be modified such that upon determining that an arbitration FIFO is empty, the procedure returns to start, rather than to examine the next arbitration FIFO.
• the procedure may be further enhanced by testing whether paths through the switch fabric have broken. For example, after the VC pointer is popped at 74, but before the cell is popped from the VC FIFO into the switch, the cell processor determines at 124 if the switch fabric path for this VC is broken. If it is, the cell processor determines at 126 whether an alternate path is available through the second switch fabric. If an alternative path is available, the cell processor pushes the pointer at 128 into the appropriate arbitration FIFO for the second switch fabric and then returns to start at 70. If the path is broken and no alternative path is available, the cell is discarded at 130. It will be appreciated that this testing of the switch fabric may be implemented for each arbitration FIFO.
• routines at 82-90, 92-100, and 102-110 would be modified to include the same steps as described with reference to 124-130.
• pointers stored in the arbitration FIFOs preferably include information for output port number, switch fabric preference, and priority, in addition to the VC information.
• the arbitration of the buffering system can be further enhanced to deal with "blocked ports".
• another arbitration FIFO is created for pointers to VCs having blocked ports.
• the blocked port arbitration FIFO is then given the highest priority. Since the presence of a single blocked port could, under this system, prevent all cells from being transmitted until a particular port becomes un-blocked, the pointers in the blocked port arbitration FIFO are preferably recycled each time a pointer encounters a blocked port . In other words, when a pointer is popped from a blocked port arbitration FIFO, the pointer is pushed back to the bottom of the FIFO if it points to a VC which continues to have a blocked port.
• a separate blocked port FIFO is provided for each priority arbitration FIFO so that the blocked ports are also dealt with according to priority level.
• the leaky bucket processing according to the invention monitors the ABR traffic through the switch and makes certain adjustments to the flow of ABR traffic as illustrated in Figure 7.
• the cell processor monitors the output bandwidth for all ABR traffic over time and determines an average value periodically at 200.
• the MCR for the VC corresponding to the pointer is looked up in the look-up table. It will be recalled that pointers are popped from the traffic shaping FIFO according to the time stamp contained in the pointers which were assigned as described herein above with reference to Figure 5.
• the cell processor divides the current average output bandwidth by the number of pointers remaining in the traffic shaping buffer in order to determine an output cell rate (OCR) per ABR VC.
• OCR output cell rate
• the OCR is compared to the MCR at 206 and if the OCR is greater than the MCR for this particular VC, the pointer is discarded and the forwarding of cells for this VC is left to be accomplished by the arbitration buffer as described above with reference to Figure 6. If, on the other hand, the OCR is not greater than the MCR, the cell pointed to by the pointer is popped from the VC FIFO and the cell count for the VC FIFO is decremented at 210 before the pointer is discarded at 208.
• the output bandwidth available for ABR traffic is allocated fairly among ABR VCs with due consideration being given to the MCR for each VC.
• the calculated OCR can be used to provide a new ER which is signalled back to the source for each ABR VC handled by the switch.
• the ER is set equal to or slightly below the OCR with a lower threshold being provided so that the FIFO does not empty.
• the ER for each VC may be customized based on the number of cells in the FIFO for each VC according to formula (1) given below where VCcount is the number of cells in a particular VC FIFO and MAXcount is a configurable parameter for each particular ABR VC.
• the ER will be reduced as the number of cells in the VC FIFO increases.
• the ABR traffic shaping has been disclosed in conjunction with a particular priority buffering system, the ABR traffic shaping may be used alone or in conjunction with other buffering schemes Moreover, while particular configurations have been disclosed in reference to the operations of the input and output cell processors, it will be appreciated that other configurations could be used as well. For example, the management of the arbitration, traffic shaping, and VC FIFOs could be accomplished at either the input cell processor or the output cell processor or by a separate processor and not delegated to the input and/or output cell processors. Furthermore, while the ATM switch has been disclosed as having eight slot controllers and the slot controllers have been shown with eight data links, it will be understood that different numbers of slot controllers and data links can be used.

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• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Quality & Reliability (AREA)
• Data Exchanges In Wide-Area Networks (AREA)

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• 1995
  • 1995-11-29 GB GB9524398A patent/GB2307823B/en not_active Expired - Fee Related
• 1996
  • 1996-11-27 EP EP96943690A patent/EP0872091A1/de not_active Withdrawn
  • 1996-11-27 WO PCT/US1996/019720 patent/WO1997020415A1/en not_active Application Discontinuation
  • 1996-11-27 CA CA002238713A patent/CA2238713A1/en not_active Abandoned

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