Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
  • H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
  • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
  • H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
  • H03D3/008—Compensating DC offsets
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
  • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
  • H03D7/16—Multiple-frequency-changing
  • H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
  • H03D7/166—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature using two or more quadrature frequency translation stages
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/06—Receivers
  • H04B1/16—Circuits
  • H04B1/26—Circuits for superheterodyne receivers

Definitions

• This invention relates generally to RF receivers and, more particularly, to a highly integrated universal direct conversion receiver for receiving RF signals modulated by any of various analog and digital techniques.
• Superheterodyne RF receivers which operate by mixing an incoming RF signal with a local oscillator (LO) signal are known.
• the output of the mixer is an intermediate frequency (IF) signal which is filtered at IF with the use of passive bandpass filters in order to select a particular channel (i.e., frequency) of interest.
• IF intermediate frequency
• Such filters generally consist of a resonant element in which the physical properties of the material determine filter characteristics, including filter size. Use of such passive bandpass filters in superheterodyne receivers has precluded size reduction and integration of such receivers.
• zero IF receiver which, like the superhederodyne receiver, down converts received RF signals.
• zero IF receivers instead of down converting to some IF frequency in the manner of a super ⁇ heterodyne receiver, zero IF receivers down convert to zero IF (i.e., to the modulating frequency, by removing the carrier frequency) .
• zero IF receivers While down conversion to zero IF advantageously permits the use of active filters for purposes of channel selection, zero IF receivers have not been practical to implement due to the inherent DC offsets which result from the introduction of significant gain at zero IF.
• the advent of superheterodyne receivers coincided with the use of analog modulation techniques for RF transmission, such as amplitude modulation (AM) and frequency modulation (FM) techniques.
• AM amplitude modulation
• FM frequency modulation
• CDMA Code Division Multiple Access
• NADC North American Digital Cellular
• GSM pan-European digital cellular radio
• Japan has adopted a variation of the NADC IS-54 standard entitled the Personal Digital Cellular (PDC) RCR-27 standard.
• a highly integrated universal RF receiver capable of processing RF signal modulated by various analog and digital modulation techniques is described.
• the receiver includes a down converter for converting received RF signals to in- phase and quadrature zero IF signals (i.e., baseband signals at the frequency of the modulating signal with the carrier frequency removed) .
• Active channel selection filters pass signals within a desired frequency band and an up converter converts the zero IF signals to an IF signal.
• Channel selection filtering at zero IF permits the use of readily integratable active filters for this purpose, enabling the receiver to be implemented on one or two application specific integrated circuits (ASICs) .
• ASICs application specific integrated circuits
• the amplified IF signal is quantized by a Period-to- Digital (P/D) converter which provides a count value signal to a signal processor.
• P/D Period-to- Digital
• the P/D converter is capable of quantizing signals that contain information in the form of phase or frequency modulation (i.e. , constant envelope modulation) .
• phase or frequency modulation i.e. , constant envelope modulation
• signal information is contained in the zero crossings.
• the count value signal is representative of the period between consecutive zero crossings of the IF signal and thus, is also representative of the instantaneous frequency of the modulated signal.
• the P/D converter advantageously uses digital only construction, has low gate complexity and can be fabricated by any of a variety of semiconductor processes.
• a phase comparator compares the amplified IF signal to a reference voltage in order to provide a signal containing zero crossing information to the P/D converter.
• the phase comparator also serves to amplitude limit the IF signal, thereby eliminating performance degradation due to amplitude fading and the need to otherwise compensate for amplitude fading. Amplitude limiting in this manner is possible due to the use of the P/D converter for equalization, since the P/D converter relies on zero crossing information, as opposed to amplitude information.
• the signal processor demodulates the count value signal provided by the P/D converter. Additional functionality of the signal processor includes intersymbol interference (ISI) equalization and additionally, in mobile receiver applications, time dispersion equalization. Clock recovery may also be performed by the signal processor.
• the signal processor is a digital signal processor (DSP) .
• DSP digital signal processor
• the receiver is compatible with various modulation standards, both analog and digital. In particular, different modulation standards are accommodated by modifying the bandwidth of an RF input bandpass filter of the receiver, the down converter LO frequency, the IF frequency to which the zero IF signal is up converted and the demodulation technique employed by the signal processor.
• Fig. 1 is a block diagram of a universal RF receiver in accordance with the invention
• Fig. 2 is a detailed block diagram of the receiver of Fig. 1;
• Fig. 3 is a block diagram of the P/D converter of Fig.
• Fig. 4 is a schematic of a first portion of the RF/analog circuitry of the receiver of Fig. 2;
• Fig. 5 is a schematic of a second portion of the RF/analog circuitry of the receiver of Fig. 2;
• Fig. 6 is a schematic of a third portion of the RF/analog circuitry of the receiver of Fig. 2;
• Fig. 7 is a schematic of a fourth portion of the RF/analog circuitry of the receiver of Fig. 2;
• Figs. 8 and 8A are a schematic of the digital portion of the receiver of Fig. 2;
• Fig. 9 is a graph illustrating peak-to-peak signal levels over the receiver's dynamic range
• Fig. 10 is a functional block diagram of an embodiment of the a signal processor for use in non-mobile receiver applications
• Fig. 11 is a flow diagram of the steps performed by the signal processor of Fig. 10;
• Fig. 12 is a functional block diagram of an embodiment of the signal processor for use in mobile receiver applications; and Fig. 13 is a flow diagram of the steps performed by the signal processor of Fig. 12.
• a universal RF receiver 10 includes an RF bandpass filter (BPF) 18 responsive to transmitted RF signals 16 which are received by an antenna 14.
• BPF RF bandpass filter
• the RF BPF 18 attenuates signals having frequencies outside a particular
• the filtered output signal 20 of the RF BPF 18 is coupled to a low noise amplifier (LNA) 22 which provides gain to the received signals.
• LNA low noise amplifier
• the amount of gain provided by the LNA 22 is selected to ensure a satisfactory receiver noise
• NF 15 figure
• a circuit 26 operates to down convert, filter and up
• Zero IF signals are baseband signals having the frequency of the modulating
• the I and Q zero IF signals are then filtered to select a particular channel within the frequency band of interest for reception.
• the filter is an active filter.
• the filtered I and Q zero IF signals are then
• the up conversion is achieved with an image canceling mixer (Fig. 2) .
• the resulting IF signal 28 is then processed by an IF
• LPF low pass filter
• a quantizer 34 is responsive to the IF output signal 37 of the IF amplifier 33 for generating a count value signal 38 for coupling to a signal processor 35.
• the count value signal 38 is representative of the period between consecutive zero crossings of the IF signal 37 and thus, the instantaneous frequency of the IF signal.
• the quantizer 34 is a Period-to-Digital (P/D) converter described in U.S. Patent Nos. 5,159,281, 5,239,273 and 5,272,448, which are assigned to the assignee of the subject application and incorporated herein by reference.
• the RF antenna 14 is coupled to the RF BPF 18 which filters out-of-band received signals 16.
• the frequency band of interest is between 935Mhz and 960Mhz and the RF BPF 18 has a bandwidth of 25MHz.
• One suitable type of RF BPF 18 is a duplexer, in which two filters are provided in a single resonant element.
• the filtered output signal 20 of the RF BPF 18 is coupled to the LNA 22 for amplification.
• the bandwidth of the LNA 22 is at least the same as that of the RF BPF 18.
• the output signal 24 of the LNA 22 may be coupled to an optional additional RF BPF 40 which provides additional out- of-band filtering. Use of the RF BPF 40 may be particularly advantageous in cellular applications.
• the down converter/channel selector/up converter circuit 26 includes an integrated down converter sub-circuit 52 having an automatic gain control (AGC) amplifier 48 which introduces a selectable gain, such as -3dB or 22dB of gain, to the input
• AGC automatic gain control
• the AGC amplifier 48 further serves to convert the single-ended input signal 42 to a differential output signal 50.
• the output signal 50 is coupled to an image reject mixer including an in-phase (I) mixer 54, a quadrature (Q) mixer 58, an I low pass filter (LPF) 80 and a Q LPF 90.
• Each mixer 54 and 58 receives a respective local oscillator (LO) signal 60 and 62, with the LO signal 62 being 90° out-of-phase with respect to the LO signal 60.
• LO local oscillator
• a reference clock oscillator 72 such as a crystal, generates a reference clock signal 65 having a precise frequency, such a ⁇ 13.0MHz in the illustrative GSM embodiment.
• a frequency synthesizer 64 such as a phase locked loop (PLL) and a voltage controlled oscillator, converts the reference clock signal 65 into a higher frequency LO signal 67 which is phase-locked to the reference clock signal 65.
• the LO signal 67 generated by the frequency synthesizer 64 is matched to the carrier frequency of the RF input signal 16 which, in the GSM embodiment, is between 935MHz and 960MHz.
• a circuit 68 is responsive to the LO signal 67 for generating the in-phase LO signal 60 and the quadrature LO signal 62 which are thus, phase-locked to the reference clock signal 65.
• the differential signal 50 coupled to the mixers 54, 58 is given by cos( ⁇ .t)
• the I LO signal 60 is given by cos( ⁇ 0 t)
• the Q LO signal 62 is given by cos( ⁇ 0 t -90°), where the LO frequency ⁇ 0 is equal to the carrier frequency ⁇ c .
• the output signal I(t) 78 of I mixer 54 is then given by:
• the signal I f (t) can be expressed as the zero IF signal:
• the output signal Q(t) 88 generated by the Q mixer 58 is given by:
• the Q(t) signal 88 is then filtered by the LPF 90 to generate an output signal Q f (t) 92 which contains only the frequency difference term as follows:
• the signal Q f (t) can be expressed as the zero IF signal:
• Moderate gain may be provided at zero IF in both the I and Q signal paths by respective instrumentation amplifiers 94 and 96.
• the optional additional linear gain provided by the amplifiers 94, 96 helps to establish the desired overall system NF. However, most of the system gain is not provided at zero IF in order to minimize DC offsets.
• the instrumentation amplifiers 94, 96 convert the respective differential input signals 82, 92 into single-ended output signals 98, 100, respectively. In the illustrative GSM embodiment, each of the instrumentation amplifiers 94, 96 provides a fixed 6dB of gain.
• the single-ended output signals 98, 100 of the instrumentation amplifiers 94, 96, respectively, are coupled to respective active LPFs 106, 108 which are active filters operable to pass the desired frequency spectrum (i.e., channel selection) while attenuating noise and interference outside of the desired signal bandwidth. Since channel selection and interference rejection is performed at zero IF, active LPFs 106, 108 are suitable for providing such functionality.
• active LPFs 106, 108 are readily integratable.
• each of the LPFs 106, 108 is implemented as an eight pole Bessel filter, as shown and described below in conjunction with Fig. 5.
• LPFs 106, 108 may be provided by any suitable active filter, such as switched capacitor filters.
• LPFs 106, 108 provide matched filter response for the receive channel. Additionally, any filter structure which can approximate the required gaussian filter response would suffice for LPFs 106, 108, provided they feature minimal group (phase) delay. Additional gain is introduced to the output signals 110,
• each of the amplifiers provides a gain of OdB or 20dB.
• the amplifiers 116 and 118 are additionally responsive to DC offset compensation circuitry, as indicated by respective DC offset control signals 102, 104.
• the DC offset compensation circuitry will be described in conjunction with Fig. 5 below. Suffice it to say that the DC offset circuitry serves to minimize DC offsets at the outputs of the IF amplifiers 116 and 118, such as may be caused by differential DC offsets at the outputs of the image reject mixers 54, 58.
• the output signals 126, 128 of the IF amplifiers 116, 118 are up-converted by an image canceling mixer, including an I mixer 132 and a Q mixer 134 responsive to respective LO signals 138, 140.
• a circuit 142 is responsive to a divided version 139 of the reference clock signal 65 for generating the in-phase LO signal 138 and the quadrature LO signal 140, which is 90° phase-shifted relative to the signal 138.
• the LO signals 138, 140 have a frequency which meets the Nyquist criterion for the data rate of the transmitted GSM signal or 203.125KHz, where the GSM data rate is equal to 270.833KHZ.
• the single-ended I signal 126 is given by cos ⁇ m t
• the single- ended Q signal 128 is given by cos( ⁇ m t-90°)
• the LO signal 138 is given by cos( ⁇ 0 t)
• the LO signal 140 is given by cos( ⁇ 0 t-90°)
• the output signal I p (t) 146 of mixer 132 is given by: (7)
• Equation (9) reveals that only the lower sideband signal remains, thereby converting the zero IF signals 126 and 128 into an IF signal 28 centered about the LO frequency ⁇ 0 .
• the IF signal 28 is coupled to the IF LPF 30 which passes the lowest frequency signal components and rejects the odd harmonic response.
• the LPF 30 is two cascaded six pole Butterworth filters (Figs. 6 and 7) , but may alternatively be implemented with any suitable filter.
• the output signal 32 of the LPF 30 is coupled to the IF amplifier 33 which introduces additional gain to the IF signal 32.
• Amplifier 33 introduces a selectable gain, such as OdB, lOdB or 20dB, in accordance with an AGC signal 182.
• Amplifier 33 additionally implements a DC offset correction feature to minimize DC offsets introduced prior to the amplifier inputs in response to a DC offset control signal
• the output signal 37 of the amplifier 33 is coupled to a phase comparator 250 and to a Received Signal Strength Indicator (RSSI) circuit 38.
• the phase comparator 250 configured as a zero crossing detector has a non-inverting input responsive to the output signal 37 of the IF amplifier 33 and an inverting input receiving a reference voltage, such as 2.5 volts.
• the phase comparator 250 provides a pair of output signals 252, 254 indicative of the zero crossings of the IF signal 37 and which are inverted versions of one another.
• the phase comparator output signals 252 and 254 are hard amplitude limited pulse trains having transitions at the zero crossings of the IF signal 37.
• the hard amplitude limiting of the output signals 252 and 254 reduces amplitude flat fading of the received RF signals, a phenomena which can occur as a mobile receiver moves.
• amplitude limiting is not possible; rather, complex equalization techniques have been employed to address amplitude fading.
• the quantizer 34 determines the instantaneous frequency of the IF signal, thereby enabling the advantageous technique of hard amplitude limiting to be used to address amplitude fading.
• the output signals 252 and 254 of the phase comparator 250 are coupled to the quantizer 34 which is implemented with a P/D converter 260.
• the P/D converter 260 will be described further in conjunction with Fig. 3 and is the subject of the above incorporated issued U.S. Patents. Additionally, the P/D converter 260 is described in a Numa Technologies data sheet entitled Period to Digital (P/D) Converter NT304 dated 3QTR/94, which is incorporated herein by reference.
• the P/D converter 260 integrates the signals 252, 254 with high resolution so as to provide a digital output signal 264 indicative of the instantaneous frequency of the IF signal 37. More particularly, the output of the P/D converter 260 is a sixteen bit count value signal 264 having a value equal to the number of clock cycles which occur between consecutive zero crossings of the IF signal 37. Since frequency is inversely proportional to period, the count value signal 264 can be expressed as:
• the count value signal 264 of the P/D converter 260 is equalized and demodulated by the signal processor 35, as will be described below in conjunction with Figs. 10-13.
• the output signal 37 of the IF amplifier 33 is further coupled to the RSSI circuit 38.
• the RSSI circuit 38 shown in Fig. 2 is a linear slope integrating analog-to- digital (A/D) converter, as described in a National Semiconductor Application Note 260 entitled "A 20-Bit (1 ppm) Linear Slope-Integrating A/D Converter" which is incorporated herein by reference.
• A/D converter configurations are suitable for determining received signal strength, such as the successive approximation A/D converter 282 shown in the GSM embodiment below (Figs. 8 and 8A) .
• the RSSI circuit 38 includes an RMS to DC converter 270 which converts the RMS value of the IF signal 37 to a DC signal 318 for further coupling to the inverting input of a comparator 274.
• a non-inverting input of the comparator 274 is responsive to a ramp signal 276 generated by a ramp generator 278.
• the comparator 274 compares the DC signal 318 to the ramp signal 276 and provides an output signal 278 to a control circuit 280, as shown.
• the ramp signal 276 is further coupled to a comparator 284 which compares the ramp signal to a reference signal 286.
• the reference signal 286 is selectively provided by either a reference voltage source 288 or ground in accordance with the position of a switch 290 controlled by the control circuit 280 via a control signal line 294.
• the output signal 296 of the reference comparator 284 is a reference output signal coupled to the control circuit 280, as shown.
• the control circuit 280 provides Q and ⁇ Q output signals
• a twelve bit count value signal 310 is provided by the P/D converter 306 to the signal processor 35. With these signal widths provided by the P/D converter 306, the signal processor 35 is able to calculate the RSSI as follows:
• C VIN is the count provided by the P/D converter 306 in response to the comparator output signal 278,
• C ⁇ Q is the count provided by the P/D converter 306 in response to the reference comparator output signal 296 when its inverting input is connected to ground
• C FSREF is the count provided by the P/D converter 306 in response to the reference comparator output signal 296 when its inverting input is connected to the reference voltage source 288
• K is a constant, such as IO 7 .
• the P/D converter is available in a sixteen bit output version, as in the case of the quantizer P/D converter 260, or a twelve bit output version, as in the case of the RSSI P/D converter 306.
• baseband signals are processed from the instrumentation amplifiers 94, 96 through the quantizer 34.
• This baseband processing portion of the receiver may be fabricated as an ASIC, by either a bipolar, CMOS or BiCMOS process. Although both the RF and baseband receiver portions may be integrated on a single die using a BiCMOS process, isolation considerations may render it desirable to provide separate RF and baseband devices.
• a block diagram of an illustrative P/D converter 260 is shown.
• the P/D converter is capable of quantizing signals that contain information in the form of phase or frequency modulation (i.e. , constant envelope modulation) , such as Frequency Shift Keying (FSK) , Gaussian Minimum Shift Keying (GMSK) , Binary Phase Shift Keying (BPSK) and Quadrature Phase Shift Keying (QPSK) modulation techniques.
• FSK Frequency Shift Keying
• GMSK Gaussian Minimum Shift Keying
• BPSK Binary Phase Shift Keying
• QPSK Quadrature Phase Shift Keying
• signal information is contained in the zero crossings.
• the P/D converter 260 includes a pair of gates 350, 352, each responsive to a respective one of the phase comparator output signals 252 and 254 (Fig.
• Control signals 360 and 362 are further coupled to gates 350 and 352 by a timing and control circuit 370.
• the control signals 360 and 362 operate to alternatingly enable the gates 350 and 352.
• the gates 350, 352 are coupled to respective sixteen bit counters 372, 374.
• the associated counter 372, 374 When the input signal 252, 254 to one of the gates 350, 352 is high, the associated counter 372, 374, respectively, advances one count for each cycle of the CLK signal 356.
• the counters 372 and 374 thus provide respective digital count value signals 376, 378 representative of the period of a half cycle of the IF signal 37 (Fig. 2) .
• the count value signals 376 and 378 are further coupled to respective data latches 380 and 382, as shown.
• a FIFO 390 alternatingly receives the latched count value signals from latches 380 and 382 in accordance with enabling control signals 384 and 386 which control the data latches 380 and 382, respectively.
• the output of the FIFO 390 is in the form of a sixteen bit DATA OUTPUT count value signal 264.
• An interface and control circuit 404 provides the control interface to the signal processor 35 (Fig. 2) .
• Asynchronous operation of the P/D converter 260 i ⁇ accomplished by reading the DATA OUTPUT signal 264 at a rate greater than two times the frequency of the input signals 252, 254.
• Synchronou ⁇ operation on the other hand, i ⁇ accomplished by using the ⁇ DA output signal 406 of the interface and control circuit 404.
• a low ⁇ DA signal 406 indicates the availability of data at the output of the FIFO 390.
• a RESET input signal 408 is applied upon power up in order to ensure proper initialization.
• the RESET ⁇ ignal generated by reset circuitry 450 (Fig. 8) causes the FIFO 390 and counters 372, 374 to be cleared.
• a WR input signal 410 in conjunction with a CSO signal 414 and a CS1
• An -RZ? input signal 412 in conjunction with theCSO signal 414 and the CS1 signal 418, causes the DATA OUTPUT signal 264 to change from a tri-state condition to enabled. Data is shifted out of the FIFO 390 on the falling edge of the RD signal.
• the CSO signal 414 and the CS1 signal 418 are chip select input signals. When the CSO signal 414 is low and the CS1 signal 418 is high, the ⁇ e inputs indicate that the control and data lines of the P/D converter 260 are valid and that the operation specified by the " RD andltfR inputs should be performed.
• Additional circuitry of the P/D converter 260 includes a divider 360 which is responsive to the CLK signal 356 for generating various frequency sub-multiples of the CLK signal, such as four, eight, sixteen, thirty-two and sixty-four at signal lines 392, 394, 396, 398 and 400, respectively.
• the clock signals 392-400 may be used as a clock source for other devices, such as the signal processor 35.
• Fig. 4 shows the receiver 10 from the RF input 16 through the instrumentation amplifiers 94, 96
• Fig. 5 shows the receiver 10 from the LPFs 106, 108 through the IF amplifiers 116 and 118
• Fig. 6 shows the receiver 10 from the up converting mixers 132, 134 partially through the IF LPF 30
• Fig. 7 shows the remainder of the RF/analog portion of the receiver through the IF amplifier 33.
• Figs. 8 and 8A show the digital portion 10b (Fig. 2) of the receiver.
• GMSK Gaussian Minimum Shift Keying
• SDBS ⁇ TI ⁇ SHEET (RULE 26) parameters of a GSM system are a data rate of 270.833KHZ, received signal frequencies between 935.2MHz and 959.8MHz and channel spacing of 200KHz.
• the RF input 16 is coupled to the RF BPF 18, which, in the illustrative embodiment may be of the type sold by Integrated Microwave under the part number 917745.
• the output signal 20 of the RF BPF 18 is coupled to the LNA 22 which may be of the type sold by Amplifonix under the part number AX0686.
• the optional RF BPF 40 may be coupled to the output of the LNA 22, as shown.
• DC offset compensation circuitry compensates for DC offsets at the I and Q IF amplifiers 116, 118 as well as at the IF amplifier 33.
• the DC offset compensation circuitry associated with the I and Q IF amplifiers 116, 118 operates, generally, by measuring the DC offset during intervals when RF signals 16 are not being received and using this measured DC offset to compensate for the actual DC offset occurring during operating intervals when RF signals 16 are received. More particularly, most digital modulation techniques, including GMSK, utilize Time Division Multiple Access (TDMA) by which RF energy is received in bur ⁇ t ⁇ . Because the receiver 10 is not continuously receiving RF signal ⁇ , the receiver i ⁇ "powered down" during intervals when no RF signals are received. In particular, the LNA 22 is powered down and the antenna 14 (Fig. 2) is decoupled from the receiver 10.
• TDMA Time Division Multiple Access
• a switch 36 is coupled between a reference voltage, such a ⁇ +5 volt ⁇ , and ⁇ ignal line 24 via a re ⁇ i ⁇ tor Rl, an inductor Ll, a capacitor Cl and a capacitor C3, a ⁇ shown.
• the switch 36 is responsive to an LNA control ⁇ ignal 41 provided by the digital portion 10b of the receiver (Fig ⁇ . 8 and 8A) via a connector Jl.
• the LNA control signal 41 is further coupled to a driver 66 which provides output signals 70, 74 to a switch circuit 84, as shown.
• the switch circuit 84 is operable to isolate the RF input 16 from down stream portions of the receiver 10. That is, during operating intervals when RF signals are received, the output signals 70, 74 of the driver 66 cause the switch 84 to serially connect its RFI input to its RFC output. Alternatively however, during operating intervals when RF signals are not being received, the output signals 70, 74 of the driver 66 open the switch 84 so as to decouple the RFI input from the RFC output.
• RFC is connected to RF2 in order to terminate the impedance matching network comprising C150, L3 and L6 into a 50 ohm terminating impedance connected to RF2 output, thereby decoupling the RF input 16 from down ⁇ tream portions of the receiver 10.
• the RFC output of the switch 84 is coupled to the down conver ⁇ ion sub-circuit 52 (Fig. 2) .
• the RFC output is coupled to an R ⁇ F input of ⁇ ub-circuit 52.
• the ⁇ ub-circuit 52 include ⁇ the AGC amplifier 48, the I and Q down conver ⁇ ion mixer ⁇ 54 and 58, and the I and Q LPF ⁇ 80 and 90, re ⁇ pectively.
• the outputs of the sub-circuit 52 are two pairs of differential signal lines 82 and 92, a ⁇ ⁇ hown.
• Signal 82 provides the differential I output of the sub-circuit 52
• ⁇ ignal 92 provides the differential Q output of the sub-circuit 52.
• the down conversion sub ⁇ circuit 52 is of the type sold by Temic Telefunken Semiconductors under the part number U2791B and described in a Temic data sheet entitled 1000MHz Quadrature Demodulator U2791B, dated 08.06.1995 and incorporated herein by reference.
• the down conversion sub-circuit 52 is additionally respon ⁇ ive to AGC ⁇ ignal 49 for causing the internal AGC amplifier 48 to selectively introduce -3dB or 22dB of gain.
• the AGC ⁇ ignal 49 labelled GCO, i ⁇ provided by the signal proces ⁇ or 35 (Fig. 8A) .
• the GCO ⁇ ignal controls a switch Ql such that, when the GCO signal is high, the GC pin of the sub-circuit 52 at the collector of switch Ql is pulled low, causing 22dB of gain to be introduced by the internal AGC amplifier 48.
• the GCO ⁇ ignal is low on the other hand, the GC pin of the sub-circuit 52 is high, causing -3dB of gain to be introduced by the AGC amplifier 48.
• the receiver 10 is equally operable in the case of continuous modulation technique ⁇ , whereby RF signals are continuously received by the receiver 10.
• the DC offset correction provided by the DC offset circuitry described herein may be enhanced by including optional capacitors C73, C74, C120 and C125.
• the AC coupling provided by these capacitors blocks any DC off ⁇ et at the outputs of the down conversion mixers 54, 58 within ⁇ ub-circuit 52.
• capacitor ⁇ C73, C74, C120 and C125 in di ⁇ continuou ⁇ receiver applications may be detrimental to the DC offset, since the resulting RF level shifts generate a DC component which is subject to integration by the capacitors, thereby aggravating any DC offset introduced by the mixer ⁇ . Thu ⁇ , in di ⁇ continuou ⁇ receiver applications, capacitor C73, C74, C120 and C125 are jumpered or otherwise removed.
• the reference clock oscillator 72 provides the reference clock signal 65 (OSCOUT) having a predetermined frequency.
• the reference clock oscillator 72 is a crystal operating at 13.0MHz.
• the OSCOUT signal 65 is coupled to the frequency synthe ⁇ izer 64 converts the OSCOUT signal 65 to a signal 67 having a frequency matched to the carrier frequency. More particularly, the synthe ⁇ izer 64 i ⁇ re ⁇ ponsive to control signal ⁇ 75 via a connector 73 which set the frequency of the LO signal 67 provided by the synthe ⁇ izer.
• the control ⁇ ignal ⁇ 75 may be provided by any suitable user interface, such a ⁇ a microprocessor.
• SUS ⁇ E SHEET (RULE 26) conversion sub-circuit 52 include ⁇ the circuit 68 which provides the in-phase LO signal 60 and the quadrature LO signal 62 to the I and Q mixers, respectively.
• the OSCOUT signal 65 is coupled to the signal processor 35 (Fig. 8A) , where it is divided by sixteen to generate an 812.5KHZ LO signal 139 for use in up conversion, as will be described.
• each of the instrumentation amplifier ⁇ 94 and 96 introduce ⁇ a fixed 6dB gain.
• the matched LPF ⁇ 106, 108 (Fig. 2) are shown.
• the LPFs 106 and 108 are implemented as eight pole Bessel filters, each having four stages 106a, 106b, 106c, I06d and 108a, 108b, 108c, 108d, respectively.
• the LPFs 106 and 108 provide matched filtering for channel selection. No additional gain is introduced by the LPFs 106 and 108.
• the I and Q frequency selected output signals 110, 112 of the LPFs 106, 108, re ⁇ pectively, are coupled to the inverting input terminal ⁇ of re ⁇ pective IF amplifiers 116, 118, as shown.
• the IF amplifiers 116 and 118 have a selectable gain as ⁇ ociated therewith.
• amplifiers 116, 118 provide either OdB of gain or 20dB of gain.
• each of the amplifier ⁇ 116, 118 has a switch circuit 122, 124 coupled in feedback relationship therewith.
• Switch circuit ⁇ 122, 124 have an internal ⁇ witch between the Sl and S2 pin ⁇ .
• the AGC ⁇ ignal 120 (Fig. 2), labelled GC1, i ⁇ generated by the signal processor 35 and controls the ⁇ witche ⁇ 122, 124 in order to selectively open and close the respective internal switch between the Sl and S2 pins.
• the feedback resistor of amplifier 116 is provided by the parallel combination of resistor ⁇ R73 and R87; whereas if the GCl signal 120 causes the internal switch to open, then the feedback resistor of the amplifier 116 is provided by resi ⁇ tor R87.
• the feedback resistor of the amplifier 118 is provided by the parallel combination of resistor ⁇ R58 and R79; whereas, if the GCl signal 120 cau ⁇ e ⁇ the internal switch to open, then the feedback resistor of the amplifier 118 is provided by resistor R79.
• each of the amplifiers 116, 118 when the GCl signal is high, each of the amplifiers 116, 118 introduces 20dB of gain and, when the GCl signal i ⁇ low, each of the amplifier ⁇ 116, 118 introduce ⁇ OdB of gain.
• the DC offset compensation circuitry associated with IF amplifiers 116 and 118 is operable to measure the DC offset as ⁇ ociated with feeding a ⁇ ignal through the receiver 10. This is achieved by feeding a signal through I and Q inverting operational amplifiers 130, 136 and applying the output of such amplifiers to the non-inverting input of respective sample and hold circuits 150, 152.
• a ⁇ ample and hold control ⁇ ignal 151 generated by the ⁇ ignal proce ⁇ sor Fig.
• the output ⁇ ignal ⁇ 153, 155 of the sample and hold circuits 150, 152 are coupled to the non-inverting inputs of the IF amplifiers 116, 118, respectively, as shown.
• the output signals 126 and 128 of the I and Q IF amplifiers 116 and 118 are coupled to unity gain inverting amplifiers 164 and 166.
• the output signals 168 and 170 of the inverting amplifiers 164 and 166, respectively, are coupled to inputs of a quad FET switch 174, such as the type sold by Maxim under the part number MAX393.
• the quad FET switch 174 provides the up conversion mixer functionality of mixers 132, 134 (Fig. 2).
• the switch 174 includes four internal FETs (FET1, FET2, FET3 and FET4) , each having a drain coupled to a respective pin Dl, D2, D3, D4, a source coupled to a respective pin Sl, S2, S3, S4 and a gate coupled to a respective pin INI, IN2, IN3, IN4.
• the switch 174 is further responsive to the LO signal ⁇
• the LO ⁇ ignal ⁇ 138 and 140 are generated in response to an LO signal 139 from the ⁇ ignal proce ⁇ or 35 (Fig. 8A) by a flip-flop circuit 142, a ⁇ ⁇ hown.
• a flip-flop 142a divide ⁇ the ⁇ ignal 139 by four and phase-shifts the signal by 90° to provide the LO signal 140 to the Q mixer 134 (i.e., to the IN3 and IN4 inputs to switch 174) and a flip-flop 142b divides the signal 139 by four to provide the LO ⁇ ignal 138 to the I mixer 132 (i.e., to the INI and IN2 input ⁇ to ⁇ witch 174).
• the LO signal ⁇ 138, 140 have a frequency of 203.125KHZ to satisfy the minimum Nyquist frequency required for the data rate of the transmitted GSM signals.
• input signal 126 is coupled to the drain of FET1 and 90° pha ⁇ e- ⁇ hifted ⁇ ignal 168 i ⁇ coupled to the drain of FET2.
• the sources of FET1 and FET2 are externally coupled together at the Sl and S2 pins, as shown.
• the gates of FET1 and FET2 are likewise externally coupled together at the INI and IN2 pins.
• the Q channel is similarly mixed by a pair of FET switche ⁇ , FET3 and FET4, one of which, FET3, ha ⁇ a drain terminal coupled to signal 128
• FET4 has a drain terminal coupled to 90° phase-shifted signal 170.
• the sources of FET3 and FET4 are commonly connected external to the switch 174 at pins S3 and S4.
• the gate terminals of FET3 and FET4 are likewise commonly connected at the IN3 and IN4 pins, as shown.
• the I output signal 146 of the up conversion ⁇ witch 174 i ⁇ coupled to an inverting input terminal of a summing amplifier 176.
• the Q output signal 148 of the ⁇ witch 174 is likewise coupled to the inverting input of the ⁇ umming amplifier 176.
• the output ⁇ ignal 28 of the ⁇ umming amplifier 176 i ⁇ thus, the sum of the ⁇ ignal ⁇ 146 and 148 and, in particular, i ⁇ given by equation (9) above.
• the ⁇ ummed IF ⁇ ignal 28 is coupled to the LPF 30, a ⁇ shown.
• the LPF 30 is implemented with two six pole Butterworth filters, four two pole stage ⁇ of which are shown in Fig. 6 (30a, 30b, 30c and 30d) and the last two two pole ⁇ tages of which are ⁇ hown in Fig. 7 (30e and 30f) .
• Each of the operational amplifier ⁇ in the Butterworth filter 30 may be of the type ⁇ old by Linear Technologie ⁇ under the part number LT1214, for example.
• the output signal 32 of the IF LPF 30 is coupled to the IF amplifier 33 which, in the illustrative embodiment, is implemented in two stage ⁇ 33a, 33b.
• the IF amplifier ⁇ 33a and 33b are re ⁇ ponsive to a AGC signals 182 for selecting the gain to be introduced by such amplifiers.
• each of the IF amplifier ⁇ 33a and 33b provides OdB or lOdB of gain.
• the gain provided by each such amplifier stage is selected by a quad FET switch 180, of the type described above in conjunction with the up conversion mixers, in re ⁇ pon ⁇ e to control ⁇ ignal ⁇ 182.
• FET1 and FET2 control the gain of the fir ⁇ t amplifier ⁇ tage 33a.
• Control ⁇ ignal ⁇ 182 alternatingly actuate FET1 and FET2 ⁇ uch that, at any given time, one of FET1 and FET2 i ⁇ clo ⁇ ed and the other i ⁇ open.
• FET1 is on (i.e., clo ⁇ ed)
• feedback resistor R72 is connected between the inverting input and output of amplifier 33a and if FET2 is closed, then the feedback resistor R55 is connected between the inverting input and output of amplifier 33a.
• FET3 and FET4 of switch 180 control the gain of the amplifier stage 33b.
• Control signal ⁇ 182 alternatingly control FET3 and FET4 such that only one of such FETs is on at any given time.
• control ⁇ ignal ⁇ 182 are provided by signal processor generated GC2 and GC3 signal ⁇ 181 (Fig. 8A) . Specifically, when GC2 and GC3 are both low, stages 33a and 33b introduce OdB of gain and when GC2 is high and GC3 is low, each of stage ⁇ 33a and 33b introduce ⁇ lOdB of gain.
• Additional DC offset compensation circuitry is provided for the gain stage 33 by a servo amplifier 200 which compares the output signal 37 of amplifier stage 33b to a reference voltage.
• the output signal 204 of the servo amplifier 200 i ⁇ fed back to the non-inverting inputs of the amplifiers 33a and 33b, a ⁇ shown. With this arrangement, the DC offset associated with the amplifiers 33a, 33b is compensated.
• the servo amplifier 200 is of the type ⁇ old by Maxim under the part number MAX400.
• the phase comparator 250 receives the IF output signal 37 of the amplifier ⁇ tage 33b at it ⁇ non-inverting input and a reference voltage at it ⁇ inverting input, such as 2.5 volts.
• the Q and ⁇ Q output signals 252, 254 of the phase comparator 250 are indicative of the zero crossings of the IF signal 37.
• Pha ⁇ e comparator output ⁇ ignal ⁇ 252, 254 are coupled to the quantizer 34 (Fig. 8) .
• the IF signal 37 is additionally coupled to the RSSI circuit 38, a portion of which is shown in Fig. 7.
• SUBSTlTUli; SHEET E 26 particular, the IF signal 37 i ⁇ coupled to a 2X inverting amplifier 258, the output of which is coupled to the RMS to DC converter 270.
• the output signal 262 of the RMS to DC converter 270 is further proces ⁇ ed by an operational amplifier 268 which provide ⁇ an RSSI signal 310 to an A/D converter 282 (Fig. 8) .
• the digital portion 10b of the receiver 10 is shown to include the quantizer 34, RSSI circuit 38 and signal processor 35.
• the RSSI circuit includes a successive approximation A/D converter 282 of the type sold by Maxim under part number MAX153.
• the output of the A/D converter 282 is an eight bit digital signal 292 representative of the RMS amplitude of the received RF signal.
• the A/D output signal 292 is coupled to the signal proces ⁇ or 35, as shown.
• the ⁇ ignal processor 35 ⁇ elect ⁇ between the P/D converter output ⁇ ignal 264 and the A/D converter output signal 292 for receipt.
• Chip select logic 308 i ⁇ provided for thi ⁇ purpose.
• the Q output signal 252 and the ⁇ Q output signal 254 of the phase comparator 250 are coupled to the P/D converter 260.
• the CLK signal 356 coupled to the P/D converter is provided by a clock generator 420, such as the illustrated 100MHz crystal oscillator.
• the illustrated signal processor 35 is a digital signal processor (DSP)
• DSP digital signal processor
• other types of ⁇ ignal proce ⁇ or ⁇ may be ⁇ uitable, particularly for non- mobile receiver application ⁇ , as described below.
• the sixteen bit DATA OUTPUT signal 264 and the ⁇ DA signal 406 are coupled from the P/D converter 260 to the DSP 35 and the P/D converter 260 receives the CSO signal 414, the CS1 signal 418, the R ⁇ D ⁇ ignal 412, and the " WR signal 410 from the DSP
• WR , RD and DMS output ⁇ ignal ⁇ of the DSP 35 are buffered by a buffer 484 to provide the " WR , " RD and CSO input ⁇ ignal ⁇ to the P/D converter 260 which are also coupled to IfR and ⁇ RD inputs of the A/D converter 282 and to the chip select circuit 308, a ⁇ ⁇ hown.
• Al ⁇ o provided in the digital portion 10b of the receiver 10 is power up/reset circuitry 450 for the DSP 35.
• An EPROM 454 stores the code executed by the DSP 35. Upon power up, code stored in the EPROM 454 is read and executed by the DSP 35.
• a one bit latch 458 is coupled to the DSP 35.
• Al and A2 control inputs of the latch 458 receive control signal ⁇ from the DSP by which one of the eight latch output ⁇ Q0-Q7 i ⁇ selected for coupling to the latched data input signal 462.
• control signal ⁇ from the DSP by which one of the eight latch output ⁇ Q0-Q7 i ⁇ selected for coupling to the latched data input signal 462.
• only seven of the latch outputs Q0, Ql, Q2, Q3, Q4, Q6 and Q7 are used.
• latch output Q0 provides the GCO ⁇ ignal 49
• latch output Ql provide ⁇ the GCl signal 120
• latch output Q2 provides the GC2 signal
• latch output Q3 provide ⁇ the GC3 ⁇ ignal
• latch output Q4 provides the LNA control signal 41
• latch output Q6 provides the sample and hold control ⁇ ignal 151
• latch output Q7 provide ⁇ the receiver data output signal 470.
• Enable circuitry 464 provides an enable ⁇ ignal ⁇ E to the one bit latch 458.
• the GC2 and GC3 ⁇ ignals together (labelled 181) provide gain control signal ⁇ 182 (Fig. 7) for selecting the gain of amplifier stages 33a and 33b, as discu ⁇ ed above.
• a divider/clock source 480 divides the frequency of the OSCOUT signal 65 to generate the LO signal 139 for use in up conver ⁇ ion (Fig. 4) and a ⁇ econd ⁇ ignal 490 for u ⁇ e by the clock recovery circuit 488.
• the OSCOUT ⁇ ignal 65 is a 13.0MHz signal which is divided by four to generate the signal 490 at 3.25MHz and i ⁇ divided by sixteen to generate the LO signal 139 at 812.5KHZ.
• the clock recovery circuit 488 provides a recovered clock signal 482 at the data rate and in-phase with the transmitted RF signal ⁇ .
• the recovered clock ⁇ ignal 482 is coupled to DSP 35 and the flip-flop 486, as shown.
• the flip- flop 486 clocks the receiver data output signal 470 in accordance with the recovered clock signal 482 in order to provide an RXDATA signal which i ⁇ repre ⁇ entative of the recovered tran ⁇ mitted bit.
• the RSSI circuit output 292 is used by the DSP 35 to adjust the overall system gain via the AGC control signals 49, 120 and 182 (Fig. 2). More particularly, in operation, the gain stage ⁇ provided by the AGC amplifier 48, the IF amplifiers 116 and 118, and the IF amplifier 33 are sequentially "turned off” (i.e., ⁇ witched to a gain of OdB), from the rear of the receiver 10 proximal to the ⁇ ignal proce ⁇ sor 35, forward toward the antenna 14 as the received signal strength increase ⁇ .
• Curve 500 illustrates the signal level of a received RF signal.
• the other curve ⁇ 502, 504, 506, 508 and 510 represent gain at various ⁇ tage ⁇ of the receiver.
• curve 502 represents the gain at the output of the IF amplifier 33
• curve 504 represent ⁇ the gain at the outputs of the IF amplifiers 116 and 118
• curve 506 repre ⁇ ent ⁇ the gain at the output of the up converter mixer ⁇ 132, 134
• curve 508 repre ⁇ ent ⁇ the gain at the output of the down conver ⁇ ion ⁇ ub-circuit 52.
• the ⁇ tep ⁇ in each of the ⁇ e curve ⁇ represent the "turning off" of the particular gain stage a ⁇ the received signal strength increa ⁇ e ⁇ .
• Thi ⁇ operation is performed by the signal processor 35 and, specifically, by signals GCO 49, GCl 120, GC2 and GC3 181 (Fig. 8A) .
• Step 512 represents the gain of amplifier stage 33b being switched from lOdB to OdB when the received ⁇ ignal ⁇ trength reaches approximately -85dBm
• step 514 represents the gain of amplifier stage 33a being switched from lOdB to OdB when the received signal strength reaches approximately -75dBm
• ⁇ tep 516 repre ⁇ ent ⁇ the gain of amplifiers 116 and 118 being switched from 2OdB to OdB when the received ⁇ ignal ⁇ trength reache ⁇ approximately - 65dBm
• ⁇ tep 518 repre ⁇ ent ⁇ the gain of amplifier ⁇ tage 48 being switched from 22dB to -3dB when the received signal strength reaches approximately -45dBm.
• the choice of when to turn off each of the gain stage ⁇ is ba ⁇ ed on a compromise of SNR ratio and signal (i.e., gain) compression, as may occur when exce ⁇ ive signal strengths cau ⁇ e the amplifiers to saturate.
• the signal proces ⁇ or 35 demodulate ⁇ and equalize ⁇ the output 264 of the P/D converter 260. Recall that amplitude fading is addressed by the hard amplitude limiting of the phase comparator 250. Thus, the signal proces ⁇ or 35 need not provide equalization to addres ⁇ amplitude fading.
• Intersymbol interference (ISI) is a phenomena which is introduced deliberately in GSM sy ⁇ tems, by the modulator at the transmitter and is produced by each bit of energy being spread over several bit periods, both before and after the currently transmitted bit. Thi ⁇ energy spreading is the result of the impulse respon ⁇ e of the Gau ⁇ sian filter at the modulator.
• the equalizer of the signal proces ⁇ or 35 addre ⁇ ses ISI in order to prevent degradation in the bit error rate (BER) caused by a reduction in the SNR of the receiver.
• BER bit error rate
• ISI equalization is achieved with a decision-feedback equalization (DFE) approach.
• DFE decision-feedback equalization
• a functional block diagram of an embodiment of the signal proce ⁇ or 35 for use in non-mobile receiver applications is shown.
• the P/D converter 260 provides the count value signal 264 repre ⁇ entative of the period between con ⁇ ecutive zero crossing ⁇ of the IF ⁇ ignal 37 to an integrator 580 of the ⁇ ignal proce ⁇ or 35.
• the count value signal 264 is integrated over a one bit time interval T b as provided to the integrator by a signal 584.
• ISI equalization is performed by summing the integrated signal 581 with a DFE ⁇ ignal 583 generated in a manner described below.
• a data slicer 586 determine ⁇ whether the ⁇ ummation signal 585 represents the transmission of a one or a zero over the bit time T b .
• the output signal 587 of the data slicer 586 represent ⁇ the recovered, tran ⁇ mitted bit.
• a scale factor ⁇ is determined in accordance with whether the output signal 587 is a one or zero.
• the P/D count value signal generated in respon ⁇ e to a mark (logic 1) or a ⁇ pace (logic 0) condition at the modulator (i.e., tran ⁇ itter) ha ⁇ a non ⁇ linear transfer function due to the l/f or period measurement.
• the center IF frequency is approximately 203KHz corresponding to a P/D count of approximately 246, a +67KHz deviation equals an IF frequency of 270KHz and a P/D count value of approximately 184, whereas a -67KHz deviation at the transmitter results in an IF frequency of 135KHZ and a P/D count value of approximately 369.
• ⁇ is set to -0.67 and, if the transmitted bit is a zero, then ⁇ is set to +1.
• the scale factor a is set equal to the previous scale factor value .,.
• the previous scale factor ct_ is then summed with a DFE constant e 592 by a multiplier 594 to provide the DFE signal 583.
• the DFE constant e is derived from the transfer ratio of the l/f P/D process (i.e., the non-linear transfer function).
• the ISI equalization provided by multiplying the scale factor . j and the DFE constant e implements a feedback filter 596, which may be referred to as a postcur ⁇ or equalizer. A ⁇ ⁇ uch, the feedback filter 596 eliminate ⁇ the postcursor portion of the ISI (i.e., the interference from past data symbols) .
• a flow diagram of step ⁇ performed by the ⁇ ignal processor of Fig. 10 for demodulation and ISI equalization is ⁇ hown.
• the signal proce ⁇ or 35 demodulate ⁇ received ⁇ ignal ⁇ by integrating the difference between a currently detected P/D count value signal and a previously detected P/D count value signal over a single bit time. To this end, the signal proces ⁇ or 35 wait ⁇ for an interrupt IRQ2 to occur in step 600. Interrupt IRQ2 is generated by the " DA output signal 406 of the P/D converter 260 at each detected zero crossing.
• a timer is read to determine the time ET 2 that has lapsed since a prior IRQ2 interrupt was received and the time ET 2 stored. Also in step 604, the timer is loaded with a count of 100 and restarted. Note that in the illustrative embodiment, one bit time is equal to 80 machine cycles, so the timer is loaded with a value greater than one bit time.
• the most recently computed difference value d(x) is stored as a previou ⁇ difference value d(x)., in ⁇ tep 608.
• the current count value signal 264 from the P/D converter 260 i.e., N
• the current count value N is then provided by the count value signal 264 from the P/D converter 260 in step 616.
• Step ⁇ 620-648 collectively corre ⁇ pond to the operation of the integrator 580 in Fig. 10.
• the difference value d(x) i ⁇ calculated by ⁇ ubtracting 246 from the value N.
• An intermediate integrator value f(x)' i ⁇ then calculated in step 624 by multiplying the previous difference value d(x)_ ! by the timer value ET 2 .
• the intermediate integrator value f(x)' is then updated in step 628 by incrementing the intermediate integrator value f(x)' by a previou ⁇ intermediate integrator value f(x)'.,.
• step 632 the intermediate integrator value f(x)' is stored as the previous intermediate integrator value f(x) '., .
• the Mask Off IRQ0 box 634 indicates that the serie ⁇ of sequential steps 604 through 632 is fully executed once entered.
• the ⁇ ignal proce ⁇ or 35 then idles in step 636 and waits for a subsequent interrupt IRQ0 in step 640.
• Interrupt IRQ0 is provided by the 270.833Khz recovered clock signal 482 (Fig. 8A) .
• ⁇ tep 644 i ⁇ performed in which the timer i ⁇ again read and the lap ⁇ ed time ET 0 since the prior IRQO interrupt stored. The timer is also loaded with a count of 100 and restarted.
• step 648 the integrator value f(x) is updated by adding the intermediate integrator value f(x)' to the product of the difference value d(x) and the timer value ET 0 .
• step 652 the previous intermediate integrator value f(x)' . , i ⁇ reset to zero.
• the Mask Off IRQ2 box 654 indicates that sequential step ⁇ 640 through 652 are completed once the sequence is entered.
• ⁇ tep 656 the integrator value f(x) is stored as the value I.
• Step 660 implements the one bit adaptive DFE equalization discussed above in conjunction with Fig. 10 by which the integrated signal 581 (Fig. 10) is summed with the DFE signal 583.
• the value I is summed with the product of the DFE constant e and a previous scale factor ⁇ .,.
• the data slicer 586 of Fig. 10 i ⁇ implemented in ⁇ tep ⁇ 664 and 680.
• ⁇ tep 664 it is determined whether the value I is greater than or equal to zero. In the event that I is greater than or equal to zero, then the tran ⁇ mitted bit i ⁇ determined to be a zero. Alternatively, if it is determined in step 680 that I is le ⁇ than zero, then the tran ⁇ mitted bit is determined to be a one.
• step 668 is next performed, in which the scale factor ⁇ is set to -.67.
• ⁇ tep 684 i ⁇ performed in which the ⁇ cale factor ⁇ of set to +1.
• step 672 is performed in which the data signal 462 (Fig. 8A) i ⁇ provided to the one bit latch 458.
• the previou ⁇ scale factor is then set to the current scale factor in step 676, following which the signal proces ⁇ or 35 idles again in step 636.
• the ⁇ ignal proce ⁇ or 35 In mobile receiver application ⁇ , in addition to ISI equalization and demodulation, the ⁇ ignal proce ⁇ or 35 additionally equalizes to addre ⁇ time di ⁇ per ⁇ ion.
• Time dispersion is a phenomena whereby change ⁇ in the impul ⁇ e response of the mobile channel cause an increased BER.
• an adaptive multipath equalization technique is used to address both time dispersion and ISI equalization.
• the signal processor 35 In order to implement adaptive multipath equalization, in mobile receiver applications, it may be desirable to implement the signal processor 35 with a DSP. In non-mobile receiver applications however, the ⁇ ignal processor 35 may be implemented with hardware logic. This is the because the adaptive equalization used to address time disper ⁇ ion is not neces ⁇ ary, thereby greatly ⁇ implifying the functionality of the ⁇ ignal proce ⁇ or 35.
• the P/D converter 260 provides the count value signal 264 representative of the period between consecutive zero crossings of the IF signal to an integrator 702.
• Integrator 702 integrate ⁇ the count value signal 264 over a one bit time interval T b as provided by a signal 704.
• the integrated signal 708 is proces ⁇ ed by a feedforward filter 710.
• the feedforward filter 710 may be referred to a ⁇ a precur ⁇ or equalizer and perform ⁇ the function of a whitening matched filter.
• the feedforward filter 710 al ⁇ o equalize ⁇ the precursor portion of the ISI (i.e., interference from future data symbols) .
• the feedforward filter 710 includes a plurality of delay circuits 712 0 , 712,, 712 2 , ...712 n and corresponding feedforward coefficients g 0 , g,, g 2 , ...g n .,.
• Each of the coefficients g 0 , g,, g 2 , ...g n ., is multiplied in a multiplier 714 0 , 714,, 714 2 , ...714 n ., by a re ⁇ pective output ⁇ ignal 718 0 , 718,, 718 2 , ...718-,- !
• the ⁇ ignal ⁇ 720 0 , 720,, 720 2 , ...720 n. , provided by multipliers 714 0 , 714,, 714 2 , ...714 n ., are coupled to a ⁇ ummation circuit 724 where they are summed with output signals 714 0 , 714,, 714 2 , ...714 n _, from a feedback filter 750.
• the output of the summation circuit 724 is coupled to a data slicer 728 for determination of the tran ⁇ mitted bit at each bit time T b and to a summation circuit 730.
• Summation circuit 730 in conjunction with a coefficient adaptation circuit 739 and a stored training sequence code 738, adaptively determines optimum values for the feedforward coefficients g 0 , g,, g 2 , g 3 ...g n ., and feedback DFE coefficient ⁇ e 0 , e,, e 2 , e 3 ...e m .
• the training sequence code 738 is specified by the GSM specification for the received time slot and, in particular, is specified by the 1994 European Telecommunications Standards In ⁇ titute (ETSI) Standard GSM 05.02 specification which is incorporated herein by reference.
• every received GSM burst contains 156.25 bits, of which 26 bits comprise a training sequence.
• the summation circuit 730 strips the training sequence from the input to the data ⁇ licer 728 and correlate ⁇ the training sequence to the stored training ⁇ equence code 738.
• the re ⁇ ult of thi ⁇ correlation i ⁇ provided to the coefficient adaptation circuit 739 which iteratively ⁇ ets the feedforward coefficients g 0 , g,, g 2 , g 3 ...g tone-, and feedback DFE coefficients ⁇ o, ei, e 2 , e 3 ...e m and compares the training sequence stripped from the resulting input to the data slicer 728 to the known training ⁇ equence code 738 until an optimum match is achieved.
• the feedback filter 750 like the feedback filter 596 of Fig. 10, eliminates the postcur ⁇ or portion of ISI, albeit in an adaptive manner.
• the feedback filter 750 include ⁇ a plurality of delay circuit ⁇ 740 0 , 740,, 740 2 , ...740 n , the output ⁇ of which provide re ⁇ pective scale factor value ⁇ ⁇ . ,, ⁇ .2 , ⁇ .3 , ... . n .
• the ⁇ cale factor ⁇ ⁇ .,, ⁇ _ 2 , ⁇ _ 3 , ... ⁇ _ n are multiplied in multipliers 742,, 742 2 , 742 3 , ...742 m by corresponding feedback coefficients e,, e 2 , e 3 , ...e m .
• the signals 744,, 744 2 , 744 3 , ...744 m provided by multipliers 742,, 742 2 , 742 3 , ...742 m are coupled to the summation circuit 724 where they are summed with output signals 714 0/ 714,, 714 2 , ...714.,., from the feedforward filter 710.
• step 800 the signal processor 35 waits for an interrupt IRQ2 which is generated by the ⁇ DA output signal 406 of the P/D converter 260.
• step 804 a timer is read to determine the time ET 2 that has lapsed since a prior IRQ2 interrupt was received. The time ET 2 is stored and the timer i ⁇ loaded with a count of 100 and re ⁇ tarted.
• step 808 the current difference value d(x) is stored as the previous difference value d(x).,. Thereafter, the current count value signal 264 from the P/D converter 260 is stored as a value N. A new difference value is then computed in step 816 by subtracting 246 from the value N. An intermediate integrator value f(x)' i ⁇ then computed in ⁇ tep 820 by multiplying the previou ⁇ difference value d(x)., by the timer value ET . In a ⁇ ub ⁇ equent ⁇ tep 824, the intermediate integrator value f(x)' i ⁇ incremented by the previou ⁇ intermediate integrator value f(x)'.,.
• the current intermediate integrator value f(x)' is set to the previou ⁇ intermediate integrator value f(x)'.,.
• the Mask Off IRQ0 box 832 indicates sequential steps 804 through 828 are completed once the sequence is entered.
• step 844 is next performed in which the timer i ⁇ again read and the lap ⁇ ed time since the last IRQ0 interrupt stored as timer value ET 0 .
• the timer is also loaded with a value of 100 and restarted in step 844.
• a value I is set equal to the sum of the current integrator value f(x)' and the product of the difference value d(x) and the timer value ET 0 .
• Steps 816-848 collectively represent the operation of the integrator 702 of Fig. 12. Thereafter, the previous intermediate integrator value f(x)'., is set to zero.
• a step 860 the operation of the feedback filter 750 and the summation circuit 724 is performed by computing a value I" which is equal to the summation of the value I' and the product of each of the scale factors .,, ⁇ . 2 , ... ⁇ .n with the corresponding DFE constant e,, e 2 , ..e m .
• the value m 2.
• the value I ' ' represent ⁇ the output ⁇ ignal of the ⁇ ummation circuit 724 provided to the data slicer 728 (Fig. 12) .
• step 864 if it i ⁇ determined that the value I' ' is greater than or equal to zero, then the transmitted bit is a zero.
• step 872 if it i ⁇ determined that the value I" i ⁇ le ⁇ than zero, then the tran ⁇ mitted bit i ⁇ a one.
• the ⁇ cale factor value ⁇ i ⁇ then computed in steps 868 and 876. In particular, if the transmitted bit is a zero, then the scale factor value ⁇ i ⁇ ⁇ et to -1 in step 868.
• the scale factor value ⁇ is set to +1 in ⁇ tep 876. Thereafter, in ⁇ tep 890, the data ⁇ ignal 462 (Fig. 8A) i ⁇ provided to the one bit latch 458.
• IRQO box 900 indicate ⁇ that the ⁇ equence of steps 840 through 896 is completed once entered.
• the receiver 10 described herein is readily adaptable for use in receiving RF signals modulated by various analog and digital scheme ⁇ .
• the required modification ⁇ to the receiver include modifying the bandwidth of the RF BPF 18, the down converter frequency (i.e., the frequency of the LO ⁇ ignal ⁇ 60 and 62 in Fig. 2), the bandwidth of the IF LPF 30 and the demodulation technique employed by the signal proces ⁇ or 35.

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